CN117238947A - IGBT cell optimization method and IGBT cell structure - Google Patents
IGBT cell optimization method and IGBT cell structure Download PDFInfo
- Publication number
- CN117238947A CN117238947A CN202311046331.4A CN202311046331A CN117238947A CN 117238947 A CN117238947 A CN 117238947A CN 202311046331 A CN202311046331 A CN 202311046331A CN 117238947 A CN117238947 A CN 117238947A
- Authority
- CN
- China
- Prior art keywords
- wafer
- type
- igbt
- contact hole
- igbt cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000005457 optimization Methods 0.000 title claims abstract description 29
- 238000002347 injection Methods 0.000 claims abstract description 32
- 239000007924 injection Substances 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 210000000746 body region Anatomy 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 3
- 238000009826 distribution Methods 0.000 abstract description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The application discloses an IGBT cell optimization method and an IGBT cell structure, which comprise the steps that an N-type source region is not doped at a corner when an IGBT is prepared, so that current does not flow through the corner; the wafer comprises a wafer body, a groove main body arranged on the surface of the wafer body, an N-type injection region injected on the surface of the wafer body, a contact hole body arranged on the surface of the wafer body and a metal region arranged on the surface of the wafer body. According to the IGBT cell optimization method and the IGBT cell structure, the square grooves are added on the wafer, so that voltage reduction in the on state can be reduced, the on performance is improved, meanwhile, doping of an N-type source region is not carried out at the corners, the current concentration phenomenon is reduced, the turn-off capability and the voltage withstand performance of the device are improved, the uniform current distribution is ensured by optimizing the electrode structure, the heat dissipation of the device is reduced, and the turn-off capability of the square groove cell is improved by enabling the current not to flow through the corners of the square groove cell, namely, the N-type source region is not injected at the corners.
Description
Technical Field
The application relates to the technical field of semiconductor power devices, in particular to an IGBT cell optimization method and an IGBT cell structure.
Background
IGBTs are a common power semiconductor device, and combine the advantages of Field Effect Transistors (FETs) and bipolar transistors (BJTs), in order to reduce the turn-on voltage drop of the IGBTs, it is a common practice to use square trench cell structures, but the currents at the four corners of the square trench cell structures are concentrated, so that the turn-off capability of the IGBTs is reduced.
While the strip-shaped groove cell structure is adopted, the turn-off capability of the IGBT is not reduced, if the groove spacing of the cell is kept unchanged, the turn-on voltage drop is generally increased; however, with smaller trench spacing, the miller capacitance Cres of the IGBT device increases and wafer processing also risks warping.
To overcome this difficulty, the following technical hurdles are considered: complicated structural optimization requires finding the best balance among on-voltage drop, turn-off capability and current uniformity; manufacturing cost and scalability, finding economically viable solutions, and ensuring scalability of the manufacturing process; numerical simulation and optimization techniques, performing accurate numerical simulation and optimization may require significant computational resources and efficient algorithms; reliability and durability, adequate reliability testing and life assessment are required to ensure adequate stability of the device over long periods of use.
Overcoming these technical obstacles requires extensive research and development effort involving a number of aspects of design, materials, manufacture, and testing.
Disclosure of Invention
This section is intended to outline some aspects of embodiments of the application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the application and in the title of the application, which may not be used to limit the scope of the application.
The present application has been made in view of the above-mentioned problems with the existing IGBT cell optimization methods.
Therefore, the application aims to provide an IGBT cell optimization method, which aims to: the problem of current square slot IGBT cell structure turn-off capability decline is solved.
In order to solve the technical problems, the application provides the following technical scheme: including where the N-type source region is undoped at the corners during IGBT fabrication so that current does not flow through the corners.
As a preferable scheme of the IGBT cell optimization method of the application, wherein: the preparation method of the IGBT comprises the following steps of,
preparing an N-type silicon wafer substrate and forming a silicon oxide layer;
forming square grooves on the surface of the wafer by photoetching and etching;
injecting doped P-type impurities on the wafer, and pushing the doped P-type impurities to form a P-type body region;
injecting doped N-type impurities on the wafer, and pushing to form an N-type source region; undoped N-type sources at the corners;
depositing a SiO medium layer;
forming a contact hole on the surface of the wafer through photoetching and etching;
implanting P-type impurities on the wafer and annealing;
depositing a metal film on the surface of the wafer, and photoetching to form an electrode structure;
dicing and packaging the wafer to form the finished IGBT device.
As a preferable scheme of the IGBT cell optimization method of the application, wherein: the preparation method of the IGBT specifically comprises the following steps of,
growing a silicon oxide layer on an N-type silicon wafer;
forming square grooves on the surface of the wafer by utilizing photoetching and etching processes;
doping P-type elements on the wafer to form a P-type body region;
doping N-type material on the wafer to form an N-type source region;
an N-type source region is not doped at the corner, and the electrode structure is optimized to improve the turn-off capability;
depositing a SiO medium layer;
forming a contact hole on the surface of the wafer by utilizing photoetching and etching processes;
injecting a P-type element into the contact hole and annealing;
depositing a metal film on the surface of the wafer, and photoetching to form an electrode structure;
dicing and packaging the wafer to form the finished IGBT device.
As a preferable scheme of the IGBT cell optimization method of the application, wherein: the position and the shape of the square groove are defined on the surface of the wafer through photoetching, and the square groove is etched at the defined position by using an etching process, so that the shape and the size of the groove are ensured.
As a preferable scheme of the IGBT cell optimization method of the application, wherein: at the corner of the square groove cell structure, doping of an N-type source region is not carried out, so that current does not flow through the corner; and depositing a metal film on the surface of the wafer to form an electrode structure.
As a preferable scheme of the IGBT cell optimization method of the application, wherein: the contact hole is contacted with the N-type injection region, the depth of the contact hole is deeper than that of the N-type injection region, and the depth is 0.4um-1um.
The IGBT cell optimization method has the beneficial effects that: by adding square grooves on the wafer, the voltage reduction in the on state can be reduced, the on performance is improved, meanwhile, the doping of an N-type source region is not carried out at the corner, the current concentration phenomenon is reduced, the turn-off capability and the voltage resistance of the device are improved, and the reliability and the service life are improved.
The present application has been made in view of the above-described problems with the existing IGBT cell structure.
Accordingly, the present application aims to provide an IGBT cell structure, which aims to: the problem of the shutdown capability decline of the conventional square groove IGBT cell structure is solved.
In order to solve the technical problems, the application provides the following technical scheme: including that the N-type source region is not implanted at the corner of the wafer body.
As a preferable scheme of the IGBT cell structure of the application, wherein: the wafer comprises a wafer body, a groove main body arranged on the surface of the wafer body, an N-type injection region injected on the surface of the wafer body, a contact hole body arranged on the surface of the wafer body and a metal region arranged on the surface of the wafer body.
As a preferable scheme of the IGBT cell structure of the application, wherein: the contact hole body is contacted with the N-type injection region, and the depth of the N-type injection region is smaller than that of the contact hole body.
As a preferable scheme of the IGBT cell structure of the application, wherein: the depth of the contact hole body is deeper than that of the N-type injection region, and the depth of the contact hole body is 0.4um-1um;
the distance between the contact hole body and the groove body is 0.2um-1.5um.
The IGBT cell structure has the beneficial effects that: the turn-off capability of the square trench cell is improved by not allowing current to flow through the corners of the square trench cell, i.e., without N-type source region injection at the corners.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
fig. 1 is a schematic flow chart of an IGBT cell optimization method of the present application.
Fig. 2 is a schematic diagram of a trench type of an IGBT cell optimization method and an IGBT cell structure according to the present application.
Fig. 3 is a schematic diagram of an n+ injection region of an IGBT cell structure and an IGBT cell optimization method according to the present application.
Fig. 4 is a schematic diagram of an emitter contact hole of an IGBT cell structure according to the present application.
Fig. 5 is a schematic diagram of a metal area emission hole of an IGBT cell structure according to the present application.
Fig. 6 is a schematic diagram of an analysis structure of an IGBT cell structure according to the IGBT cell optimization method of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Further, in describing the embodiments of the present application in detail, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of description, and the schematic is only an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Example 1
Referring to fig. 1, in a first embodiment of the present application, an IGBT cell optimization method is provided, which includes not doping N-type source regions at corners of square cells to prevent current from flowing through the corners when square IGBTs are fabricated.
The preparation method of the square IGBT cell comprises the following steps:
preparing an N-type silicon wafer substrate and forming a silicon oxide layer;
forming square grooves on the surface of the wafer by photoetching and etching;
injecting doped P-type impurities on the wafer, and pushing the doped P-type impurities to form a P-type body region;
injecting doped N-type impurities on the wafer, and pushing to form an N-type source region;
undoped N-type sources at the corners;
depositing a SiO medium layer;
in the use process, because in the traditional square groove IGBT cell structure, the current at the corner can be concentrated, so that the stress and the temperature of the area are increased, the turn-off capability of the device is reduced, and the current does not flow through the corner by not doping the N-type source region at the corner, so that the current concentration phenomenon is reduced, the turn-off capability of the device is improved, the complex problem of optimizing a current flow path is solved, and the current can be uniformly distributed in the whole cell structure.
Forming a contact hole on the surface of the wafer through photoetching and etching;
the square groove IGBT cell structure reduces the conduction voltage drop of the active area in unit area during conduction by increasing the channel width and fully utilizing the area of the active area, but the optimization can lead IGBT current to be concentrated at the corners of the square cell, so that the corners are damaged first.
Implanting P-type impurities on the wafer and annealing;
by solving the problem that current distribution is uneven in the preparation and processing processes of materials, the uniform flow of current in a cell structure is ensured by optimizing an electrode structure.
Depositing a metal film on the surface of the wafer, and photoetching to form an electrode structure;
dicing and packaging the wafer to form the finished IGBT device.
Further, in order to apply the square trench IGBT cell structure to actual production, the manufacturing process of the device must be compatible with existing processes, and can meet the requirements of mass production.
After the design of the square groove IGBT cell structure is realized, strict performance test and reliability verification are required, the test result must prove the reliability and stability of the device under the conditions of high voltage, high current and high temperature, and meanwhile, the long-term stability of the device must be evaluated to ensure that the device has lasting performance in practical application.
Example 2
Referring to fig. 1, a second embodiment of the present application is shown, which is different from the first embodiment in that: the method is specifically optimized.
Preparing a required material, such as N-type silicon, preparing an N-type silicon wafer by a crystal growth technology, and generating a silicon oxide layer;
defining the position and the shape of a square groove on the surface of a wafer by adopting a photoetching technology, and etching the square groove at the defined position by adopting an etching process to ensure that the shape and the size of the groove meet the design requirements;
a silicon oxide layer is formed on the wafer surface by chemical oxidation or other methods for insulating and dielectric layer formation.
Doping into P-type element on the wafer, pushing to form P-type body region, doping N-type material on the wafer, pushing to form N-type source region;
at the corners of the square groove cell structure, the doping of the N-type source region is not carried out, so that current does not flow through the corners, the current concentration phenomenon is reduced, the turn-off capability of the cell is improved, the electrode structure is optimized to improve the turn-off capability, the current is ensured to be uniformly distributed, the problem of current concentration in other areas is avoided, namely, at the corners of the square groove cell structure, the doping of the N-type source region is not carried out, the current does not flow through the corners, and meanwhile, the SiO medium layer is deposited;
defining the position and the shape of a contact hole on the surface of a wafer by adopting a photoetching technology, and etching the contact hole at the defined position by using an etching process to ensure that the shape and the size of the contact hole meet the design requirements;
and injecting a P-type element into the contact hole, annealing to form an injection region, depositing a metal film on the surface of the wafer, and photoetching to form an electrode structure.
The step can form an N-type or P-type injection region near the contact hole by adopting a mask and ion injection technology, so that the injection region is ensured to be properly connected with the doped region of the wafer, and current control is realized;
and dicing and packaging the manufactured wafer, and forming the finished IGBT device by adopting proper packaging materials and processes.
The contact hole is contacted with the N-type injection region, and the depth of the contact hole is deeper than that of the N-type injection region and is 0.4um-1um.
The rest of the structure is the same as that of embodiment 1.
Example 3
Referring to fig. 2 to 6, for a third embodiment of the present application, there is provided an IGBT cell structure including: the N-type source region is not implanted at the corners of the wafer body 100.
Further, compared to embodiment 2, the position and shape of the trench body 200 are defined on the wafer body 100 by photolithography, and the trench body 200 is etched at the originally located position and shape by etching process, so as to ensure the shape of the trench body 200.
The wafer body 100 defines the position and shape of the contact hole body 400 by photolithography, and etches the contact hole body 400 at the originally positioned position and shape by using the etching process, so as to ensure the shape of the contact hole body 400.
The contact hole body 400 is a metallized hole on the surface of the square IGBT cell, and is used for connecting an external circuit with the internal structure of the IGBT, and the electrode can be electrically connected with different areas of the square IGBT cell through the contact hole body 400.
By forming the N-type implant region 300 at the contact hole body 400 using a mask and ion implantation technique, current control is achieved by ensuring that the N-type implant region 300 is properly connected to the doped region of the wafer body 100.
In the square IGBT cell, the N-type injection region 300 is a region formed between the P-type and N-type materials, and the P-type materials are usually injected into the N-type region to form an N-P-N structure, so that the N-type injection region 300 plays an important role in determining the turn-on capability and turn-off capability of the square IGBT cell during the operation of the IGBT.
A metal film is deposited on the surface of the wafer body 100 to form a metal region 500 of the electrode structure.
The contact hole body 400 contacts the N-type implant region 300, and the depth of the N-type implant region 300 is smaller than the depth of the contact hole body 400.
In square IGBT devices, the contact hole body 400 generally does not directly pass through the N-type injection region 300, and the contact hole body 400 is generally designed and manufactured on the surface of the N-type injection region 300, rather than in the interior thereof, so as to ensure that the contact hole body 400 can establish electrical connection with a metallization layer or a doped region on the surface of the N-type injection region 300, thereby effectively connecting the electrode with the N-type injection region 300, and realizing control over the N-type injection region 300.
The relationship between the contact hole body 400 and the N-type injection region 300 is important in the manufacture of the IGBT device, and the position and layout of the contact hole body 400 must be precisely designed to ensure that the N-type injection region 300 and other critical regions can be properly contacted in the internal structure of the IGBT device, and the position and size of the contact hole body 400 directly affect the current transmission and control between the electrode and the N-type injection region 300, the gate and other regions, thereby affecting the performance and characteristics of the IGBT.
Therefore, referring to fig. 6, the distance between the wafer body 100, that is, the trench body 200 and the contact hole body 400 provided on the wafer, can be set to be in the range of 0.2um to 1.5um, while the trench body 200 passes through the P-type body region 600 and the wafer body 100, the contact hole body 400 is provided on the P-type body region 600 and the wafer body 100, and after the wafer body 100 forms the N-type injection region 300 through the contact hole body 400, deposition of a metal film is performed on the surface of the wafer body 100 to form an electrode structure, metal is coated at the trench body 200 to form the P-type anode region 700 of the trench body 200 region, and simultaneously the metal region 500 of the electrode structure is also formed;
the P-type body region 600 forms a P-N junction with the N-type implant region 300 as part of forming a P-N structure.
Further, the depth of the contact hole body 400 needs to be set to be deeper than the depth of the N-type implantation region 300, and the depth of the contact hole body 400 is 0.4um to 1um.
The contact hole body 400 is metallized to form an electrode structure so that the electrode can properly contact the various regions to achieve effective control and operation of the IGBT, whereas in a normal IGBT device the contact hole typically does not pass through the implanted region, and the contact hole is typically designed and fabricated at the surface of the implanted region rather than inside it.
In order to avoid the current concentration at the corners, the current can be prevented from flowing through the corners, the saturation voltage drop of the IGBT can be reduced, the reverse turn-off capability of the IGBT is not reduced, and the turn-off capability of the square groove cell is improved by preventing the current from flowing through the corners of the square groove cell, namely, no N-type source region is injected at the corners.
The square grooves on the wafer are increased, so that voltage reduction in a conducting state is reduced, and the conducting performance is improved; meanwhile, the doping of an N-type source region is not carried out at the corners, the phenomenon of current concentration is reduced, the turn-off capability and the voltage resistance of the device are improved, the electrode structure is optimized to ensure the current to be uniformly distributed, the heat dissipation of the device is reduced, the reliability and the service life of the device are improved, in addition, the structure also improves the power consumption performance, the power loss is reduced, the efficiency is improved, the whole manufacturing method also has better feasibility, and the method accords with the common semiconductor manufacturing process, so that the method has important application value in the design and the manufacture of IGBT devices.
The rest of the structure is the same as that of embodiment 2.
It is important to note that the construction and arrangement of the application as shown in the various exemplary embodiments is illustrative only. Although only a few embodiments have been described in detail in this disclosure, those skilled in the art who review this disclosure will readily appreciate that many modifications are possible (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, values of parameters (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the novel teachings and advantages of the subject matter described in this application. For example, elements shown as integrally formed may be constructed of multiple parts or elements, the position of elements may be reversed or otherwise varied, and the nature or number of discrete elements or positions may be altered or varied. Accordingly, all such modifications are intended to be included within the scope of present application. The order or sequence of any process or method steps may be varied or re-sequenced according to alternative embodiments. In the claims, any means-plus-function clause is intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present applications. Therefore, the application is not limited to the specific embodiments, but extends to various modifications that nevertheless fall within the scope of the appended claims.
Furthermore, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not be described (i.e., those not associated with the best mode presently contemplated for carrying out the application, or those not associated with practicing the application).
It should be noted that the above embodiments are only for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or substituted without departing from the spirit and scope of the technical solution of the present application, which is intended to be covered in the scope of the claims of the present application.
Claims (10)
1. An IGBT cell optimization method is characterized in that: the undoped N-type source region at the corners during IGBT fabrication prevents current from flowing through the corners.
2. The IGBT cell optimization method according to claim 1, characterized in that: the preparation method of the IGBT comprises the following steps of,
preparing an N-type silicon wafer substrate and forming a silicon oxide layer;
forming square grooves on the surface of the wafer by photoetching and etching;
injecting doped P-type impurities on the wafer, and pushing the doped P-type impurities to form a P-type body region;
injecting doped N-type impurities on the wafer, and pushing to form an N-type source region;
undoped N-type sources at the corners;
depositing a SiO medium layer;
forming a contact hole on the surface of the wafer through photoetching and etching;
implanting P-type impurities on the wafer and annealing;
depositing a metal film on the surface of the wafer, and photoetching to form an electrode structure;
dicing and packaging the wafer to form the finished IGBT device.
3. The IGBT cell optimization method according to claim 1 or 2, characterized in that: the preparation method of the IGBT specifically comprises the following steps of,
growing a silicon oxide layer on an N-type silicon wafer;
forming square grooves on the surface of the wafer by utilizing photoetching and etching processes;
doping P-type elements on the wafer to form a P-type body region;
doping N-type material on the wafer to form an N-type source region;
an N-type source region is not doped at the corner, and the electrode structure is optimized to improve the turn-off capability;
depositing a SiO medium layer;
forming a contact hole on the surface of the wafer by utilizing photoetching and etching processes;
injecting a P-type element into the contact hole and annealing;
depositing a metal film on the surface of the wafer, and photoetching to form an electrode structure;
dicing and packaging the wafer to form the finished IGBT device.
4. The IGBT cell optimization method according to claim 3, wherein: the position and the shape of the square groove are defined on the surface of the wafer through photoetching, and the square groove is etched at the defined position by using an etching process, so that the shape and the size of the groove are ensured.
5. The IGBT cell optimization method according to claim 4, wherein: at the corner of the square groove cell structure, doping of an N-type source region is not carried out, so that current does not flow through the corner;
and depositing a metal film on the surface of the wafer to form an electrode structure.
6. The IGBT cell optimization method according to claim 4 or 5, characterized in that: the contact hole is contacted with the N-type injection region, the depth of the contact hole is deeper than that of the N-type injection region, and the depth is 0.4um-1um.
7. An IGBT cell structure, characterized in that: comprising the IGBT cell optimization method according to any one of claims 1 to 6, further comprising,
the N-type source region is not implanted at the corner of the wafer body (100).
8. The IGBT cell structure of claim 7 wherein: comprising the steps of (a) a step of,
the wafer comprises a wafer body (100), a groove main body (200) arranged on the surface of the wafer body (100), an N-type injection region (300) injected on the surface of the wafer body (100), a contact hole body (400) arranged on the surface of the wafer body (100) and a metal region (500) arranged on the surface of the wafer body (100).
9. The IGBT cell structure of claim 8 wherein: the contact hole body (400) is in contact with the N-type injection region (300), and the depth of the N-type injection region (300) is smaller than the depth of the contact hole body (400).
10. The IGBT cell structure of claim 9 wherein: the depth of the contact hole body (400) is deeper than that of the N-type injection region (300), and the depth of the contact hole body (400) is 0.4um-1um;
the distance between the contact hole body (400) and the groove main body (200) is 0.2um-1.5um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311046331.4A CN117238947A (en) | 2023-08-18 | 2023-08-18 | IGBT cell optimization method and IGBT cell structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311046331.4A CN117238947A (en) | 2023-08-18 | 2023-08-18 | IGBT cell optimization method and IGBT cell structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117238947A true CN117238947A (en) | 2023-12-15 |
Family
ID=89093824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311046331.4A Pending CN117238947A (en) | 2023-08-18 | 2023-08-18 | IGBT cell optimization method and IGBT cell structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117238947A (en) |
-
2023
- 2023-08-18 CN CN202311046331.4A patent/CN117238947A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5751024A (en) | Insulated gate semiconductor device | |
| US6001678A (en) | Insulated gate semiconductor device | |
| JP3288218B2 (en) | Insulated gate semiconductor device and method of manufacturing the same | |
| US6768168B1 (en) | Insulated gate semiconductor device with low on voltage and manufacturing method thereof | |
| JP3995219B2 (en) | Insulated gate bipolar transistor with built-in diode and manufacturing method thereof | |
| US7880200B2 (en) | Semiconductor device including a free wheeling diode | |
| CN108682624B (en) | Manufacturing method of IGBT chip with composite gate | |
| JP2001326353A (en) | Semiconductor device | |
| CN103872108B (en) | IGBT structure and preparation method thereof | |
| CN116207146A (en) | Softness modulation type IGBT device, preparation method thereof and chip | |
| CN113488525B (en) | Super-junction EA-SJ-FINFET device with charge accumulation effect | |
| CN117238947A (en) | IGBT cell optimization method and IGBT cell structure | |
| JP2008053610A (en) | Insulated-gate bipolar transistor | |
| JPH10335630A (en) | Semiconductor device and its manufacture | |
| CN112117327B (en) | IGBT device and manufacturing process thereof | |
| CN113130628B (en) | Semiconductor device with high robustness and preparation method thereof | |
| CN213459737U (en) | Novel power device with high dynamic latch-up resistance | |
| CN111564486B (en) | Power semiconductor device with lateral electric field pinch-off structure and method of manufacturing the same | |
| CN116454119A (en) | Fast recovery diode and preparation method thereof | |
| CN115132576A (en) | Mask structure for RC-IGBT ion implantation and manufacturing method thereof | |
| CN118841443A (en) | Cell structure of deep contact hole insulated gate bipolar transistor and manufacturing method | |
| CN114171386A (en) | Process optimization method for carrier storage groove gate bipolar transistor structure | |
| CN117352540A (en) | Semiconductor device and control method of semiconductor device and preparation method | |
| JP2023179936A (en) | Semiconductor device | |
| JP2005026392A (en) | Semiconductor device and its fabricating process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |