CN116207146A - Softness modulation type IGBT device, preparation method thereof and chip - Google Patents

Softness modulation type IGBT device, preparation method thereof and chip Download PDF

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CN116207146A
CN116207146A CN202310233712.7A CN202310233712A CN116207146A CN 116207146 A CN116207146 A CN 116207146A CN 202310233712 A CN202310233712 A CN 202310233712A CN 116207146 A CN116207146 A CN 116207146A
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type
softness
igbt device
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杨磊
刘杰
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Shenzhen Xiner Semiconductor Technology Co Ltd
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Shenzhen Xiner Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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Abstract

The utility model belongs to the technical field of power devices, a softness modulation type IGBT device and a preparation method thereof, a chip are provided, through forming the softness modulation area including N type diffusion layer and local carrier life control layer between N type field termination layer and N type drift layer, and set up the doping concentration of N type diffusion layer and be less than the doping concentration of N type field termination layer, then form positive IGBT structure and positive protective layer on N type drift layer, make when the IGBT device is in lower operating voltage, can provide the carrier at the device turn-off terminal and keep turn-off softness, reduce turn-off time and turn-off loss, and when the IGBT device is in higher operating voltage, guarantee that the depletion layer of device can cut off in N type diffusion layer, make the turn-off current of IGBT device can not take place the vibration, the current length that has when current fluctuation, the loss is big, the high risk of overvoltage invalidation is great problem of IGBT device existence at present.

Description

Softness modulation type IGBT device, preparation method thereof and chip
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a softness modulation type IGBT device, a preparation method thereof and a chip.
Background
Insulated Gate Bipolar Transistor (IGBT) has a compromise between low on-voltage drop of bipolar junction transistor (Bipolar Junction Transistor, BJT) and fast switching of Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and simple control, and is widely used in power electronic systems.
However, the IGBT device actually works in a relatively large range, for example, an IGBT with 1200V bearing capacity, the bus voltage fluctuates in the voltage range of 400V to 800V, when working at a lower voltage, the non-depletion region of the IGBT device is wide, the current tail is long, the loss is large, the system efficiency cannot reach the optimum, and when working at a higher voltage, the current of the IGBT device drops rapidly, the overshoot voltage is high, and the risk of overvoltage failure is raised.
Disclosure of Invention
The invention aims to provide a softness modulation type IGBT device, a preparation method and a chip thereof, and aims to solve the problems of long current trailing, large loss and larger overvoltage failure risk of the IGBT device when voltage fluctuation occurs.
The first aspect of the embodiments of the present application provides a softness modulation type IGBT device, the softness modulation type IGBT device including:
the N-type field termination layer and the P-type collector region are formed on the back surface of the N-type field termination layer;
the softness modulation area is formed on the front surface of the N-type field termination layer; the soft modulation region comprises an N-type diffusion layer and a local carrier life control layer, and the doping concentration of the N-type diffusion layer is smaller than that of the N-type field termination layer;
the N-type drift layer is formed on the N-type diffusion layer and is of a convex structure;
a gate dielectric layer positioned above the horizontal portion of the N-type drift layer and in contact with the raised portion of the N-type drift layer; wherein the grid dielectric layer is of a concave structure;
the polysilicon layer is formed in the groove of the grid dielectric layer;
the P-type well region is formed on the protruding part of the N-type drift layer and is in contact with the gate dielectric layer;
an N-type source region formed on the P-type well region;
the insulating medium layer is formed on the polycrystalline silicon layer and the N-type source region;
the emission metal layer is formed on the insulating medium layer and is in a convex structure, and the protruding part of the emission metal layer penetrates into the P-type well region through the insulating medium layer and the through hole on the N-type source region;
and the collector metal layer is formed on the back surface of the P-type collector region.
In one embodiment, the localized carrier lifetime control layer is formed in the N-type diffusion layer or the localized carrier lifetime control layer is formed between the N-type diffusion layer and the N-type field stop layer.
In one embodiment, the number of the local carrier lifetime control layers is plural, and the N-type diffusion layers isolate the plurality of the local carrier lifetime control layers.
In one embodiment, the distances between adjacent ones of the localized carrier lifetime control layers are equal.
In one embodiment, the localized carrier lifetime control layer has a thickness of 50nm-1um.
In one embodiment, the distance between the localized carrier lifetime control layer and the boundary of the softness modulated zone is equal to or less than 5um.
In one embodiment, the localized carrier lifetime control layer is formed by implanting hydrogen ions or helium ions into a designated region in the N-type diffusion layer.
In one embodiment, the doping concentration of the N-type field stop layer is at least 100 times the doping concentration of the N-type diffusion layer;
the doping concentration of the N-type diffusion layer is set in a gradient mode.
The second aspect of the embodiment of the application also provides a method for preparing a softness modulation type IGBT device, which comprises the following steps:
growing an N-type diffusion layer on the front surface of the N-type field termination layer; the doping concentration of the N-type diffusion layer is smaller than that of the N-type field termination layer;
growing an N-type drift layer on the N-type diffusion layer;
etching the N-type drift layer to form a groove structure on the N-type drift layer, and enabling the N-type drift layer to be in a convex structure;
forming a gate dielectric layer on the inner wall of the groove structure on the N-type drift layer, and filling a polysilicon layer in the gate dielectric layer; the grid dielectric layer is positioned above the horizontal part of the N-type drift layer and is in contact with the protruding part of the N-type drift layer;
forming a P-type well region which is in contact with the gate dielectric layer on the convex part of the N-type drift layer;
forming an N-type source region on the P-type well region;
forming an insulating medium layer on the polysilicon layer and the N-type source region;
etching the polysilicon layer and the N-type source region to form an etching groove penetrating into the P-type well region, and forming the emission metal layer in the etching groove; the emitting metal layer is in a convex structure, and the protruding part of the emitting metal layer is in contact with the P-type well region;
thinning the back surface of the N-type field termination layer, and implanting hydrogen ions or helium ions into a designated area in the N-type diffusion layer and then annealing to form a local carrier life control layer;
and forming a P-type collector region on the back surface of the N-type field termination layer, and forming a collector metal layer on the back surface of the P-type collector region.
The third aspect of the embodiment of the present application further provides a chip, where the chip includes the softness modulation type IGBT device according to any one of the embodiments above; or the chip comprises a softness modulation type IGBT device prepared by the preparation method according to any one of the embodiments.
The embodiment of the invention has the beneficial effects that:
the soft modulation region comprising the N-type diffusion layer and the local carrier life control layer is formed between the N-type field termination layer and the N-type drift layer, the doping concentration of the N-type diffusion layer is smaller than that of the N-type field termination layer, and then the front IGBT structure and the front protection layer are formed on the N-type drift layer, so that when the IGBT device is at a lower working voltage, carriers can be provided to maintain the turn-off current at the end of turn-off of the device, the turn-off softness is maintained, the turn-off time and turn-off loss are reduced, and when the IGBT device is at a higher working voltage, the depletion layer of the device is ensured to be cut off in the N-type diffusion layer, so that the turn-off current of the IGBT device cannot oscillate, and the problems of long current tailing, high loss and high overvoltage failure risk existing in the current fluctuation of the IGBT device are solved.
Drawings
Fig. 1 is a schematic structural diagram of a softness modulation type IGBT device according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of another softness-modulating IGBT device according to an embodiment of the present application.
Fig. 3 is a schematic diagram showing a doping concentration distribution along a CD dotted line of the softness modulated IGBT device of fig. 1, and an electric field distribution when subjected to a high voltage.
Fig. 4 is a schematic flow chart of a method for manufacturing a softness modulation type IGBT device according to an embodiment of the present application.
Fig. 5 is a schematic diagram of forming an N-type diffusion layer and an N-type drift layer according to an embodiment of the present application.
Fig. 6 is a schematic diagram of forming a gate dielectric layer and a polysilicon layer according to an embodiment of the present application.
Fig. 7 is a schematic diagram of forming a P-type well region according to an embodiment of the present application.
Fig. 8 is a schematic diagram of an embodiment of the present application after forming an etched trench.
Fig. 9 is a schematic diagram of forming an emissive metal layer according to an embodiment of the present application.
FIG. 10 is a schematic diagram of forming a localized carrier lifetime control layer provided in an embodiment of the present application;
fig. 11 is a schematic diagram of forming a P-type collector region and a collector metal layer according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In some high-end industrial application fields, such as photovoltaic inversion, the performance requirements on IGBTs are very high, the saturation conduction voltage (V CEsat ) And turn-off loss (E) off ) All the requirements are small, in reducing V CEsat In aspects, the trench gate IGBT structure reduces V without increasing Eoff due to reduced Junction Field-Effect Transistor (JFET) resistance CEsat Is widely applied. To reduce E off One, one (a)Generally, under the condition of ensuring voltage withstanding, the thinner and better the drift region of the IGBT is, and for achieving the purpose, an N-type field termination structure is introduced, wherein an N-type field termination layer is arranged between a P-type heavily doped collector region and an N-type drift region, and the concentration of the N-type field termination layer is higher than that of the N-type drift region. The N-type field stop layer is mainly introduced to make the N-type drift region as thin as possible under the premise of ensuring certain voltage resistance, thereby obtaining good performance.
But on the other hand, the introduction of the N-type field stop layer causes current oscillation when the N-type field stop layer is turned off at a high bus voltage. When the device is selected, the operating voltage of the IGBT does not exceed two thirds of the withstand voltage. The operating voltage of the IGBT device with 1200V bearing capacity is generally around 600V, and at most not more than 800V. Otherwise, a higher voltage class device is selected. When the IGBT is turned off, the channel is cut off, the external inductance current is unchanged, the drift layer bears voltage, and electrons and holes are ionized by internal depletion to maintain the inductance current. As the voltage applied to the drift region increases gradually, the depletion layer expands inward. Under most conditions, the electric field can be reduced to zero in the drift region, and the drift region is provided with a remaining non-depleted region, so that enough surplus minority carrier holes can still be provided at the end of the turn-off period of the IGBT to maintain the tailing current, and soft turn-off is realized. The wider the non-depleted region, the longer the tail current, the slower the turn-off and the greater the loss. The narrower the non-depleted region, the shorter the tail current, the faster the turn-off, and the smaller the turn-off loss. If the thickness of the drift region is reduced too thin, the depletion layer can extend into the N-type field stop layer at the end of turn-off, the minority carrier concentration in the N-type field stop layer is 1-2 orders of magnitude less than that of the drift region, the tailing current is not maintained, hard turn-off can occur, strong oscillation and voltage overshoot peak are caused, the safety of a system is seriously affected, and meanwhile, the turn-off loss is greatly increased due to strong oscillation.
In practical application, the IGBT device works in a relatively large range, for example, the bus voltage fluctuates in the voltage range of 400V to 800V, and when working at a lower voltage, the non-depletion region of the IGBT device is wide, the current trailing is long, the loss is large, and the system efficiency cannot reach the optimum, and when working at a higher voltage, the current of the IGBT device drops rapidly, and the problems of high overshoot voltage and the risk of overvoltage failure are solved.
In order to solve the above technical problem, an embodiment of the present application provides a softness-modulated IGBT device, as shown in fig. 1, where the softness-modulated IGBT device includes: an N-type field stop layer 103, a P-type collector region 102, a softness-modulating region (including an N-type diffusion layer 105 and a localized carrier lifetime control layer 104), an N-type drift layer 106, a polysilicon layer 107, a gate dielectric layer 108, a P-type well region 109, an N-type source region 110, an insulating dielectric layer 111, an emitter metal layer 112, and a collector metal layer 101.
In this embodiment, the P-type collector region 102 is formed on the back surface of the N-type field stop layer 103, the softness modulation region is formed on the front surface of the N-type field stop layer 103, and the softness modulation region includes an N-type diffusion layer 105 and a local carrier lifetime control layer 104, the doping concentration of the N-type diffusion layer 105 is smaller than that of the N-type field stop layer 103, the N-type drift layer 106 is formed on the N-type diffusion layer 105 and the N-type drift layer 106 has a convex structure, the gate dielectric layer 108 is located above the horizontal portion of the N-type drift layer 106, the gate dielectric layer 108 is in contact with the convex portion of the N-type drift layer 106, the gate dielectric layer 108 has a concave structure, the polysilicon layer 107 is located in the groove of the gate dielectric layer 108, the P-type well region 109 is formed on the convex portion of the N-type drift layer 106, and the P-type well region 109 is in contact with the gate dielectric layer 108, the N-type source region 110 is formed on the P-type well region 109, and the insulating dielectric layer 111 is formed on the polysilicon layer 107 and the N-type source region 110. The emission metal layer 112 is formed on the insulating dielectric layer 111, the emission metal layer 112 has a convex structure, the protruding portion of the emission metal layer 112 penetrates into the P-type well region 109 through the through holes on the insulating dielectric layer 111 and the N-type source region 110, and the collector metal layer 101 is formed on the back surface of the P-type collector region 102.
In this embodiment, a softness modulation region including the N-type diffusion layer 105 and the local carrier lifetime control layer 104 is formed between the N-type field stop layer 103 and the N-type drift layer 106, and the doping concentration of the N-type diffusion layer 105 is set to be smaller than that of the N-type field stop layer 103, then a front IGBT structure (composed of the gate dielectric layer 108, the P-type well region 109, the N-type source region 110, the insulating dielectric layer 111, and the emission metal layer 112) and a front protection layer are formed on the N-type drift layer 106, so that when the IGBT device is at a lower operating voltage, the depletion layer does not extend to the bottom of the N-type drift layer 106 at the end of device turn-off, and a region which is not depleted is still left outside the depletion region, so that the carrier lifetime control layer can be turned off, and the turn-off softness can be maintained from the container, and at the same time, electrons in the non-depletion region in the N-type drift layer 106 can flow to the local carrier lifetime control layer 104 in the form of diffusion flow out, and recombine with holes, and disappear, and a large number of holes stored in the N-type drift layer 106 can flow out to the P-type rapid region 109, so that the lifetime of the IGBT device can be turned off, and the lifetime of the IGBT device can be turned off, as long as the time is small, and the lifetime of the IGBT device can be turned off, and the device can be kept low, and the lifetime, and the device can be turned off, and the device can be very short, as long as the time, and the device can be turned off time.
In this embodiment, when the IGBT device is at a higher operating voltage, the N-type diffusion layer 105 has a wider width and a higher concentration, so that the depletion layer can be ensured to be turned off in the N-type diffusion layer 105, and when the IGBT device is turned off under a higher voltage condition, the N-type diffusion layer 105 still has a partially non-depleted region, so that minority carriers can be provided to maintain the turn-off current, and the N-type diffusion layer 105 in the IGBT device is formed by diffusing the N-type field stop layer 103 in a subsequent high temperature process, so that a very good concentration gradient can be formed (as shown in fig. 2). The turn-off current of the IGBT device is not oscillated. Meanwhile, due to the existence of the carrier service life control layer, the IGBT device can be turned off rapidly, and lower turn-off loss is maintained, so that the turn-off current of the IGBT device is ensured not to oscillate under high-voltage and low-voltage working conditions, and the problems of long current trailing, large loss and larger overvoltage failure risk existing in the current fluctuation of the IGBT device are solved.
In one embodiment, the localized carrier lifetime control layer 104 is formed in the N-type diffusion layer 105, see figure.
In one embodiment, localized carrier lifetime control layer 104 may also be formed between N-type diffusion layer 105 and N-type field stop layer 103.
In one embodiment, referring to fig. 3, the number of localized carrier lifetime control layers 104 is multiple, and the multiple localized carrier lifetime control layers 104 are separated by N-type diffusion layers 105.
In one embodiment, the distances between adjacent localized carrier lifetime control layers 104 are equal.
In one embodiment, the localized carrier lifetime control layer 104 is 50nm-1um thick.
In this embodiment, the N-type diffusion layer 105 may be formed by N-type doping of intrinsic silicon, for example, in a subsequent high temperature process of IGBT wafer fabrication, N-type impurities are diffused from the N-type field stop layer 103 to the intrinsic layer to form the N-type diffusion layer 105.
In one embodiment, the distance between the localized carrier lifetime control layer 104 and the boundary of the softness modulated zone is equal to or less than 5um.
In one embodiment, localized carrier lifetime control layer 104 is formed by implanting hydrogen ions or helium ions into designated regions in N-type diffusion layer 105.
In the present embodiment, the localized carrier lifetime control layer 104 may be formed in the N-type diffusion layer 105, and the carrier lifetime in the N-type diffusion layer 105 may range from 1 to 50 nanoseconds.
In one embodiment, the doping concentration of N-type field stop layer 103 is at least 100 times the doping concentration of N-type diffusion layer 105.
In this embodiment, the N-type diffusion layer 105 has an intrinsic structure, and the doping concentration of the N-type dopant ions in the N-type field stop layer 103 is at least 100 times that of the N-type dopant ions in the N-type diffusion layer 105.
In one embodiment, the doping concentration of the N-type dopant ions in the N-type field stop layer 103 is 1×10 15 cm -3 。
In one embodiment, the thickness of N-type diffusion layer 105 is 5-10um.
In one embodiment, the doping concentration of the N-type diffusion layer 105 is set in a gradient.
In this embodiment, N-type impurity is diffused from the N-type field stop layer 103 to the intrinsic layer to form an N-type diffusion layer 105. Therefore, the N-type diffusion layer 105 has a good N-type doping concentration gradient, and the concentration gradient can be controlled by grasping the highest temperature and diffusion time.
In one embodiment, the doping concentration of N-type dopant ions in N-type diffusion layer 105 is inversely proportional to the distance between N-type field stop layer 103.
The embodiment of the application also provides a preparation method of the softness modulation type IGBT device, and referring to fig. 4, the preparation method in the embodiment comprises steps S101 to S108.
In step S101, as shown in fig. 5, an N-type diffusion layer 105 is grown on the front surface of the N-type field stop layer 103.
In this embodiment, the N-type diffusion layer 105 may be formed by growing an N-type semiconductor material on the front surface of the N-type field stop layer 103 through a growth process, and the doping concentration of the N-type diffusion layer 105 is smaller than that of the N-type field stop layer 103.
In one embodiment, the doping concentration of the N-type field stop layer 103 is at least 100 times the doping concentration of the N-type diffusion layer 105.
In one embodiment, the thickness of the N-type diffusion layer 105 is 5um to 10um.
In one specific embodiment, the N-type field stop layer 103 may be an N-type silicon-based substrate.
In step S102, as shown in fig. 5, an N-type drift layer 106 is grown on the N-type diffusion layer 105.
Specifically, an N-type drift layer 106 may be formed by growing an N-type semiconductor material on the N-type diffusion layer 105 through a growth process.
In a specific embodiment, the thickness of the N-type drift layer 106 is greater than that of the N-type diffusion layer 105, and in particular, the growth thickness of the N-type drift layer 106 may be 75um to 100um, and the concentration of N-type dopant ions in the N-type drift layer 106 may be 1-5×10 13 。
In step S103, as shown in fig. 6, the N-type drift layer 106 is etched to form a trench structure on the N-type drift layer 106, and the N-type drift layer 106 is made to have a convex structure.
In this embodiment, a trench structure is formed on the front surface of the N-type drift layer 106 by a silicon etching process, and specifically, the etched region is located in an edge region of the front surface of the N-type drift layer 106, so that the etched N-type drift layer 106 has a convex structure.
In one specific embodiment, the cross-section of the trench structure is circular in shape, and the circular trench structure surrounds the raised portion of the N-type drift layer 106.
In step S104, a gate dielectric layer 108 is formed on the inner wall of the trench structure on the N-type drift layer 106, and a polysilicon layer 107 is filled in the gate dielectric layer 108.
In this embodiment, as shown in fig. 6, the gate dielectric layer 108 may be formed by a thermal oxidation process on the surface of the trench structure, the gate dielectric layer 108 has a concave structure, the polysilicon layer 107 is formed by filling a polysilicon material in the groove of the gate dielectric layer 108, and the cross-section shape of the polysilicon layer 107 is circular.
Specifically, the gate dielectric layer 108 is located above the horizontal portion of the N-type drift layer 106 and contacts the raised portion of the N-type drift layer 106.
In step S105, as shown in fig. 7, a P-type well region 109 is formed on the raised portion of the N-type drift layer 106 in contact with the gate dielectric layer 108.
In this embodiment, P-type doped ions (e.g., P-type impurities) are implanted into the raised portion of the N-type drift layer 106 by an ion implantation process, so that a P-type well region 109 is formed in the raised portion of the N-type drift layer 106, and the thickness of the P-type well region 109 is smaller than the thickness of the polysilicon layer 107.
In step S106, an N-type source region 110 is formed on the P-type well region 109, and an insulating dielectric layer 111 is formed on the polysilicon layer 107 and the N-type source region 110.
In this embodiment, an ion implantation process is used to implant N-type dopant ions (e.g., N-type impurities) into the P-type well 109, and then an N-type source region 110 is formed on the P-type well 109 after a high temperature annealing process.
As shown in fig. 8, an insulating dielectric layer 111 may be formed on the upper surface of the wafer by a deposition process, and the insulating dielectric layer 111 covers the polysilicon layer 107 and the N-type source region 110, and wraps the polysilicon layer 107 together with the gate dielectric layer 108.
In step S107, the polysilicon layer 107 and the N-type source region 110 are etched to form an etched trench deep into the P-type well region 109, and an emission metal layer 112 is formed in the etched trench.
In this embodiment, as shown in fig. 8, an etching process is used to form an etching trench 201 penetrating into the P-type well region 109 in the central region on the polysilicon layer 107 and the N-type source region 110, then a metal deposition process is used to deposit a metal material on the upper surface of the device, and the metal material is etched to remove the excess metal material to form an emission metal layer 112, where the emission metal layer 112 has a convex structure, and the convex portion of the emission metal layer 112 contacts the P-type well region 109, as shown in fig. 9.
In step S108, as shown in fig. 10, the back surface of the N-type field stop layer 103 is thinned, and hydrogen ions or helium ions are implanted into a specified region in the N-type diffusion layer 105 and then annealed to form the localized carrier lifetime control layer 104.
In this embodiment, the thickness of the N-type field stop layer 103 is determined according to the pressure-resistant and reliability requirements, then after the back surface of the N-type field stop layer 103 is thinned, hydrogen or helium ions are implanted into a designated area by using a high-energy ion implantation device, and annealing is performed at 320-340 ℃ to form a local lifetime control layer.
In step S109, as shown in fig. 11, a P-type collector region 102 is formed on the back surface of the N-type field stop layer 103, and a collector metal layer 101 is formed on the back surface of the P-type collector region 102.
In this embodiment, P-type impurities may be implanted into the back surface of the N-type field stop layer 103 and annealed to form the P-type collector region 102, and then the back collector metal layer 101 may be formed by evaporation or sputtering.
In one specific application embodiment, the Ni/Ti/Ni/Ag stack metal may be deposited as the collector metal layer 101 on the back side of the device by depositing the Ni/Ti/Ni/Ag stack metal as the emitter metal layer on the front side of the device.
In one embodiment, the gate metal layer may be formed by forming a gate contact hole in the insulating dielectric layer 111 to communicate to the polysilicon layer 107 and filling a metal material in the gate contact hole.
The embodiment of the application also provides a chip, and the chip in the embodiment comprises any one of the softness modulation type IGBT devices.
In another embodiment, the chip may further include a softness-modulated IGBT device fabricated by any of the fabrication methods described above.
In this embodiment, the chip includes a chip substrate, and one or more soft modulation type IGBT devices are disposed on the substrate, where the soft modulation type IGBT devices may be prepared by the preparation method in any of the above embodiments, or the soft modulation type IGBT devices in any of the above embodiments may be disposed on the chip substrate.
In a specific application embodiment, other related semiconductor devices can be integrated on the chip substrate to form an integrated circuit with the soft modulation type IGBT device.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The embodiment of the invention has the beneficial effects that:
the soft modulation region comprising the N-type diffusion layer and the local carrier life control layer is formed between the N-type field termination layer and the N-type drift layer, the doping concentration of the N-type diffusion layer is smaller than that of the N-type field termination layer, and then the front IGBT structure and the front protection layer are formed on the N-type drift layer, so that when the IGBT device is at a lower working voltage, carriers can be provided to maintain the turn-off current at the end of turn-off of the device, the turn-off softness is maintained, the turn-off time and turn-off loss are reduced, and when the IGBT device is at a higher working voltage, the depletion layer of the device is ensured to be cut off in the N-type diffusion layer, so that the turn-off current of the IGBT device cannot oscillate, and the problems of long current tailing, high loss and high overvoltage failure risk existing in the current fluctuation of the IGBT device are solved.
It will be apparent to those skilled in the art that the above-described division of each doped region is merely illustrative for convenience and brevity of description, and that in practical applications, the above-described allocation of functional regions may be performed by different doped regions, i.e., the internal structure of the device is divided into different doped regions, to perform all or part of the above-described functions.
In the embodiment, each doped region may be integrated in one functional region, or each doped region may exist physically alone, or two or more doped regions may be integrated in one functional region, where the integrated functional regions may be implemented by using the same doping ion, or may be implemented by using multiple doping ions together. In addition, the specific names of the doped regions are also only for distinguishing from each other, and are not used to limit the protection scope of the present application. The specific working process of the middle doped region in the method for manufacturing a device may refer to the corresponding process in the foregoing method embodiment, and will not be described herein.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. A softness-modulated IGBT device, characterized in that the softness-modulated IGBT device comprises:
the N-type field termination layer and the P-type collector region are formed on the back surface of the N-type field termination layer;
the softness modulation area is formed on the front surface of the N-type field termination layer; the soft modulation region comprises an N-type diffusion layer and a local carrier life control layer, and the doping concentration of the N-type diffusion layer is smaller than that of the N-type field termination layer;
the N-type drift layer is formed on the N-type diffusion layer and is of a convex structure;
a gate dielectric layer positioned above the horizontal portion of the N-type drift layer and in contact with the raised portion of the N-type drift layer; wherein the grid dielectric layer is of a concave structure;
the polysilicon layer is formed in the groove of the grid dielectric layer;
the P-type well region is formed on the protruding part of the N-type drift layer and is in contact with the gate dielectric layer;
an N-type source region formed on the P-type well region;
the insulating medium layer is formed on the polycrystalline silicon layer and the N-type source region;
the emission metal layer is formed on the insulating medium layer and is in a convex structure, and the protruding part of the emission metal layer penetrates into the P-type well region through the insulating medium layer and the through hole on the N-type source region;
and the collector metal layer is formed on the back surface of the P-type collector region.
2. The softness-modulated IGBT device of claim 1 wherein the localized carrier lifetime control layer is formed in the N type diffusion layer or the localized carrier lifetime control layer is formed between the N type diffusion layer and the N type field stop layer.
3. The softness-modulated IGBT device of claim 1 wherein the number of localized carrier lifetime control layers is a plurality, the plurality of localized carrier lifetime control layers being separated by the N-type diffusion layer.
4. The softness-modulated IGBT device of claim 3 wherein the distance between adjacent localized carrier lifetime control layers is equal.
5. The softness-modulated IGBT device of any one of claims 1 to 4 wherein the localized carrier lifetime control layer has a thickness of 50nm to 1um.
6. The softness-modulated IGBT device of any one of claims 1 to 4 wherein the distance between the localized carrier lifetime control layer and the boundary of the softness modulated zone is equal to or less than 5um.
7. The softness-modulated IGBT device of any one of claims 1 to 4 wherein the localized carrier lifetime control layer is formed by implanting hydrogen ions or helium ions into a designated area in the N-type diffusion layer.
8. The softness-modulated IGBT device of any one of claims 1 to 4 wherein the N-type field stop layer has a doping concentration at least 100 times that of the N-type diffusion layer;
the doping concentration of the N-type diffusion layer is set in a gradient mode.
9. The preparation method of the softness modulation type IGBT device is characterized by comprising the following steps of:
growing an N-type diffusion layer on the front surface of the N-type field termination layer; the doping concentration of the N-type diffusion layer is smaller than that of the N-type field termination layer;
growing an N-type drift layer on the N-type diffusion layer;
etching the N-type drift layer to form a groove structure on the N-type drift layer, and enabling the N-type drift layer to be in a convex structure;
forming a gate dielectric layer on the inner wall of the groove structure on the N-type drift layer, and filling a polysilicon layer in the gate dielectric layer; the grid dielectric layer is positioned above the horizontal part of the N-type drift layer and is in contact with the protruding part of the N-type drift layer;
forming a P-type well region which is in contact with the gate dielectric layer on the convex part of the N-type drift layer;
forming an N-type source region on the P-type well region, and forming an insulating medium layer on the polycrystalline silicon layer and the N-type source region;
etching the polysilicon layer and the N-type source region to form an etching groove penetrating into the P-type well region, and forming a transmitting metal layer in the etching groove; the emitting metal layer is in a convex structure, and the protruding part of the emitting metal layer is in contact with the P-type well region;
thinning the back surface of the N-type field termination layer, and implanting hydrogen ions or helium ions into a designated area in the N-type diffusion layer and then annealing to form a local carrier life control layer;
and forming a P-type collector region on the back surface of the N-type field termination layer, and forming a collector metal layer on the back surface of the P-type collector region.
10. A chip comprising the softness-modulated IGBT device of any one of claims 1 to 8; or the chip comprises a softness modulation type IGBT device prepared by the preparation method of claim 9.
CN202310233712.7A 2023-02-28 2023-02-28 Softness modulation type IGBT device, preparation method thereof and chip Pending CN116207146A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117650162A (en) * 2023-10-31 2024-03-05 海信家电集团股份有限公司 Semiconductor device and method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117650162A (en) * 2023-10-31 2024-03-05 海信家电集团股份有限公司 Semiconductor device and method for manufacturing semiconductor device

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