JPH01293694A - Manufacture of printed-circuit board - Google Patents
Manufacture of printed-circuit boardInfo
- Publication number
- JPH01293694A JPH01293694A JP12612288A JP12612288A JPH01293694A JP H01293694 A JPH01293694 A JP H01293694A JP 12612288 A JP12612288 A JP 12612288A JP 12612288 A JP12612288 A JP 12612288A JP H01293694 A JPH01293694 A JP H01293694A
- Authority
- JP
- Japan
- Prior art keywords
- film
- plating
- resist
- resist film
- plating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000004020 conductor Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000007747 plating Methods 0.000 claims description 94
- 239000000758 substrate Substances 0.000 claims description 11
- 238000010030 laminating Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 102
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 21
- 239000011889 copper foil Substances 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 229910000831 Steel Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、大電流信号回路の実装に適したプリント配線
基板の製造方法に係り、詳しくは、基板上の導体パター
ンの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a printed wiring board suitable for mounting a large current signal circuit, and more particularly to a method of forming a conductor pattern on the board.
〈従来の技術〉
従来、基板に所要の導体パターンを形成する方法として
はサブトラクティブ法がある。<Prior Art> Conventionally, there is a subtractive method as a method for forming a required conductor pattern on a substrate.
このサブトラクティブ法は、基板表面に設けられた銅箔
等の導体層の各部分のうち、不要部分を薬品で溶解除去
する方法で、導体層を化学的に腐食させるので、エツチ
ング法とも呼ばれる。This subtractive method is a method in which unnecessary parts of a conductor layer such as copper foil provided on the surface of a substrate are dissolved and removed using chemicals, and the conductor layer is chemically corroded, so it is also called an etching method.
サブトラクティブ法には、大きく分けて、テンティング
方式と、金属レジスト方式との２通りの方式がある。There are two main subtractive methods: a tenting method and a metal resist method.
第３図（Ａ）〜（Ｄ）はテンティング方式の各工程を示
している。このテンティング方式では、まず、第３図（
Ａ）に示すように、銅張りの積層基板ｌを用意する。こ
の基板１には、スルーホールもしくはバイアホールのよ
うな導通孔２が穿設されている。３は基板本体上の銅箔
である。次いで、第３図（Ｂ）に示すように、導通孔２
を通じての電気的導通を図るために、無電解銅メッキと
電気銅メッキとにより銅のメッキ膜４を形成する。その
後、メッキ膜４の表面と裏面とに全面にわたってエツチ
ングレジストとなる感光性レジストをラミネートシ、こ
の感光性レジスト膜５に対して露光と現像とを行い、第
３図（Ｃ）に示すように、導体パターンが必要とする個
所にのみ感光性レジスト膜５が残るようにする。そして
、このように残存した感光性レジスト膜５を利用してエ
ツチングを行い、その後、感光性レジスト膜５を取り除
く。これによって、第３図（Ｄ）に示すように、感光性
レジスト＠５が存在しなかった個所のメッキ膜４と銅箔
３とが除去されるとともに、感光性レジスト膜５の下側
にあった銅箔３とメッキ膜４とが残存し、この残存した
銅箔３とメッキ膜４とにより所要の導体パターンが形成
される。FIGS. 3(A) to 3(D) show each step of the tenting method. In this tenting method, first, as shown in Figure 3 (
As shown in A), a copper-clad multilayer substrate l is prepared. This substrate 1 is provided with a conductive hole 2 such as a through hole or a via hole. 3 is a copper foil on the board body. Next, as shown in FIG. 3(B), the conduction hole 2
In order to achieve electrical continuity through the electrodes, a copper plating film 4 is formed by electroless copper plating and electrolytic copper plating. Thereafter, a photosensitive resist that will become an etching resist is laminated over the entire surface and back surface of the plating film 4, and this photosensitive resist film 5 is exposed and developed to form the etching resist as shown in FIG. 3(C). , so that the photosensitive resist film 5 remains only at locations where the conductor pattern is required. Then, etching is performed using the photosensitive resist film 5 remaining in this way, and then the photosensitive resist film 5 is removed. As a result, as shown in FIG. 3(D), the plating film 4 and the copper foil 3 at the locations where the photosensitive resist @5 was not present are removed, and the portions below the photosensitive resist film 5 are removed. The copper foil 3 and plating film 4 remain, and a required conductor pattern is formed by the remaining copper foil 3 and plating film 4.
第４図（Ａ）〜（Ｅ）は金属レジスト方式の各工程を示
している。この金属レジスト方式では、まず、第４図（
Ａ）に示すように、銅張りの積層基板！を用意し、次い
で、第４図（Ｂ）に示すように、導通孔２を通じての電
気的導通を図るために、無電解鋼メッキと電気銅メッキ
とにより銅のメッキ膜４を形成する。これまでの工程は
、テンティング方式と同様である。なお、この方式では
、銅のメッキＨ４の上にさらにメッキ膜が積層されるの
で、この銅のメッキ膜４が第１のメッキ膜となる。FIGS. 4(A) to 4(E) show each process of the metal resist method. In this metal resist method, first of all, as shown in Fig. 4 (
As shown in A), a copper-clad laminated board! Next, as shown in FIG. 4(B), a copper plating film 4 is formed by electroless steel plating and electrolytic copper plating in order to establish electrical continuity through the conduction hole 2. The steps up to this point are similar to the tenting method. In addition, in this method, since a plating film is further laminated on the copper plating H4, this copper plating film 4 becomes the first plating film.
その後、第１メッキ膜４の表面と裏面とに全面にわたっ
てメッキレジストとなる感光性レジストをラミネートし
、この感光性レジスト膜６に対して露光と現像とを行い
、第４図ＣＧ”）に示すように、導体パターンが不要で
ある個所にのみ感光性レジスト膜６が残るようにする。Thereafter, a photosensitive resist serving as a plating resist is laminated over the entire surface and back surface of the first plating film 4, and this photosensitive resist film 6 is exposed and developed, as shown in FIG. 4 CG''). In this way, the photosensitive resist film 6 is left only in areas where a conductive pattern is not required.
そして、導体パターンが必要個所である感光性レジスト
膜６の欠如部分には、第４図（Ｄ）に示すように、電気
銅メッキによる第２のメッキ膜７と、同じく電気メッキ
によるエツチングレジスト用の金属メッキ膜８とを形成
する。その後、感光性レジスト膜６を取り除き、金属メ
ッキ膜８をエツチングレジストとしてエツチングを行い
、感光性レジスト膜６が存在した個所の第１メッキ膜４
と銅箔３とを除去する。Then, as shown in FIG. 4(D), in the missing portion of the photosensitive resist film 6 where a conductor pattern is required, a second plating film 7 is formed by electrolytic copper plating and an etching resist film 7 is also formed by electrolytic plating. A metal plating film 8 is formed. Thereafter, the photosensitive resist film 6 is removed and etching is performed using the metal plating film 8 as an etching resist, and the first plating film 4 is removed at the location where the photosensitive resist film 6 was present.
and copper foil 3 are removed.
金属メッキ膜８が存在する個所では、第４図（Ｅ）に示
すように、銅箔３と第１メッキ膜４と第２メッキ膜７と
金属メッキ膜８とが残存し、これらの残存した導体層と
により所要の導体パターンが形成される。In the area where the metal plating film 8 exists, the copper foil 3, the first plating film 4, the second plating film 7, and the metal plating film 8 remain, as shown in FIG. 4(E). A required conductor pattern is formed by the conductor layer.
〈発明が解決しようとする課題〉
一般に、プリント配線基板を大電流信号回路の実装に用
いるには、その導体パターンの許容電流値を増大させる
必要があるが、上記従来のいずれの製造方法でも、導体
パターンを厚くすることが困難で、許容電流値の増大を
図るのが難しい、という問題がある。<Problems to be Solved by the Invention> Generally, in order to use a printed wiring board for mounting a large current signal circuit, it is necessary to increase the allowable current value of the conductor pattern. There is a problem in that it is difficult to increase the thickness of the conductor pattern and it is difficult to increase the allowable current value.
すなわち、テンティング方式の場合、導体パターンの厚
さを厚くするには、メッキ膜４の膜厚を厚くする必要が
あるが、メッキ膜４の膜厚を厚くすると、エツチングに
時間がかかるほか、エツチングの際、感光性レジスト膜
５の下側にあるメッキ膜４部分がエツチングの薬剤によ
り深く侵食されて導体７（ターンの形状が縮小し、所望
の導体パターンが得られなくなる。In other words, in the case of the tenting method, in order to increase the thickness of the conductor pattern, it is necessary to increase the thickness of the plating film 4, but increasing the thickness of the plating film 4 not only takes time for etching, but also increases the thickness of the plating film 4. During etching, the portion of the plating film 4 below the photosensitive resist film 5 is deeply eroded by the etching agent, and the shape of the conductor 7 (turn) is reduced, making it impossible to obtain a desired conductor pattern.
金属レジスト方式の場合は、導体パターンの厚みの大部
分は、第１メッキ膜４と第２メッキ膜７とで占められて
いる。したがって、導体パターンの膜厚を厚くする場合
、エツチングされる第１メッキ模４の膜厚を特に厚くし
なくても、第２メッキ膜７の膜厚を厚くすればよい。そ
のため、テンティング方式におけるような問題は生じな
い。In the case of the metal resist method, most of the thickness of the conductor pattern is occupied by the first plating film 4 and the second plating film 7. Therefore, when increasing the thickness of the conductor pattern, it is sufficient to increase the thickness of the second plating film 7 without particularly increasing the thickness of the first plating pattern 4 to be etched. Therefore, problems like those in the tenting method do not occur.
しかしながら、この金属レジスト方式では、第２メッキ
膜７の膜厚は、第１メッキ膜４上の感光性レジスト膜６
の膜厚で決まるのであるが、従来、この感光性レジスト
膜６は、感光性の薄膜、いわゆるドライフィルムを接着
して形成しているから、５０〜７５μｍ程度の膜厚にし
か得られない。したがって、第２メッキ膜７は、感光性
レジスト膜６に対応しても同程度の薄膜となるので、導
体パターン全体の厚さを充分に厚くすることができない
。However, in this metal resist method, the film thickness of the second plating film 7 is smaller than that of the photosensitive resist film on the first plating film 4.
Conventionally, the photosensitive resist film 6 has been formed by adhering a photosensitive thin film, a so-called dry film, so that a film thickness of only about 50 to 75 μm can be obtained. Therefore, since the second plating film 7 is as thin as the photosensitive resist film 6, the thickness of the entire conductor pattern cannot be made sufficiently thick.
これに対しては、もちろん、導体パターンの幅を広げて
、許容電流値の増大に対応することが考えられるが、こ
の対策は、多くの導体パターンを設ける基板では、スペ
ース的に余裕がなく、採用することができない。To deal with this, of course, it is possible to widen the width of the conductor pattern to accommodate the increase in the allowable current value, but this measure does not have enough space on a board with many conductor patterns. cannot be adopted.
このように、従来の製法では、導体パターンの許容電流
値が大きいプリント配線基板を製作することが極めて困
難で、そのため、大電流信号回路は、ジャンパー線処理
、あるいはブスバ一方式により組み立てられており、組
立工数が多く、生産効率が低かった。As described above, with conventional manufacturing methods, it is extremely difficult to produce a printed wiring board with a large permissible current value for the conductor pattern. Therefore, large current signal circuits are assembled using jumper wire processing or busbar one-way methods. , the number of assembly steps was large, and production efficiency was low.
本発明は、上述の問題点に鑑みてなされたものであって
、前記した金属レジスト方式の製造方法に改良を加える
ことで、導体パターンの厚さの増大を図り、許容電流値
が大きなプリント配線基板が得られるようにすることを
課題とする。The present invention has been made in view of the above-mentioned problems, and by improving the metal resist manufacturing method described above, the thickness of the conductor pattern is increased and the printed wiring has a large allowable current value. The challenge is to make it possible to obtain a substrate.
〈課題を解決するための手段〉
本発明は、上記の目的を達成するために、金属レジスト
方式の製造方法、すなわち、基板上に形成された第１の
導体メッキ膜の各部のうち、導体パターンの不要個所に
メッキレジスト膜を形成する工程と、メッキレジスト膜
の欠如部分に第２の導体メッキ膜とエツチングレジスト
となる金属メッキ膜とを積層して形成する工程と、前記
メッキレジスト膜を取り除き、前記金属メッキ膜をエツ
チングレジストとしてエツチングを行う工程とを含むプ
リント配線基板の製造方法において、前記メッキレジス
ト膜を湿式により厚膜に形成し、このメッキレジスト膜
の欠如部分に形成する第２の導体メッキ膜の膜厚を前記
メッキレジスト膜と同程度の厚膜にするようにした。<Means for Solving the Problems> In order to achieve the above object, the present invention provides a metal resist manufacturing method, that is, a method for manufacturing a conductor pattern in each part of a first conductor plating film formed on a substrate. a step of forming a plating resist film on unnecessary parts of the plating resist film, a step of laminating and forming a second conductor plating film and a metal plating film serving as an etching resist in the missing part of the plating resist film, and removing the plating resist film. , a method of manufacturing a printed wiring board including the step of performing etching using the metal plating film as an etching resist, the plating resist film being formed into a thick film by a wet method, and a second step of forming the plating resist film in the missing portion of the plating resist film. The thickness of the conductive plating film was made to be approximately the same as that of the plating resist film.
く作用〉
上記の製法によれば、第１の導体メッキ膜上のメッキレ
ジスト膜が１〜２ｍｍ程度の厚膜に形成され、これに対
応して、第２の導体メッキ膜の膜厚も同程度の厚さとな
る。したがって、第１の導体メッキ膜と第２の導体メッ
キ膜とで構成される導体パターンの厚さは、従来のもの
に比べて、大幅に増大するので、その許容電流値も著し
く増大する。According to the above manufacturing method, the plating resist film on the first conductor plating film is formed to a thickness of about 1 to 2 mm, and correspondingly, the film thickness of the second conductor plating film is also the same. It will be about the same thickness. Therefore, the thickness of the conductor pattern composed of the first conductor plating film and the second conductor plating film is significantly increased compared to the conventional one, and the allowable current value thereof is also significantly increased.
〈実施例〉
以下、本発明を図面に示す実施例に基づいて詳細に説明
する。第１図は、本発明の製造方法により得られたプリ
ント配線基板の一部の断面図、第２図（Ａ）〜（Ｄ）は
、本発明の製造方法の各工程における基板の断面図であ
る。<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings. FIG. 1 is a cross-sectional view of a part of a printed wiring board obtained by the manufacturing method of the present invention, and FIGS. 2 (A) to (D) are cross-sectional views of the board at each step of the manufacturing method of the present invention. be.
本発明の製法により得られたプリント配線基板は、従来
の益属レジスト方式の製法により得られたものと同様に
、積層基板ｌの所要個所に、銅箔３と、第１のメッキ膜
４と、第２のメッキ膜７と、エツチングレジストとなる
金属メッキ膜８とが順次積層形成されたもので、これら
銅箔３、第１メッキ膜４、第２メッキ膜７および金属メ
ッキ膜８とで導体パターンが構成されている。The printed wiring board obtained by the manufacturing method of the present invention has a copper foil 3 and a first plating film 4 in the required places of the multilayer board l, similar to that obtained by the conventional metal resist method. , a second plating film 7 and a metal plating film 8 serving as an etching resist are sequentially laminated. A conductor pattern is formed.
従来の金属レジスト方式のものと異なる点は、第２メッ
キ［１７の膜厚ｄが１〜２ｍｓ程度の厚膜となっている
ことである。The difference from the conventional metal resist method is that the second plating [17] has a film thickness d of about 1 to 2 ms.
次の本発明の製造方法の各工程を第２図の（Ａ）〜（Ｄ
）に基づいて説明する。The following steps of the manufacturing method of the present invention are shown in FIG. 2 (A) to (D).
).
■ まず、第２図（Ａ）に示すように、銅張りの積層基
板Ｉを用意する。この基板Ｉには、スルーホールもしく
はバイアホールのような導通孔２が穿設されている。(1) First, as shown in FIG. 2(A), a copper-clad laminate board I is prepared. This substrate I is provided with a conductive hole 2 such as a through hole or a via hole.
■ 次いで、第２図（Ｂ）に示すように、導通孔２を通
じての電気的導通を図るために、無電解銅メッキと電気
鋼メッキとにより第１のメッキ膜４を形成する。(2) Next, as shown in FIG. 2(B), a first plating film 4 is formed by electroless copper plating and electric steel plating in order to establish electrical continuity through the conduction hole 2.
これまでの工程は、従来の金属レジスト方式と同様であ
る。The steps up to this point are similar to those of the conventional metal resist method.
■ その後、湿式により所要部にメッキレジストとなる
感光性レジスト膜６を形成する。すなわち、第１メッキ
膜４の表面と裏面とに全面にわたって感光剤を塗布して
から、導体パターンが不要である個所だけ露光し、次い
で現像、定着を行って、第２図（Ｃ）に示すように、導
体パターンが不要である個所にのみ感光性レジスト膜６
が残るようにする。(2) Thereafter, a photosensitive resist film 6 that will serve as a plating resist is formed at required portions by a wet process. That is, after applying a photosensitive agent to the entire surface and back surface of the first plating film 4, exposing only the areas where no conductive pattern is required, and then developing and fixing, as shown in FIG. 2(C). As shown in FIG.
so that it remains.
ここで、感光性レジスト膜６は湿式により形成されるか
ら、その膜厚ｅは１〜２ｍｍ程度にすることができる。Here, since the photosensitive resist film 6 is formed by a wet method, its film thickness e can be set to about 1 to 2 mm.
■ そして、導体パターンの必要個所である感光性レジ
スト膜６の欠如部分には、第２図（Ｄ）に示すように、
電気銅メッキによる第２のメッキＭ７と、同じく電気メ
ッキによるエツチングレジスト用の金属メッキ膜８とを
形成する。(2) In the missing part of the photosensitive resist film 6, which is the necessary part of the conductor pattern, as shown in FIG. 2(D),
A second plating M7 by electrolytic copper plating and a metal plating film 8 for etching resist also by electroplating are formed.
この場合、第２メッキ膜７の膜厚ｄは、はぼ感光性レジ
スト膜６の膜厚ｅに対応するので、該膜厚ｄは１〜２烏
鵬程度となる。In this case, the film thickness d of the second plating film 7 corresponds to the film thickness e of the photosensitive resist film 6, so the film thickness d is approximately 1 to 2 mm.
■ その後、感光性レジスト膜６を取り除く。(2) After that, the photosensitive resist film 6 is removed.
■ そして、金属メッキ膜８をエツチングレジストとし
、エツチングを行い、感光性レジスト膜６が存在した個
所の第１メッキ模４と銅箔３とを除去する。金属メッキ
膜８が存在する個所では、第２メッキ膜７と第１メッキ
膜４と銅箔３とが残存し、この残存した銅箔３と第１メ
ッキ膜４と第２メッキ膜７と金属メッキ膜８とにより導
体パターンが形成される。(2) Then, etching is performed using the metal plating film 8 as an etching resist to remove the first plating pattern 4 and the copper foil 3 where the photosensitive resist film 6 was present. In the area where the metal plating film 8 exists, the second plating film 7, the first plating film 4, and the copper foil 3 remain, and the remaining copper foil 3, the first plating film 4, the second plating film 7, and the metal A conductive pattern is formed by the plating film 8.
これによって、第１図に示したようなプリント配線基板
が得られる。As a result, a printed wiring board as shown in FIG. 1 is obtained.
なお、厚膜のレジスト膜６を構成する感光性レジストに
代えて、耐酸、耐アルカリのメッキレジストを用いても
よい。また、実施例では、エツチングレジストとなる金
属メッキ膜８を導体パターンの一部として残したが、エ
ッヂング処理後に除去してもよい。このほか、金属メッ
キ膜８を設けないで、第１メッキ膜４と第２メッキ膜７
との膜厚の差を利用して、エツチングを行うこともでき
る。Note that instead of the photosensitive resist constituting the thick resist film 6, an acid-resistant and alkali-resistant plating resist may be used. Further, in the embodiment, the metal plating film 8 serving as an etching resist is left as a part of the conductor pattern, but it may be removed after the etching process. In addition, the first plating film 4 and the second plating film 7 are not provided with the metal plating film 8.
Etching can also be performed using the difference in film thickness.
〈発明の効果〉
以上のように、本発明によれば、導体パターンの厚さが
従来のものに比べ、大幅に厚くなり、導体パターンの許
容電流値が著しく増大する。したがって、本発明の製造
方法により得られたプリント配線基板には、ジャンパー
線処理やブスバ一方式によらずに、大電流信号回路を実
装することができる。<Effects of the Invention> As described above, according to the present invention, the thickness of the conductor pattern becomes significantly thicker than that of the conventional conductor pattern, and the allowable current value of the conductor pattern increases significantly. Therefore, a large current signal circuit can be mounted on the printed wiring board obtained by the manufacturing method of the present invention without using jumper wire processing or a single bus bar system.
第１図は、本発明の製造方法により得られたプリント配
線基板の一部の断面図、第２図（Ａ）〜（Ｄ）は、本発
明の製造方法の各工程における基板の断面図である。
第３図および第４図はいずれも従来例に係り、第３図（
Ａ）〜（Ｄ）は従来の製造方法の各工程における基板の
断面図、第４図（Ａ）〜（Ｅ）は他の従来の製造方法に
おける各工程の基板の断面図である。
Ｉ・・・積層基板、３・・・銅箔、４・・・第１メッキ
膜、６・・・感光性レジスト膜（メッキレジスト膜）、
７・・・第２メッキ膜、８・・・金属メッキ膜。FIG. 1 is a cross-sectional view of a part of a printed wiring board obtained by the manufacturing method of the present invention, and FIGS. 2 (A) to (D) are cross-sectional views of the board at each step of the manufacturing method of the present invention. be. Both Fig. 3 and Fig. 4 relate to the conventional example, and Fig. 3 (
A) to (D) are cross-sectional views of the substrate at each step in a conventional manufacturing method, and FIGS. 4(A) to (E) are cross-sectional views of the substrate at each step in another conventional manufacturing method. I... Laminated substrate, 3... Copper foil, 4... First plating film, 6... Photosensitive resist film (plating resist film),
7... Second plating film, 8... Metal plating film.
Claims (1)
うち、導体パターンの不要個所にメッキレジスト膜を形
成する工程と、メッキレジスト膜の欠如部分に第２の導
体メッキ膜とエッチングレジストとなる金属メッキ膜と
を積層して形成する工程と、前記メッキレジスト膜を取
り除いて前記金属メッキ膜をエッチングレジストとして
エッチングを行う工程とを含むプリント配線基板の製造
方法において、 前記メッキレジスト膜を湿式により厚膜に形成し、この
メッキレジスト膜の欠如部分に形成する第２の導体メッ
キ膜の膜厚を前記メッキレジスト膜と同程度の厚膜にす
ることを特徴とするプリント配線基板の製造方法。(1) Forming a plating resist film on parts of the first conductor plating film formed on the substrate where the conductor pattern is not needed, and etching a second conductor plating film on the missing parts of the plating resist film. A method for manufacturing a printed wiring board, which includes a step of laminating and forming a metal plating film to serve as a resist, and a step of removing the plating resist film and performing etching using the metal plating film as an etching resist. A printed wiring board characterized in that a second conductive plating film formed on the missing part of the plating resist film has a thickness comparable to that of the plating resist film. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12612288A JPH01293694A (en) | 1988-05-23 | 1988-05-23 | Manufacture of printed-circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12612288A JPH01293694A (en) | 1988-05-23 | 1988-05-23 | Manufacture of printed-circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01293694A true JPH01293694A (en) | 1989-11-27 |
Family
ID=14927195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12612288A Pending JPH01293694A (en) | 1988-05-23 | 1988-05-23 | Manufacture of printed-circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01293694A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710594A (en) * | 1980-06-20 | 1982-01-20 | Matsushita Electric Ind Co Ltd | Remote control originating device |
| JPS63500837A (en) * | 1985-08-08 | 1988-03-24 | マツクダ−ミツド インコ−ポレ−テツド | Printed circuit board manufacturing method |
-
1988
- 1988-05-23 JP JP12612288A patent/JPH01293694A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710594A (en) * | 1980-06-20 | 1982-01-20 | Matsushita Electric Ind Co Ltd | Remote control originating device |
| JPS63500837A (en) * | 1985-08-08 | 1988-03-24 | マツクダ−ミツド インコ−ポレ−テツド | Printed circuit board manufacturing method |
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