JPH05347468A - Manufacture of printed circuit board - Google Patents

Manufacture of printed circuit board

Info

Publication number
JPH05347468A
JPH05347468A JP15397192A JP15397192A JPH05347468A JP H05347468 A JPH05347468 A JP H05347468A JP 15397192 A JP15397192 A JP 15397192A JP 15397192 A JP15397192 A JP 15397192A JP H05347468 A JPH05347468 A JP H05347468A
Authority
JP
Japan
Prior art keywords
photoresist
thin film
circuit
conductive thin
electrodeposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15397192A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Kuboi
良行 窪井
Toru Nobetani
徹 延谷
Seiji Kobayashi
誠司 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP15397192A priority Critical patent/JPH05347468A/en
Publication of JPH05347468A publication Critical patent/JPH05347468A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To form a circuit of a fine pattern on a surface of a base which is stereoscopically formed. CONSTITUTION:A conductive thin film 2 is provided on a surface of a base 1 which is stereoscopically formed. The surface of the film 2 is covered with electrodeposited photoresist 3. The photoresist 3 is exposed and developed to remove the photoresist 3 by a circuit pattern. The surface of the film 2 of a part exposed by removing the photoresist 3 is electroplated to form a conductor layer 4. After the photoresist 3 is peeled, the film exposed by peeling the photoresist 3 is removed by etching. A part exposed without covering with the photoresist 3 of the film 2 is electroplated to provide a conductor layer 4 having a predetermined thickness thereby to form a circuit, and hence etching may be lightly processed to remove the film 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、表面が立体的に形成さ
れたプリント配線板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board having a three-dimensional surface.

【0002】[0002]

【従来の技術】MCB(Molded Circuit
Board)やMID(Molded Interc
onnection Device)として、樹脂のモ
ールド成形品で基体(基板)を作成したプリント配線板
が最近注目されている。このようなMCBやMIDの基
体は表面が立体的に形成されているために、表面が平滑
面であることを前提とする従来の回路形成法をそのまま
採用することはできない。
2. Description of the Related Art MCB (Molded Circuit)
Board) and MID (Molded Interc)
As a connection device, a printed wiring board in which a base (substrate) is made of a resin molded product has recently been receiving attention. Since the surface of such a MCB or MID substrate is three-dimensionally formed, the conventional circuit forming method, which is premised on the surface being a smooth surface, cannot be adopted as it is.

【0003】そこで、種々の工夫がなされており、例え
ば特開平4−76985号公報においてレジストとして
電着フォトレジストを用いたプリント配線板の製造法が
提供されている。すなわち、基体の表面の全面に無電解
メッキした後さらに電気メッキして回路として要求され
る厚みの金属層を設け、次にこの金属層の上に電着フォ
トレジストを被着する。従来よりフォトレジストは塗布
したり印刷したりして被着されており、表面が平滑な基
板の表面には均一な厚みでフォトレジストを被着させる
ことができるが、表面が立体的な基体の場合には均一な
厚みでフォトレジストを被着させることができない。一
方、電着フォトレジストは電着塗装の技術をフォトレジ
ストの塗布に応用したものであり、電着フォトレジスト
液に基体を浸漬して電着フォトレジスト液と基体の金属
層との間に直流電流を通電すると、電気メッキと同様な
原理で電極反応によって電着フォトレジスト液の樹脂成
分が金属層の表面に析出し、金属層の表面に電着フォト
レジストを電着塗装することができる。金属層の表面に
析出した電着フォトレジストは電気的に絶縁性であるた
めに、金属層の表面で部分的に電着フォトレジストの析
出量に差が生じると、析出量が少なく絶縁性の低い部分
に析出が集中することになり、この結果、基体の表面が
立体的で凹んだ部分があっても均一な厚みで電着フォト
レジストを塗布することができるのである。そして所定
の回路パターンに応じて電着フォトレジストを露光する
ことによって露光した部分を分解させ、次に現像するこ
とによって電着フォトレジストの露光され分解された部
分を溶解除去し、回路パターンとは逆パターンで金属層
を露出させる。そしてエッチング液で処理することによ
って金属層の露出される部分を溶解除去して金属層の残
存部分で回路を形成した後、電着フォトレジストを除去
することによって、プリント配線板を作成することがで
きるものである。
Therefore, various measures have been taken. For example, Japanese Patent Laid-Open No. 4-76985 provides a method for manufacturing a printed wiring board using an electrodeposited photoresist as a resist. That is, electroless plating is performed on the entire surface of the substrate, and then electroplating is performed to provide a metal layer having a thickness required for a circuit, and then an electrodeposition photoresist is deposited on this metal layer. Conventionally, photoresist has been applied by coating or printing, and it is possible to apply photoresist with a uniform thickness on the surface of a substrate with a smooth surface. In this case, the photoresist cannot be applied with a uniform thickness. On the other hand, electrodeposition photoresist is an application of the technique of electrodeposition coating to the application of photoresist, in which the substrate is immersed in the electrodeposition photoresist solution to form a direct current between the electrodeposition photoresist solution and the metal layer of the substrate. When an electric current is applied, the resin component of the electrodeposition photoresist solution is deposited on the surface of the metal layer by an electrode reaction on the same principle as electroplating, and the electrodeposition photoresist can be electrodeposited on the surface of the metal layer. Since the electrodeposited photoresist deposited on the surface of the metal layer is electrically insulating, if there is a difference in the deposition amount of the electrodeposited photoresist on the surface of the metal layer, the deposition amount will be small and Precipitation concentrates on the lower portion, and as a result, the electrodeposited photoresist can be applied with a uniform thickness even if the surface of the substrate is three-dimensional and has concave portions. Then, the exposed portion is decomposed by exposing the electrodeposited photoresist according to a predetermined circuit pattern, and then the exposed and decomposed portion of the electrodeposited photoresist is dissolved and removed by developing. The metal layer is exposed in a reverse pattern. Then, the exposed portion of the metal layer is dissolved and removed by treatment with an etching solution to form a circuit in the remaining portion of the metal layer, and then the electrodeposition photoresist is removed to form a printed wiring board. It is possible.

【0004】[0004]

【発明が解決しようとする課題】上記特開平4−769
85号公報の工法では、基体の表面に無電解メッキ及び
電解メッキで形成される金属層は回路として必要な厚
み、例えば10〜50μmの厚みで形成する必要があ
る。そしてこの金属層の不要部分をエッチングすること
によって回路形成をおこなうことになるが、10〜50
μm程度に厚く形成されている金属層をエッチングする
にあたっては処理時間を長くする等の必要があり、この
結果、回路として残すべき金属層の側面がエチング液で
侵食されていわゆるサイドエッチングされ易くなる。従
って回路のパターン精度が悪くなってファインパターン
で回路形成することが難しくなるという問題があった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the method disclosed in Japanese Patent Publication No. 85, the metal layer formed on the surface of the substrate by electroless plating and electrolytic plating needs to be formed to have a thickness necessary for a circuit, for example, 10 to 50 μm. Then, a circuit is formed by etching an unnecessary portion of this metal layer.
When etching a metal layer having a thickness of about μm, it is necessary to lengthen the processing time, etc. As a result, the side surface of the metal layer that should be left as a circuit is eroded by the etching liquid and is easily side-etched. .. Therefore, there has been a problem that the pattern accuracy of the circuit deteriorates and it becomes difficult to form a circuit with a fine pattern.

【0005】本発明は上記の点に鑑みてなされたもので
あり、ファインパターンで回路形成することができるプ
リント配線板の製造方法を提供することを目的とするも
のである。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a printed wiring board capable of forming a circuit in a fine pattern.

【0006】[0006]

【課題を解決するための手段】本発明に係るプリント配
線板の製造方法は、立体的に形成された基体1の表面に
導電性薄膜2を設け、この導電性薄膜2の表面に電着フ
ォトレジスト3を被着すると共に電着フォトレジスト3
を露光・現像処理して電着フォトレジスト3を回路パタ
ーンで除去し、電着フォトレジスト3の除去で露出され
る部分において導電性薄膜2の表面に電気メッキして導
体層4を形成し、電着フォトレジスト3を剥離した後、
電着フォトレジスト3の剥離で露出される導電性薄膜2
をエッチング除去することを特徴とするものである。
According to the method of manufacturing a printed wiring board of the present invention, a conductive thin film 2 is provided on the surface of a three-dimensionally formed substrate 1, and the surface of this conductive thin film 2 is subjected to electrodeposition photo. Resist 3 is deposited and electrodeposited photoresist 3
Is exposed and developed to remove the electrodeposited photoresist 3 with a circuit pattern, and the surface of the conductive thin film 2 is electroplated at the portion exposed by the removal of the electrodeposited photoresist 3 to form a conductor layer 4. After peeling off the electrodeposited photoresist 3,
Conductive thin film 2 exposed by peeling of electrodeposited photoresist 3
Is removed by etching.

【0007】[0007]

【作用】基体1の表面に設けた導電性薄膜2の電着フォ
トレジスト3で覆われず露出される部分に電気メッキし
て所定厚みの導体層4を設けることによって回路形成す
ることができるために、導電性薄膜2の厚みは電着フォ
トレジスト3を設けたり導体層4を電気メッキする際に
通電できる程度の薄い厚みで十分であり、エッチングは
この薄い導電性薄膜2を除去する軽い処理で済む。
A circuit can be formed by electroplating the exposed portion of the electroconductive thin film 2 provided on the surface of the substrate 1 without being covered with the electrodeposition photoresist 3 and providing the conductor layer 4 of a predetermined thickness. In addition, the thickness of the conductive thin film 2 is sufficiently thin that it can be energized when the electrodeposition photoresist 3 is provided or the conductor layer 4 is electroplated, and the etching is a light treatment for removing the thin conductive thin film 2. It's done.

【0008】[0008]

【実施例】以下本発明を実施例によって詳述する。基体
1は射出成形など樹脂のモールド成形によって作成され
るものであり、図1(a)に示すようにその表面は凹凸
を有する立体形状に形成してある。図1(a)において
10は基体1の表面の凹部、11は基体1を貫通するス
ルーホールを示す。そして、先ず基体1の表面に粗面化
等の前処理をした後に、無電解銅メッキ等の無電解メッ
キをおこなって図1(b)のように基体1の凹部10や
スルーホール11を含む全表面に銅被膜等の導電性薄膜
2を被着させる。導電性薄膜2は後述の電着フォトレジ
スト3を設けたり導体層4を電気メッキしたりする際に
通電するために設けるものであるので、通電に支障がな
い範囲で薄く形成しておけばよく、例えば0.5〜10
μm(好ましくは5μm以下)程度の薄い厚みで十分で
ある。
EXAMPLES The present invention will be described in detail below with reference to examples. The base 1 is formed by resin molding such as injection molding, and its surface is formed in a three-dimensional shape having irregularities as shown in FIG. In FIG. 1A, reference numeral 10 denotes a concave portion on the surface of the substrate 1, and 11 denotes a through hole penetrating the substrate 1. Then, first, the surface of the substrate 1 is subjected to pretreatment such as roughening, and then electroless plating such as electroless copper plating is performed to include the recesses 10 and the through holes 11 of the substrate 1 as shown in FIG. 1B. A conductive thin film 2 such as a copper coating is deposited on the entire surface. Since the conductive thin film 2 is provided for energizing when the electrodeposition photoresist 3 and the conductor layer 4 which will be described later are provided, it should be thinly formed within a range that does not hinder energization. , For example, 0.5 to 10
A thin thickness of about μm (preferably 5 μm or less) is sufficient.

【0009】このように基体1の表面に導電性薄膜2を
設けた後に、導電性薄膜2の表面の全面に図1(c)の
ように電着フォトレジスト3を被着させる。電着型のフ
ォトレジストには特開昭63−23389号公報等に報
告されているようにカチオン型とアニオン型があり、一
般に提供されている任意のものを使用することができ
る。そして基体1を電着フォトレジスト液に浸漬すると
共に電着フォトレジスト液に電極を差込み、基体1の導
電性薄膜2をカチオン型電着フォトレジスト液の場合は
陰極に、アニオン型電着フォトレジスト液の場合には陽
極にそれぞれ接続すると共に、電極をカチオン型電着フ
ォトレジスト液の場合は陽極に、アニオン型電着フォト
レジスト液の場合は陰極にそれぞれ接続し、両者間に直
流電流を流すことによって、導電性薄膜2の表面にフォ
トレジストを析出させて電着塗装をおこなうことがで
き、電着フォトレジスト3を被着することができるもの
である。電着フォトレジスト3は既述のように凹部10
内にもスルーホール11内にも均一な厚みで被着させる
ことができる。
After the conductive thin film 2 is provided on the surface of the substrate 1 as described above, the electrodeposited photoresist 3 is deposited on the entire surface of the conductive thin film 2 as shown in FIG. 1 (c). Electrodeposited photoresists include cation type and anion type as reported in JP-A-63-23389, and any generally provided one can be used. Then, the substrate 1 is dipped in the electrodeposition photoresist solution and an electrode is inserted into the electrodeposition photoresist solution, and the conductive thin film 2 of the substrate 1 is used as a cathode in the case of a cation type electrodeposition photoresist solution and an anion type electrodeposition photoresist. In the case of liquid, it is connected to the anode respectively, and the electrode is connected to the anode in the case of cation type electrodeposition photoresist solution and to the cathode in the case of anion type electrodeposition photoresist solution, and a direct current is passed between them. As a result, a photoresist can be deposited on the surface of the conductive thin film 2 for electrodeposition coating, and the electrodeposition photoresist 3 can be deposited. As described above, the electrodeposition photoresist 3 has the recess 10
It can be applied to the inside as well as the through hole 11 with a uniform thickness.

【0010】このように電着フォトレジスト3を被着し
た後に、図1(d)のように基体1の表面にフォトマス
ク12を重ねて露光をおこなう。フォトマスク12とし
ては回路を形成するべき箇所にマスク部12aを設けた
ものを用い、平行光線を照射してマスク部12a以外の
箇所を通過する光で電着フォトレジスト3を露光し、電
着フォトレジスト3の露光した部分を硬化させる。次に
現像液で処理して電着フォトレジスト3のうち露光され
ていない部分を溶解除去する。このように現像処理する
ことによって、図1(e)に示すように電着フォトレジ
スト3を回路パターンで除去し、回路パターンと逆のパ
ターンで電着フォトレジスト3を残す。
After depositing the electrodeposition photoresist 3 in this manner, a photomask 12 is overlaid on the surface of the substrate 1 as shown in FIG. As the photomask 12, a mask portion 12a is provided at a place where a circuit is to be formed, and the electrodeposited photoresist 3 is exposed to light passing through a portion other than the mask portion 12a by irradiating a parallel light beam to the electrodeposition photoresist 3 The exposed portion of photoresist 3 is cured. Next, the film is treated with a developing solution to dissolve and remove the unexposed portion of the electrodeposited photoresist 3. By performing the development process in this way, the electrodeposited photoresist 3 is removed with a circuit pattern as shown in FIG. 1E, and the electrodeposited photoresist 3 is left in a pattern opposite to the circuit pattern.

【0011】次に、導電性薄膜2に電極を接続して基体
1を銅メッキ液などメッキ液に浸漬すると共に導電性薄
膜2に直流電流を通電することによって、電気銅メッキ
など電気メッキをおこなう。このように電気メッキをお
こなうと、導電性薄膜2のうち電着フォトレジスト3で
覆われていず露出する表面にはメッキ金属が析出して、
図1(f)のように金属銅による導体層4を形成するこ
とができる。導体層4は回路パターンで電着フォトレジ
スト3が除去された部分に設けられるものであり、回路
として必要な10〜50μm程度の厚みで形成される。
このとき必要に応じて導体層4の表面に金メッキ13を
施すことができる。この金メッキ13は導電性薄膜2に
通電する電気金メッキをおこなうことによって施すこと
ができるものであり、金メッキ用のメッキリード線を引
き回すような必要がなくなるものである。
Next, electrodes are connected to the conductive thin film 2, the substrate 1 is immersed in a plating liquid such as a copper plating liquid, and a direct current is applied to the conductive thin film 2 to perform electroplating such as electrolytic copper plating. .. When electroplating is performed in this manner, plating metal is deposited on the exposed surface of the conductive thin film 2 that is not covered with the electrodeposition photoresist 3,
The conductor layer 4 made of metallic copper can be formed as shown in FIG. The conductor layer 4 is provided in a portion where the electrodeposition photoresist 3 is removed in the circuit pattern, and is formed with a thickness of about 10 to 50 μm required for a circuit.
At this time, gold plating 13 can be applied to the surface of the conductor layer 4 if necessary. The gold plating 13 can be applied by performing electric gold plating for energizing the conductive thin film 2, and it is not necessary to draw a plating lead wire for gold plating.

【0012】上記のように導体層4を電気メッキして設
けた後、図1(g)のように電着フォトレジスト3を剥
離液に溶解させて剥離し、そしてエッチング液で処理す
ることによって、図1(h)に示すように、電着フォト
レジスト3の剥離で露出される不要な導電性薄膜2をエ
ッチング除去し、導体層4によって回路を作成すること
ができるものである。ここで、導電性薄膜2は通電でき
る範囲内で薄く形成されているために軽いエッチング処
理で除去することができるものであり、回路を形成する
導体層4の側面がエッチング液で侵食されることは殆ど
なく、サイドエッチングの影響を殆どなくして回路のパ
ターン精度を高く得ることができ、ファインパターンの
回路形成が可能になるものである。ちなみに、従来の技
術で説明した工法では回路幅80μm、回路間隔80μ
mが限界であるが、本発明の工法では回路幅40μm、
回路間隔40μmが可能である。尚、エッチング処理の
際に導体層4の表面もエッチングされることになるが、
導電性薄膜2と同じ程度の厚みが除去されるだけである
ので問題はない。このとき金メッキ13が導体層4の表
面に施してあれば、金メッキ13で導体層4を保護して
エッチング液から保護することができ、導体層4の厚み
が薄くなるおそれは全くない。
After electroplating the conductor layer 4 as described above, the electrodeposition photoresist 3 is dissolved in a stripping solution to strip it as shown in FIG. 1 (g) and treated with an etching solution. As shown in FIG. 1 (h), unnecessary conductive thin film 2 exposed by peeling of electrodeposited photoresist 3 is removed by etching, and a circuit can be formed by conductor layer 4. Here, since the conductive thin film 2 is formed thin within a range in which current can be applied, it can be removed by a light etching process, and the side surface of the conductor layer 4 forming a circuit is eroded by an etching solution. Since the influence of the side etching is almost eliminated, the pattern accuracy of the circuit can be obtained with high accuracy, and the fine pattern circuit can be formed. By the way, in the construction method described in the conventional technique, the circuit width is 80 μm and the circuit interval is 80 μm.
m is the limit, but in the construction method of the present invention, the circuit width is 40 μm,
A circuit spacing of 40 μm is possible. Although the surface of the conductor layer 4 is also etched during the etching process,
There is no problem because only the same thickness as the conductive thin film 2 is removed. If the gold plating 13 is applied to the surface of the conductor layer 4 at this time, the conductor layer 4 can be protected by the gold plating 13 and protected from the etching solution, and there is no possibility that the conductor layer 4 becomes thin.

【0013】[0013]

【発明の効果】上記のように本発明は、立体的に形成さ
れた基体の表面に導電性薄膜を設け、この導電性薄膜の
表面に電着フォトレジストを被着すると共に電着フォト
レジストを露光・現像処理して電着フォトレジストを回
路パターンで除去し、電着フォトレジストの除去で露出
される部分において導電性薄膜の表面に電気メッキして
導体層を形成し、電着フォトレジストを剥離した後、電
着フォトレジストの剥離で露出される導電性薄膜をエッ
チング除去するようにしたので、基体の表面に設けた導
電性薄膜の電着フォトレジストで覆われず露出される部
分に電気メッキして所定厚みの導体層を設けることによ
って回路形成することができるものであり、導電性薄膜
の厚みは電着フォトレジストを設けたり導体層を電気メ
ッキする際に通電できる程度の薄い厚みで十分であっ
て、エッチングはこの薄い導電性薄膜を除去する軽い処
理で済むことになり、エッチングの際に回路を形成する
導体層がサイドエッチングされることを低減して回路パ
ターンの精度を高めることができ、ファインパターンで
回路形成することができるものである。
As described above, according to the present invention, a conductive thin film is provided on the surface of a three-dimensionally formed substrate, and the surface of the conductive thin film is coated with an electrodeposition photoresist and the electrodeposition photoresist is formed. The electrodeposition photoresist is removed by a circuit pattern by exposure and development, and the surface of the conductive thin film is electroplated in the portion exposed by the removal of the electrodeposition photoresist to form a conductor layer. After peeling, the conductive thin film exposed by peeling of the electrodeposited photoresist was removed by etching.Therefore, the conductive thin film provided on the surface of the substrate was not covered with the electrodeposited photoresist and the exposed portion was electrically exposed. A circuit can be formed by plating and providing a conductor layer of a predetermined thickness.The thickness of the conductive thin film is the amount of electricity applied when an electrodeposition photoresist is provided or the conductor layer is electroplated. It is enough to have a thin thickness as much as possible, and etching can be done by a light treatment to remove this thin conductive thin film, so that side etching of the conductor layer forming the circuit during etching is reduced and the circuit is reduced. The precision of the pattern can be improved, and a circuit can be formed with a fine pattern.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すものであり、(a)乃
至(h)は各工程での断面図である。
FIG. 1 shows an embodiment of the present invention, in which (a) to (h) are cross-sectional views in each step.

【符号の説明】 1 基体 2 導電性薄膜 3 電着フォトレジスト 4 導体層[Explanation of symbols] 1 substrate 2 conductive thin film 3 electrodeposited photoresist 4 conductor layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 立体的に形成された基体の表面に導電性
薄膜を設け、この導電性薄膜の表面に電着フォトレジス
トを被着すると共に電着フォトレジストを露光・現像処
理して電着フォトレジストを回路パターンで除去し、電
着フォトレジストの除去で露出される部分において導電
性薄膜の表面に電気メッキして導体層を形成し、電着フ
ォトレジストを剥離した後、電着フォトレジストの剥離
で露出される導電性薄膜をエッチング除去することを特
徴とするプリント配線板の製造方法。
1. A conductive thin film is provided on the surface of a three-dimensionally formed substrate, and an electrodeposition photoresist is deposited on the surface of the conductive thin film, and the electrodeposition photoresist is exposed and developed to perform electrodeposition. After removing the photoresist with a circuit pattern and forming a conductor layer by electroplating on the surface of the conductive thin film in the portion exposed by the removal of the electrodeposition photoresist, the electrodeposition photoresist is peeled off, and then the electrodeposition photoresist is removed. A method for manufacturing a printed wiring board, which comprises removing the conductive thin film exposed by the peeling of the substrate by etching.
JP15397192A 1992-06-15 1992-06-15 Manufacture of printed circuit board Withdrawn JPH05347468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15397192A JPH05347468A (en) 1992-06-15 1992-06-15 Manufacture of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15397192A JPH05347468A (en) 1992-06-15 1992-06-15 Manufacture of printed circuit board

Publications (1)

Publication Number Publication Date
JPH05347468A true JPH05347468A (en) 1993-12-27

Family

ID=15574083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15397192A Withdrawn JPH05347468A (en) 1992-06-15 1992-06-15 Manufacture of printed circuit board

Country Status (1)

Country Link
JP (1) JPH05347468A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5879862A (en) * 1995-09-30 1999-03-09 Daewoo Electronics Co., Ltd. Method for planarizing a non planar layer
US7256495B2 (en) 2003-02-24 2007-08-14 Samsung Electro-Mechanics Co., Ltd. Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5879862A (en) * 1995-09-30 1999-03-09 Daewoo Electronics Co., Ltd. Method for planarizing a non planar layer
US7256495B2 (en) 2003-02-24 2007-08-14 Samsung Electro-Mechanics Co., Ltd. Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same

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