JPH01293626A - Wire bonding method in flexible wiring board - Google Patents

Wire bonding method in flexible wiring board

Info

Publication number
JPH01293626A
JPH01293626A JP63124011A JP12401188A JPH01293626A JP H01293626 A JPH01293626 A JP H01293626A JP 63124011 A JP63124011 A JP 63124011A JP 12401188 A JP12401188 A JP 12401188A JP H01293626 A JPH01293626 A JP H01293626A
Authority
JP
Japan
Prior art keywords
wire
electrode
ball
bonding
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63124011A
Other languages
Japanese (ja)
Inventor
Takeshi Kozuka
小塚　武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP63124011A priority Critical patent/JPH01293626A/en
Publication of JPH01293626A publication Critical patent/JPH01293626A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
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    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To achieve thinness and to restrict wire looping height by performing primary junction to the electrode at the wiring board side through Au ball at the tip of Au wire tip and then by performing secondary junction of Au wire to Au bump of a semiconductor chip in wedge shape. CONSTITUTION:An Au ball 7 is formed at the tip of an Au wire 4 by a torch electrode 6. The ball 7 is adhered to the electrode of a semiconductor chip 3. The ball 7 is cut off from the tip of the wire 4 and an Au bump 7 is formed on the chip 3. An Au ball 8 is newly formed at the tip of the wire 4 by the electrode 6. The wire 4 is moved to the terminal part of an electrode 2 of a terminal board 1 along with a capillary 5. The ball 8 is connected to the terminal of the electrode 2. The wire 4 is pulled out and the junction part of the wire 4 is adhered to the pump 7A by applying pressure. The wire 4 is cut off at the junction edge 4. It allows for thinness and allows looping height of the wire 4 to be restricted.

Description

【発明の詳細な説明】 （技術分野） 本発明は、ＩＣカード等のフレキシブル配線板に適する
ワイヤボンディング法に関するものであり、特に薄型化
を要求されるフレキシブル配線板に好適なワイヤボンデ
ィング法に関するものである。Detailed Description of the Invention (Technical Field) The present invention relates to a wire bonding method suitable for flexible wiring boards such as IC cards, and particularly to a wire bonding method suitable for flexible wiring boards that require thinning. It is.

（従来の技術） 半導体チップ上のＡ１．電極とリードフレームのインナ
リードの端子との間を接続するために、ワイヤボンディ
ングが用いられており、これにはＡＵ線を用いた熱圧着
法、ＡＩｌ線を用いた超音波ボンディング法、両者を組
み合わせたサーモン二ック法などがある。(Prior art) A1 on a semiconductor chip. Wire bonding is used to connect the electrodes and the terminals of the inner leads of the lead frame, and these methods include thermocompression bonding using AU wires, ultrasonic bonding using Al wires, and both methods. There is a combination of methods such as the salmon nick method.

また、前記ワイヤボンディングにおいて、フレキシブル
配線板１上の半導体チップ３を実装した場合、第３図に
示されるように、Ａｕワイヤ４の先端に形成したＡｕボ
ール７Ｂを半導体チップ３の電極上に接合した（第一次
接合）後、Ａｕワイヤ４の端部をフレキシブル配線板１
の電極２にウェッジ側ボンディングとして接合している
（第二次接合）。このため、半導体チップ３に取り付け
られたＡｕワイヤ４のルーピングが半導体チップ３の上
面よりも０．３〜０．４　ｔｍ高くなり、このルーピン
グの突出したＡｕワイヤの部分は、ＩＣカードのように
薄型化が要求される実装手段として問題を生じている。In addition, in the wire bonding, when the semiconductor chip 3 is mounted on the flexible wiring board 1, as shown in FIG. (first bonding), the end of the Au wire 4 is attached to the flexible wiring board 1.
It is bonded to the electrode 2 as wedge side bonding (secondary bonding). For this reason, the loop of the Au wire 4 attached to the semiconductor chip 3 is 0.3 to 0.4 tm higher than the top surface of the semiconductor chip 3, and the protruding portion of the Au wire in this loop is similar to an IC card. This is causing problems as a mounting means that requires thinning.

また、フレキシブル配線板１において、Ａｕワイヤ４の
一端が接合される電極２部分を拡大すると、第４図に示
されるように、電極２とフレキシブル配線板１との間に
接着剤９が介在しており、このため、加熱しながら超音
波を加えるサーモソニックボンディングでは、前記接着
剤９が熱により軟化し、超音波を吸収し、ワイヤボンデ
ィング性が非常に良くない欠点を有している。第４図に
おいて、１０はＣｕ箔、１１はＮｉメツキ層、１２はＡ
ｕメツキ層であり、このＡｕメツキ層１２の厚みは０．
５μｍ以上を必要とし、これはコスト高の要因上なって
いる。Furthermore, when the part of the electrode 2 on the flexible wiring board 1 to which one end of the Au wire 4 is bonded is enlarged, as shown in FIG. 4, an adhesive 9 is interposed between the electrode 2 and the flexible wiring board 1. Therefore, in thermosonic bonding in which ultrasonic waves are applied while heating, the adhesive 9 softens due to heat and absorbs ultrasonic waves, resulting in poor wire bonding properties. In Fig. 4, 10 is Cu foil, 11 is Ni plating layer, 12 is A
This is a U plating layer, and the thickness of this Au plating layer 12 is 0.
A thickness of 5 μm or more is required, which is a factor in high cost.

薄型実装手段として、ＴＡＢ　（Ｔａｐｅ　Ａｕｔｏｍ
ａｔｅｄＢｏｎｄｉｎｇ）が用いられるが、このやり方
はワイヤボンディング方式に比してコストが高く、汎用
性のあるものではない。As a thin mounting means, TAB (Tape Auto
bonding) is used, but this method is more costly than the wire bonding method and is not as versatile.

（発明の目的） ところで、本発明ではワイヤボンディングにおいて、第
一次接合側であるポール側ボンディングの接合状態が非
常に良好であることから、このポール側ボンディングを
フレキシブル基板の電極として使用し、そして、従来の
ワイヤボンディングにおける第一次接合側と第二次接合
側とを交換し、ワイヤルーピングを低くおさえることに
着目したものである。(Object of the invention) By the way, in the present invention, in wire bonding, since the bonding condition of the pole side bonding, which is the primary bonding side, is very good, this pole side bonding is used as an electrode of a flexible substrate, and This method focuses on suppressing wire looping by replacing the primary bonding side and the secondary bonding side in conventional wire bonding.

しかしながら、従来のワイヤボンディングにおける第二
次接合であるウェッジ側のボンディングを半導体チップ
に適用すると、超音波出力が大きいことから、半導体チ
ップにクラックが入ること、また、半導体チップ３にお
いてエツジショートを起こし易いことの問題を生じる。However, when wedge-side bonding, which is the secondary bonding in conventional wire bonding, is applied to a semiconductor chip, the large ultrasonic output may cause cracks in the semiconductor chip and cause edge shorts in the semiconductor chip 3. This creates a simple problem.

本発明は、これらの問題を解決し、薄型化を実現しうる
ワイヤボンディングを提供することを目的とするもので
ある。The present invention aims to solve these problems and provide wire bonding that can be made thinner.

（発明の構成） 本発明は、前記目的を達成するために、半導体チップ側
電極とフレキシブル配線板側電極とをＡｕワイヤにより
接続するフレキシブル配線板におけるワイヤボンディン
グ法において、先ず半導体チップ側電極にＡｕボールに
よるＡｕバンプを形成し、次にフレキシブル配線板側電
極に対してＡｕワイヤの先端に形成したＡｕボールを介
して第一次接合を行い、次いで半導体チップ側電極に形
成した前記ＡｕバンプにＡｕワイヤをウェッジ状の第二
次接合を行うことを特徴とするものである。(Structure of the Invention) In order to achieve the above-mentioned object, the present invention is directed to a wire bonding method for a flexible wiring board in which an electrode on the semiconductor chip side and an electrode on the flexible wiring board are connected by an Au wire. Au bumps are formed using balls, and then primary bonding is performed to the electrodes on the flexible wiring board via the Au balls formed at the tips of the Au wires, and then Au bumps are formed on the Au bumps formed on the electrodes on the semiconductor chip side. This method is characterized by performing secondary bonding of wires in a wedge shape.

以下、本発明の実施例を図面により説明する。Embodiments of the present invention will be described below with reference to the drawings.

第１図（ａ）から（ｆ）は、本発明のボンディングの工
程を順次示した説明図である。第１図の各図において、
ポリイミド等からなるフレキシブル配線１上には、半導
体チップ３が配置され、この半導体チップ３上のＡＩ！
、電極と接続されるフレキシブル配線板側電極２の端子
が半導体チップ３の近傍に設けられている。FIGS. 1(a) to 1(f) are explanatory diagrams sequentially showing the bonding steps of the present invention. In each figure in Figure 1,
A semiconductor chip 3 is arranged on a flexible wiring 1 made of polyimide or the like, and AI!
, a terminal of the flexible wiring board side electrode 2 to be connected to the electrode is provided near the semiconductor chip 3.

先ず、接続されるため用いられるワイヤであるＡｕワイ
ヤ４を支持したキャピラリ５を半導体チップ３側の上方
に位置せしめ、Ａｕワイヤ４の先端はトーチ電極６によ
ってＡｕボール７を形成する（第１図（ａ）の状態）。First, a capillary 5 supporting an Au wire 4, which is a wire used for connection, is positioned above the semiconductor chip 3 side, and the tip of the Au wire 4 is formed into an Au ball 7 by a torch electrode 6 (see Fig. 1). (a) condition).

このＡｕワイヤ４の先端に形成されたＡｕボール７を第
１図ら）に示すように、半導体チップ３に設けられた電
極に接着させる。The Au ball 7 formed at the tip of the Au wire 4 is bonded to an electrode provided on the semiconductor chip 3, as shown in FIG. 1 et al.

次に、前記Ａｕボール７を半導体チップ３上に残すため
、キャピラリ５は上方への移動時にＡｕワイヤ４を締め
付けることにより、Ａｕボール７をＡｕワイヤ４の先端
から切り取り、この結果、半導体チップ３上にはＡｕバ
ンプ７Ａが形成される。この後、Ａｕワイヤ４の先端に
は、トーチ電極６により新たにＡｕボール８が形成され
る（第１図（Ｃ）　）。Next, in order to leave the Au ball 7 on the semiconductor chip 3, the capillary 5 tightens the Au wire 4 when moving upward to cut off the Au ball 7 from the tip of the Au wire 4. As a result, the semiconductor chip 3 Au bumps 7A are formed thereon. Thereafter, a new Au ball 8 is formed at the tip of the Au wire 4 by the torch electrode 6 (FIG. 1(C)).

Ａｕボール８を有するＡｕワイヤ４はキャピラリ５と共
にフレキシブル配線板１の電極２の端子部に移動され、
Ａｕワイヤ４はその先端に形成したＡｕボール８を前記
電極２の端子に接続する（第１図（ロ））。そして、Ａ
ｕワイヤ４の他端を半導体チップ３上のＡｕバンプ７Ａ
に接続するため、キャピラリ５よりＡｕワイヤ４を所定
の長さだけ引き出して、第１図（ｅ）に示すように、Ａ
ｕワイヤ４の接合部をＡｕバンプ７Ａ上に高温状態に加
圧して接着する。The Au wire 4 having the Au ball 8 is moved together with the capillary 5 to the terminal part of the electrode 2 of the flexible wiring board 1,
An Au ball 8 formed at the tip of the Au wire 4 is connected to the terminal of the electrode 2 (FIG. 1(b)). And A
Connect the other end of the U wire 4 to the Au bump 7A on the semiconductor chip 3.
In order to connect to the A
The joint portion of the U wire 4 is bonded onto the Au bump 7A by applying pressure at high temperature.

しかる後、キャピラリ５の上方への移動の際に、Ａｕワ
イヤ４は接合端で切断され、次の接合作業のために、Ａ
ｕワイヤ４の端部に次の工程のためのＡｕボール７を形
成する（第１図（ｆ））。Thereafter, when the capillary 5 moves upward, the Au wire 4 is cut at the joining end, and the Au wire 4 is cut off at the joining end, and the Au wire 4 is
An Au ball 7 for the next step is formed at the end of the U wire 4 (FIG. 1(f)).

よって、本発明では、先ず半導体チップ３上にＡｕバン
プ７Ａを形成し、次に第一次接合としてフレキシブル配
線板１の電極２にＡｕワイヤ４の一端をボール側ボンデ
ィングにより固定し、第二次接合として半導体チップ３
のＡｕバンプ７Ａにワイヤ４の他端をウェッジ側ボンデ
ィングにより固定し、第１図（ｆ）で示される状態とな
る。Therefore, in the present invention, first, the Au bumps 7A are formed on the semiconductor chip 3, then one end of the Au wire 4 is fixed to the electrode 2 of the flexible wiring board 1 by ball side bonding as the primary bonding, and the second Au bump 7A is formed on the semiconductor chip 3. Semiconductor chip 3 as a junction
The other end of the wire 4 is fixed to the Au bump 7A by wedge side bonding, resulting in the state shown in FIG. 1(f).

第２図には、本発明のワイヤボンディング法を適用して
得られたＡｕワイヤの取付部の構成が示されている。Ａ
ｕワイヤ４の一端とフレキシブル配線板１の電極２端子
とをボール側接合による第一次接合を行い、次いでＡｕ
ワイヤ４の他端を半導体チップ３の電極端子に形成した
Ａｕバンプ７Ａとウェッジ側接合による第二次接合を行
った結果、半導体チップ３の表面からのＡｕワイヤのル
ーピングの高さを充分低く押さえることができ、このた
めフレキシブル配線板に対してのＡｕワイヤの取り付け
を薄型状となすことを可能とした。FIG. 2 shows the configuration of the Au wire attachment part obtained by applying the wire bonding method of the present invention. A
Primary bonding is performed by ball side bonding between one end of the U wire 4 and the electrode 2 terminal of the flexible wiring board 1, and then Au
As a result of secondary bonding of the other end of the wire 4 to the Au bump 7A formed on the electrode terminal of the semiconductor chip 3 by wedge side bonding, the height of the looping of the Au wire from the surface of the semiconductor chip 3 is kept sufficiently low. This made it possible to attach the Au wire to the flexible wiring board in a thin manner.

また、−次接合であるボール側接合をフレキシブル配線
板の電極端子側と接合することにより、フレキシブル配
線板１の電極におけるＡｕメツキ層８の厚みを０．１μ
ｍと薄くすることができる。In addition, by joining the ball side joint, which is a negative joint, to the electrode terminal side of the flexible wiring board, the thickness of the Au plating layer 8 on the electrode of the flexible wiring board 1 can be reduced to 0.1 μm.
It can be made as thin as m.

更に、半導体チップ３の表面にＡｕバンプを形成したこ
とにより、第二次接合側のウェッジ接合される際に超音
波出力は吸収され、半導体チップ３にクランクを生じる
ことなく、またエツジショートを阻止する作用をもたら
す。Furthermore, by forming Au bumps on the surface of the semiconductor chip 3, the ultrasonic output is absorbed when the wedge bonding is performed on the secondary bonding side, thereby preventing cranking of the semiconductor chip 3 and preventing edge shorts. It has the effect of

（発明の効果） 本発明により、フレキシブル配線板に対するワイヤボン
ディングにおいて薄型化を実現しうる効果を有し、Ａｕ
ワイヤのルーピングの高さを半導体チップ上面から約０
．１閣の高さに押さえることができ、ＩＣカード等にお
ける薄型化実装手段として好適である。更に、本発明で
は、半導体チップに対して第二次接合としてのウェッジ
側ボンディングを行う場合に生じるチップクラックやエ
ツジショートを旨く解決した利点を有し、フレキシブル
配線板上の電極のＡｕメツキ層の厚みを薄くすることが
でき、コストの低減がはかれる利点を有する。(Effects of the Invention) The present invention has the effect of realizing thinning in wire bonding to flexible wiring boards, and
The height of the wire looping is approximately 0 from the top surface of the semiconductor chip.
．． The height can be reduced to one cabinet, making it suitable as a means for thinning IC cards and the like. Furthermore, the present invention has the advantage of successfully solving the problem of chip cracks and edge shorts that occur when wedge-side bonding is performed as secondary bonding to semiconductor chips. It has the advantage that the thickness can be reduced and costs can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　、　（ｂ）　、　（Ｃ）　、　（ｄ）　
、　（ｅ）　、　（ｆ）は本発明のワイヤボンディング
の工程を順次示した概略断面図、 第２図は本発明のワイヤボンディングによるＡｕワイヤ
の取付状態を示す概略断面図、第３図は従来のワイヤボ
ンディングによるＡｕワイヤの取付状態を示す概略断面
図、 第４図は第３図のＩＶ−ＩＶ線による拡大断面図。 １・・・フレキシブル配線板、２・・・フレキシブル配
線板側の電極、３・・・半導体チップ、４・・・Ａｕワ
イヤ。 第１図Figure 1 (a), (b), (C), (d)
, (e) and (f) are schematic cross-sectional views sequentially showing the wire bonding process of the present invention. FIG. 2 is a schematic cross-sectional view showing the attachment state of Au wire by wire bonding of the present invention. FIG. FIG. 4 is an enlarged sectional view taken along the line IV-IV in FIG. 3; DESCRIPTION OF SYMBOLS 1... Flexible wiring board, 2... Electrode on the flexible wiring board side, 3... Semiconductor chip, 4... Au wire. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップ側電極とフレキシブル配線板側電極とを
Ａｕワイヤにより接続するフレキシブル配線板における
ワイヤボンディング法において、先ず半導体チップ側電
極にＡｕボールによるＡｕバンプを形成し、次にフレキ
シブル配線板側電極に対してＡｕワイヤの先端に形成し
たＡｕボールを介して第一次接合を行い、次いで半導体
チップ側電極に形成した前記ＡｕバンプにＡｕワイヤを
ウエッジ状の第二次接合を行うことを特徴とするフレキ
シブル配線板におけるワイヤボンディング法。In the wire bonding method for a flexible wiring board that connects an electrode on the semiconductor chip side and an electrode on the flexible wiring board side using an Au wire, first an Au bump is formed using an Au ball on the electrode on the semiconductor chip side, and then an Au bump is formed on the electrode on the flexible wiring board side. A flexible device characterized in that primary bonding is performed via an Au ball formed at the tip of an Au wire, and then secondary bonding is performed in a wedge shape with the Au wire to the Au bump formed on the semiconductor chip side electrode. Wire bonding method for wiring boards.
JP63124011A 1988-05-23 1988-05-23 Wire bonding method in flexible wiring board Pending JPH01293626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63124011A JPH01293626A (en) 1988-05-23 1988-05-23 Wire bonding method in flexible wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63124011A JPH01293626A (en) 1988-05-23 1988-05-23 Wire bonding method in flexible wiring board

Publications (1)

Publication Number Publication Date
JPH01293626A true JPH01293626A (en) 1989-11-27

Family

ID=14874814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63124011A Pending JPH01293626A (en) 1988-05-23 1988-05-23 Wire bonding method in flexible wiring board

Country Status (1)

Country Link
JP (1) JPH01293626A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04241432A (en) * 1991-01-14 1992-08-28 Rohm Co Ltd Wire bonding structure between semiconductor chip and substrate mounted with same
JPH04294552A (en) * 1991-03-25 1992-10-19 Matsushita Electron Corp Wire-bonding method
WO1994022166A1 (en) * 1993-03-19 1994-09-29 National Semiconductor Corporation A method of and arrangement for bond wire connecting together certain integrated circuit components
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
WO1998021780A3 (en) * 1996-11-11 1998-06-25 Siemens Ag A connection between two contacts and a process for producing such a connection
US6079610A (en) * 1996-10-07 2000-06-27 Denso Corporation Wire bonding method
US6420256B1 (en) * 1997-04-22 2002-07-16 Micron Technology, Inc. Method of improving interconnect of semiconductor devices by using a flattened ball bond
WO2002078080A1 (en) * 2001-03-23 2002-10-03 Koninklijke Philips Electronics N.V. Chip module with bond-wire connections with small loop height
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
US6946380B2 (en) 2002-02-19 2005-09-20 Seiko Epson Corporation Method for forming bump, semiconductor element having bumps and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US7404513B2 (en) 2004-12-30 2008-07-29 Texas Instruments Incorporated Wire bonds having pressure-absorbing balls

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04241432A (en) * 1991-01-14 1992-08-28 Rohm Co Ltd Wire bonding structure between semiconductor chip and substrate mounted with same
JPH04294552A (en) * 1991-03-25 1992-10-19 Matsushita Electron Corp Wire-bonding method
WO1994022166A1 (en) * 1993-03-19 1994-09-29 National Semiconductor Corporation A method of and arrangement for bond wire connecting together certain integrated circuit components
EP0753891A3 (en) * 1995-06-28 1999-03-31 Texas Instruments Incorporated Low loop wire bonding
EP0753891A2 (en) * 1995-06-28 1997-01-15 Texas Instruments Incorporated Low loop wire bonding
US6079610A (en) * 1996-10-07 2000-06-27 Denso Corporation Wire bonding method
WO1998021780A3 (en) * 1996-11-11 1998-06-25 Siemens Ag A connection between two contacts and a process for producing such a connection
US6420256B1 (en) * 1997-04-22 2002-07-16 Micron Technology, Inc. Method of improving interconnect of semiconductor devices by using a flattened ball bond
US6624059B2 (en) 1997-04-22 2003-09-23 Micron Technology, Inc. Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
WO2002078080A1 (en) * 2001-03-23 2002-10-03 Koninklijke Philips Electronics N.V. Chip module with bond-wire connections with small loop height
WO2002082527A1 (en) * 2001-04-05 2002-10-17 Stmicroelectronics Pte Ltd Method of forming electrical connections
US6946380B2 (en) 2002-02-19 2005-09-20 Seiko Epson Corporation Method for forming bump, semiconductor element having bumps and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US7176570B2 (en) 2002-02-19 2007-02-13 Seiko Epson Corporation Method for forming bump, semiconductor element having bumps and method of manufacturing the same, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US7404513B2 (en) 2004-12-30 2008-07-29 Texas Instruments Incorporated Wire bonds having pressure-absorbing balls

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