JPH03231435A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03231435A JPH03231435A JP2740490A JP2740490A JPH03231435A JP H03231435 A JPH03231435 A JP H03231435A JP 2740490 A JP2740490 A JP 2740490A JP 2740490 A JP2740490 A JP 2740490A JP H03231435 A JPH03231435 A JP H03231435A
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- semiconductor chip
- expansion coefficient
- film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 230000002093 peripheral effect Effects 0.000 claims 1
- 230000008646 thermal stress Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 5
- 239000009719 polyimide resin Substances 0.000 abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229920006231 aramid fiber Polymers 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 abstract description 2
- 229910000833 kovar Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229920006332 epoxy adhesive Polymers 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004382 potting Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- -1 42 alloy or Kovar Chemical compound 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- CLDVQCMGOSGNIW-UHFFFAOYSA-N nickel tin Chemical compound [Ni].[Sn] CLDVQCMGOSGNIW-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、特にＴＡ Ｂ（
Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）方式
により実装される半導体集積回路装置の高信頼化に適用
して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a TAB (
The present invention relates to a technique that is effective when applied to increase the reliability of a semiconductor integrated circuit device mounted by a tape automated bonding (Tape Automated Bonding) method.
絶縁フィルムの表面にパターン形成されたリード配線の
一端（インナーリード部）にバンプ電極を介して半導体
チップをボンディングしたＴＡＢ（フィルムキャリヤと
もいう）は、ＬＳＩの多ビン化、薄形化に好適な実装方
式として注目されている。上記ＴＡＢは、ポリイミド樹
脂などの可撓性フィルムの一面に接合された銅箔をエツ
チングしてリード配線を形成し、半導体チップまたはリ
ード配線に設けたバンプ電極を介して半導体チップとリ
ード配線とをギヤングボンディングにて接続した後、半
導体チップをポツティング樹脂で封止したものである。TAB (also called a film carrier), in which a semiconductor chip is bonded to one end (inner lead part) of lead wiring patterned on the surface of an insulating film via a bump electrode, is suitable for increasing the number of bins and making thinner LSIs. It is attracting attention as an implementation method. In the TAB, lead wiring is formed by etching a copper foil bonded to one surface of a flexible film such as polyimide resin, and the semiconductor chip and lead wiring are connected via bump electrodes provided on the semiconductor chip or lead wiring. After connecting by gigantic bonding, the semiconductor chip is sealed with potting resin.
なお、上記ＴＡＢの現状と動向について記載された文献
の例としては、株式会社プレスジャーナル、平成元年５
月２０日発行の「月刊セミコンダクターワールド・６月
号ＪＰＩＯ７〜Ｐ１３１がある。An example of a document describing the current status and trends of TAB mentioned above is Press Journal Co., Ltd., 1989 5.
There is "Monthly Semiconductor World June issue JPIO7-P131" published on the 20th of May.
上記ＴＡＢは、シリコン単結晶からなる半導体チップよ
りも熱膨張係数が大きい合成樹脂からなる絶縁フィルム
に接合されたリード配線と上記半導体チップとをバンプ
電極を介して電気的に接続するため、上記フィルムと半
導体チップとの熱膨張係数差に起因してバンプ電極に熱
ストレスが集中し、バンプ電極と半導体チップとの接続
強度あるいはバンプ電極とリード配線との接続強度が低
下して断線不良を引き起こし易いという欠点があった。The TAB is designed to electrically connect the semiconductor chip to the lead wires bonded to an insulating film made of synthetic resin having a coefficient of thermal expansion larger than that of the semiconductor chip made of single crystal silicon through bump electrodes. Due to the difference in thermal expansion coefficient between the semiconductor chip and the semiconductor chip, thermal stress concentrates on the bump electrode, reducing the connection strength between the bump electrode and the semiconductor chip or the connection strength between the bump electrode and lead wiring, which tends to cause disconnection defects. There was a drawback.
特に近年の多ピン対応形ＴＡＢは、半導体チップの周辺
部のみならずアクティブエリアにもバンプ電極を設ける
エリア・アレイ・テープ方式を採用しているたｔ、熱膨
張時にフィルムが反り易く、特にチップ周辺部のバンプ
電極に大きな熱ストレスが集中するという構造上の問題
点を有している。In particular, recent multi-pin TABs have adopted an area array tape method in which bump electrodes are provided not only at the periphery of the semiconductor chip but also in the active area. This has a structural problem in that a large amount of thermal stress is concentrated on the bump electrodes in the periphery.
本発明の目的は、フィルムと半導体チップとの熱膨張係
数差に起因するバンプ電極への熱ストレス集中を改善し
、ＴＡＢの高信頼化を実現することのできる技術を提供
することにある。An object of the present invention is to provide a technology that can improve the concentration of thermal stress on bump electrodes due to the difference in coefficient of thermal expansion between the film and the semiconductor chip, and achieve high reliability of TAB.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書のｇ己述および添付図面から明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the written description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本発明は、絶縁フィルムの熱膨張係数を半導体チップの
熱膨張係数と整合させたＴＡＢ方式の半導体集積回路装
置である。The present invention is a TAB type semiconductor integrated circuit device in which the coefficient of thermal expansion of an insulating film is matched with the coefficient of thermal expansion of a semiconductor chip.
上記した手段によれば、絶縁フィルムの熱膨張係数を半
導体チップの熱膨張係数と整合させることにより、バン
プ電極への熱ストレス集中を低減することができるので
、バンプ電極の接続信頼性が向上する。According to the above means, by matching the thermal expansion coefficient of the insulating film with the thermal expansion coefficient of the semiconductor chip, it is possible to reduce the concentration of thermal stress on the bump electrodes, thereby improving the connection reliability of the bump electrodes. .
第１図は、本発明の一実施例であるＴＡＢ １の断面構
造を示している。本実施例のＴＡＢＩは、いわゆるエリ
ア・アレイ・テープ方式を採用したものである。ンリコ
ン単結晶からなる半導体チ・ツブ２は、その下面が集積
回路形成面をなしており、上言己集積回路形成面には、
例えばゲートアレイやマイクロコンピュータなどの論理
ＬＳＩが形成されている。上記集積回路形成面の周辺部
に設けられた電極３ａ上には、バンプ電極４ａが接合さ
れている。また上記集積回路形成面の中央部、すなわち
アクティブエリアに設けられた電極３ｂ上には、バンプ
電＆４ｂが接合されている。上記バンプ電極４ａ、４ｂ
は、例えば鉛−錫合金（半田）からなる。FIG. 1 shows a cross-sectional structure of TAB 1, which is an embodiment of the present invention. The TABI of this embodiment employs a so-called area array tape system. The semiconductor chip 2 made of silicon single crystal has its lower surface serving as an integrated circuit forming surface, and the integrated circuit forming surface has the following features:
For example, logic LSIs such as gate arrays and microcomputers are formed. A bump electrode 4a is bonded onto the electrode 3a provided at the periphery of the integrated circuit forming surface. Further, a bump electrode &4b is bonded to the electrode 3b provided in the central portion of the integrated circuit forming surface, that is, the active area. The bump electrodes 4a, 4b
is made of, for example, a lead-tin alloy (solder).
上記半導体チップ２は、上記バンプ電極４ａ。The semiconductor chip 2 includes the bump electrodes 4a.
４ｂを介して絶縁フィルム５の表面にパターン形成され
たリード配線５ａ、５ｂと電気的に接続されている。バ
ンプ電極４ａは、絶縁フィルム５の上面に形成されたリ
ード配線６ａに直接接続されており、バンプ電極４ｂは
、絶縁フィルム５の下面に形成されたリード配線６ｂに
スルーホール７を通じて接続されている。上記半導体チ
ップ２は、例えばエポキシ樹脂からなるポツティング樹
脂８によって気密封止されている。It is electrically connected to lead wires 5a and 5b patterned on the surface of the insulating film 5 via the lead wires 4b. The bump electrode 4a is directly connected to a lead wiring 6a formed on the upper surface of the insulating film 5, and the bump electrode 4b is connected to a lead wiring 6b formed on the lower surface of the insulating film 5 through a through hole 7. . The semiconductor chip 2 is hermetically sealed with a potting resin 8 made of, for example, epoxy resin.
上記絶縁フィルム５は、その熱膨張係数を上記半導体チ
ップ２の熱膨張係数と整合させるため、例えばポリイミ
ド樹脂にシリカ（Ｓ１０２）あるいはアラミド繊維など
を含浸させた低熱膨張材料にて構成されている。また絶
縁フィルム５を低熱膨張材料で構成したことに伴い、リ
ード配線６ａ。The insulating film 5 is made of a low thermal expansion material such as polyimide resin impregnated with silica (S102) or aramid fiber, in order to match its thermal expansion coefficient with that of the semiconductor chip 2. Further, since the insulating film 5 is made of a low thermal expansion material, the lead wiring 6a.
６ｂは、例えば４２アロイやコバールなどのように銅よ
りも熱膨張係数の小さい材料で構成し、その表面にニッ
ケルー金（またはニッケルー錫）などのメツキを施した
ものを使用する。さらに上記リード配線１３ａ、５ｂを
絶縁フィルム５に接合するための接着剤も、エポキシ樹
脂系接着剤に比べて熱膨張係数の小さいポリイミド樹脂
を使用する。The material 6b is made of a material having a coefficient of thermal expansion smaller than that of copper, such as 42 alloy or Kovar, and has its surface plated with nickel-gold (or nickel-tin). Further, as the adhesive for bonding the lead wires 13a, 5b to the insulating film 5, a polyimide resin having a smaller coefficient of thermal expansion than an epoxy resin adhesive is used.
上記ＴＡＢ １は、例えば半導体チップ２の電極３ａ、
３ｂ上にバンプ電極４ａ、４ｂを形成した後、上記半導
体チップ２を絶縁フィルム５０所定箇所に位置決めして
バンプ電極４ａ、４ｂをリフローさせてボンディングを
行った後、半導体チップ２をボッティング樹脂８にて気
密封止することにより組立てられる。The TAB 1 is, for example, an electrode 3a of a semiconductor chip 2,
After forming the bump electrodes 4a and 4b on the insulating film 50, the semiconductor chip 2 is positioned at a predetermined location on the insulating film 50, and the bump electrodes 4a and 4b are reflowed and bonded. It is assembled by hermetically sealing it.
以上の構成からなる本実施例のＴＡＢ １によれば、絶
縁フィルム５の熱膨張係数を半導体チップ２の熱膨張係
数と整合させたことにより、熱膨張時における絶縁フィ
ルム５の反りが低減され、バンプ電極４ａ、４ｂへの熱
ストレス集中が低減されるため、バンプ電極４ａ、４ｂ
の接続信頼性が向上する。According to the TAB 1 of this embodiment having the above configuration, by matching the thermal expansion coefficient of the insulating film 5 with the thermal expansion coefficient of the semiconductor chip 2, warpage of the insulating film 5 during thermal expansion is reduced, Since the concentration of thermal stress on the bump electrodes 4a, 4b is reduced, the bump electrodes 4a, 4b
connection reliability is improved.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
前記実施例では、エリア・アレイ・テープ方式のＴＡＢ
に適用した場合について説明したが、半導体チップの周
辺部に設けたバンプ電極上にリード配線をギヤングボン
ディングする方式のＴＡＢに適用することもできる。In the above embodiment, the area array tape type TAB
Although the present invention has been described with reference to a case where it is applied to a semiconductor chip, the present invention can also be applied to a TAB system in which lead wires are gang-bonded onto bump electrodes provided on the periphery of a semiconductor chip.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
絶縁フィルムの表面にパターン形成されたリード配線に
バンプ電極を介して半導体チップをボンディングしてな
るＴＡＢ方式の半導体集積回路装置において、前記絶縁
フィルムの熱膨張係数を前記半導体チップの熱膨張係数
と整合させることにより、バンプ電極への熱ストレス集
中が低減され、バンプ電極の接続信頼性が向上するので
、ＴＡＢの高信頼化を実現することができる。In a TAB type semiconductor integrated circuit device in which a semiconductor chip is bonded to lead wiring patterned on the surface of an insulating film via bump electrodes, the coefficient of thermal expansion of the insulating film is matched to the coefficient of thermal expansion of the semiconductor chip. By doing so, the concentration of thermal stress on the bump electrodes is reduced and the connection reliability of the bump electrodes is improved, so that high reliability of the TAB can be realized.
第１図は、本発明の一実施例である半導体集積回路装置
の要部断面図である。
１・・・ＴＡＢ、２・・・半導体チップ、３ａ。
３ｂ・・・電極、４ａ、４ｂ・・・バンプ電極、５・・
・絶縁フィルム、５ａ、５ｂ・・・リード配線、７・・
・スルーホール、８・・・ポツティング樹脂。FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device which is an embodiment of the present invention. 1...TAB, 2...Semiconductor chip, 3a. 3b... Electrode, 4a, 4b... Bump electrode, 5...
・Insulating film, 5a, 5b...Lead wiring, 7...
・Through hole, 8...Potting resin.
Claims (1)
線にバンプ電極を介して半導体チップをボンディングす
るＴＡＢ方式の半導体集積回路装置であって、前記絶縁
性フィルムの熱膨張係数を前記半導体チップの熱膨張係
数と整合させたことを特徴とする半導体集積回路装置。 ２、前記バンプ電極は、前記半導体チップの周辺部およ
びアクティブエリアに設けられていることを特徴とする
請求項１記載の半導体集積回路装置。[Claims] 1. A TAB type semiconductor integrated circuit device in which a semiconductor chip is bonded via bump electrodes to lead wiring patterned on the surface of an insulating film, wherein the thermal expansion coefficient of the insulating film is A semiconductor integrated circuit device, characterized in that the coefficient of thermal expansion is matched to that of the semiconductor chip. 2. The semiconductor integrated circuit device according to claim 1, wherein the bump electrodes are provided in a peripheral area and an active area of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2027404A JP2858844B2 (en) | 1990-02-07 | 1990-02-07 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2027404A JP2858844B2 (en) | 1990-02-07 | 1990-02-07 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03231435A true JPH03231435A (en) | 1991-10-15 |
| JP2858844B2 JP2858844B2 (en) | 1999-02-17 |
Family
ID=12220136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2027404A Expired - Fee Related JP2858844B2 (en) | 1990-02-07 | 1990-02-07 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2858844B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5880530A (en) * | 1996-03-29 | 1999-03-09 | Intel Corporation | Multiregion solder interconnection structure |
| US6404051B1 (en) | 1992-08-27 | 2002-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device having a protruding bump electrode |
| US6498422B1 (en) * | 1998-09-02 | 2002-12-24 | Murata Manufacturing Co., Ltd. | Electronic component such as an saw device and method for producing the same |
-
1990
- 1990-02-07 JP JP2027404A patent/JP2858844B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6404051B1 (en) | 1992-08-27 | 2002-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device having a protruding bump electrode |
| US6605522B1 (en) | 1992-08-27 | 2003-08-12 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device having a protruding bump electrode |
| US5880530A (en) * | 1996-03-29 | 1999-03-09 | Intel Corporation | Multiregion solder interconnection structure |
| US6030854A (en) * | 1996-03-29 | 2000-02-29 | Intel Corporation | Method for producing a multilayer interconnection structure |
| US6498422B1 (en) * | 1998-09-02 | 2002-12-24 | Murata Manufacturing Co., Ltd. | Electronic component such as an saw device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2858844B2 (en) | 1999-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6218728B1 (en) | Mold-BGA-type semiconductor device and method for making the same | |
| US5894107A (en) | Chip-size package (CSP) using a multi-layer laminated lead frame | |
| JPH03142847A (en) | Semiconductor integrated circuit device | |
| JPH01303730A (en) | Mounting structure of semiconductor element and manufacture thereof | |
| JP2001110930A (en) | Semiconductor device | |
| JPH03231435A (en) | Semiconductor integrated circuit device | |
| JPH0563138A (en) | Semiconductor integrated circuit device | |
| US20020125568A1 (en) | Method Of Fabricating Chip-Scale Packages And Resulting Structures | |
| JP2002289741A (en) | Semiconductor device | |
| JPH06120296A (en) | Semiconductor integrated circuit device | |
| JP2756791B2 (en) | Resin-sealed semiconductor device | |
| JPH09199631A (en) | Structure and fabrication method of semiconductor device | |
| JP2705281B2 (en) | Semiconductor device mounting structure | |
| JP3965767B2 (en) | Semiconductor chip substrate mounting structure | |
| JP2551243B2 (en) | Semiconductor device | |
| JP2871575B2 (en) | Lead frame, method of manufacturing the same, resin-sealed semiconductor device and method of manufacturing the same | |
| JPS62199022A (en) | Mounting means of semiconductor device | |
| JPH0451056B2 (en) | ||
| JPH11204565A (en) | Semiconductor device | |
| JP3145892B2 (en) | Resin-sealed semiconductor device | |
| JP3127948B2 (en) | Semiconductor package and mounting method thereof | |
| JP2000021920A (en) | Semiconductor device | |
| JPH07297313A (en) | Semiconductor device and manufacture thereof | |
| JPH09306953A (en) | Bare chip-mounted semiconductor device and manufacture thereof | |
| JPH0496240A (en) | Semiconductor integrated circuit device and device thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071204 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081204 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |