JPH01273389A - Manufacture of ceramic multilayer interconnection substrate - Google Patents
Manufacture of ceramic multilayer interconnection substrateInfo
- Publication number
- JPH01273389A JPH01273389A JP10327388A JP10327388A JPH01273389A JP H01273389 A JPH01273389 A JP H01273389A JP 10327388 A JP10327388 A JP 10327388A JP 10327388 A JP10327388 A JP 10327388A JP H01273389 A JPH01273389 A JP H01273389A
- Authority
- JP
- Japan
- Prior art keywords
- sheet
- ceramic multilayer
- via hole
- insulator
- conductor paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 title abstract 2
- 239000012212 insulator Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 238000007639 printing Methods 0.000 claims abstract description 12
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 9
- 238000010304 firing Methods 0.000 claims description 3
- 230000002950 deficient Effects 0.000 abstract 2
- 239000011521 glass Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000007569 slipcasting Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はセラミック多層配線基板の製造方法に関し、特
にとア・ホールへの導体ペーストの印刷、及び絶縁体シ
ートの積層に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a ceramic multilayer wiring board, and particularly to printing conductive paste on holes and laminating insulating sheets.
従来、この種のセラミック多層配線基板の製造方法は、
第3図(a)〜(d)に示す様に、絶縁体シート1dを
一括して積層し、焼成していた。Conventionally, the manufacturing method for this type of ceramic multilayer wiring board is as follows:
As shown in FIGS. 3(a) to 3(d), insulating sheets 1d were laminated all at once and fired.
上述した従来のセラミック多層配線基板の製造方法では
、各絶縁シートに個別に導体ペーストを印刷している。In the above-described conventional method for manufacturing a ceramic multilayer wiring board, a conductive paste is individually printed on each insulating sheet.
そのため、第4図に示す様にビアホールに導体ペースト
2bを充填した後、絶縁体シート1dを印刷テーブル5
がら取る時、印刷テーブル5に導体ペースト2bが付着
し、ビアホール内の導体ペースト2bが欠落する。この
ため、ビアホール内への導体ペースト充填が不十分とな
り、ビアホールにおいて導通不良が発生するという欠点
がある。Therefore, as shown in FIG. 4, after filling the via hole with the conductive paste 2b, the insulating sheet 1d is placed on the printing table 5.
When removing the bulk, the conductive paste 2b adheres to the printing table 5, and the conductive paste 2b inside the via hole is missing. For this reason, there is a drawback that the filling of the conductive paste into the via hole becomes insufficient, resulting in poor conduction in the via hole.
本発明の目的は、絶縁シートに形成されたビアホールに
充填された導体ペーストの欠落が無くなリ、ビアホール
の導通不良を防止できるセラミック多層配線基板の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a ceramic multilayer wiring board that eliminates the loss of the conductive paste filled in the via holes formed in an insulating sheet and prevents conduction defects in the via holes.
本発明のセラミック多層配線基板の製造方法は、配線導
体及びビアホールが所定の位置に形成された複数の絶縁
体シートを積層し、焼成して得られるセラミック多層配
線基板の製造方法において、配線導体が形成された第1
の絶縁体シート上に、第2の絶縁体シートを第1の絶縁
体シートの配線導体と第2の絶縁体シートに形成された
ビアホールとを接続させて積層し、第2の絶縁体シート
に形成された前記ビアホール内に導体ペーストを印刷す
る工程とを含んで構成される。The method for manufacturing a ceramic multilayer wiring board of the present invention is a method for manufacturing a ceramic multilayer wiring board obtained by laminating and firing a plurality of insulator sheets in which wiring conductors and via holes are formed at predetermined positions. first formed
A second insulator sheet is laminated on the insulator sheet by connecting the wiring conductor of the first insulator sheet and the via hole formed in the second insulator sheet. The method includes a step of printing a conductive paste in the formed via hole.
次に、本発明について図面を参照して説明する。第1図
(a)〜(d)は、本発明の一実施例を説明するために
工程順に示した多層配線基板の断面図である。絶縁体シ
ート、la、lbはアルミナ粉末、ガラス粉末、溶剤、
有機バインダを容器内で混練した泥漿をスリップ・キャ
スティング方式で成膜・乾燥した厚さ80μmのセラミ
ック・グリーン・シートである。導体ペースト2aは銀
85重量%、パラジウム15重量%の金属粉末を有機ビ
ヒクル中に均一分散させたものである。Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views of a multilayer wiring board shown in order of steps to explain an embodiment of the present invention. Insulator sheet, LA, LB are alumina powder, glass powder, solvent,
This is a ceramic green sheet with a thickness of 80 μm, which is made by slip-casting a slurry mixed with an organic binder in a container and dried. The conductor paste 2a is made by uniformly dispersing metal powder containing 85% by weight of silver and 15% by weight of palladium in an organic vehicle.
絶縁体シート1aに導体ペースト2aを印刷した後、φ
0.25mmのビアホールを穿孔した絶縁体シート1b
を重ね合わせ、温度100℃、圧力50kg/■2で熱
圧着して積層した後、導体ペースト2bを印刷する。After printing the conductor paste 2a on the insulator sheet 1a, φ
Insulator sheet 1b with 0.25mm via hole punched
The conductor paste 2b is printed on the conductive paste 2b after stacking them by thermocompression bonding at a temperature of 100° C. and a pressure of 50 kg/cm2.
その後、必要に応じて積層、印刷をくり返し、所定の絶
縁体シートの積層体を得る。次いで、この積層体を温度
100℃、圧力300kg/cm2にて、再度熱圧着し
た後、800〜900℃にて焼成し、セラミック多層配
線基板を得る。Thereafter, lamination and printing are repeated as necessary to obtain a predetermined laminate of insulating sheets. Next, this laminate is thermocompressed again at a temperature of 100 DEG C. and a pressure of 300 kg/cm<2>, and then fired at 800 to 900 DEG C. to obtain a ceramic multilayer wiring board.
第1表に従来の製造方法と、本実施例の製造方法とによ
り得られたセラミック多層配線基板のビアホールの導通
率を示す。Table 1 shows the conductivity of via holes in ceramic multilayer wiring boards obtained by the conventional manufacturing method and the manufacturing method of this example.
第1表
絶縁体シートは20層で、ビアホールは各絶縁体シート
の同一位置にありセラミック多層配線基板の上下両面を
接続している。導通率は、セラミック多層配線基板の両
面の間でビアホールに導通のある場合であり、セラミッ
ク多層配線基板の両面を接続する1000個のビアホー
ルについて測定した。The insulator sheets shown in Table 1 have 20 layers, and the via holes are located at the same position in each insulator sheet, connecting the upper and lower surfaces of the ceramic multilayer wiring board. The conductivity was measured when there was conduction in the via hole between both sides of the ceramic multilayer wiring board, and was measured for 1000 via holes connecting both sides of the ceramic multilayer wiring board.
第2図は本発明の他の実施例により形成されたセラミッ
ク多層配線基板の断面図である。絶縁体シート1cはセ
ラミック・グリーンシートにφ0.25+u+のビアホ
ール3を形成した後、焼成した厚さ100μmのセラミ
ックシートである。FIG. 2 is a sectional view of a ceramic multilayer wiring board formed according to another embodiment of the present invention. The insulator sheet 1c is a ceramic sheet having a thickness of 100 μm, which is obtained by forming a via hole 3 of φ0.25+u+ in a ceramic green sheet and then firing it.
この絶縁体シートICをガラスペースト4を用いて接着
し、積層を行うが、1層積層する毎に導体ペースト2a
を印刷し、ビアホールの充填と配線の印刷を行なう。こ
のようにして得た積層体を400℃にて再焼成し、一体
化させる。This insulating sheet IC is bonded and laminated using glass paste 4, but every time one layer is laminated, conductor paste 2a
Fill the via holes and print the wiring. The thus obtained laminate is refired at 400° C. to be integrated.
この実施例では積層後、ビアホールにペーストを充填す
る事になるため、絶縁体シートICの間にガラスペース
ト4が存在しても印刷時に導体ペースト2aは、ビアホ
ール3を抜けて下の絶縁体シート上の導体ペースト2b
と接触する事によりビアホールの導通が確保される。In this embodiment, the via holes are filled with paste after lamination, so even if the glass paste 4 is present between the insulating sheets IC, the conductive paste 2a passes through the via holes 3 during printing and is placed on the insulating sheet below. Upper conductor paste 2b
By contacting with, conduction of the via hole is ensured.
第2表に従来の製造方法と本実施例の製造方法によって
得られた、セラミック多層配線基板のビアホールの導通
率を示す。Table 2 shows the conductivity of via holes in ceramic multilayer wiring boards obtained by the conventional manufacturing method and the manufacturing method of this example.
第2表
絶縁シートは、20層で、ビアホールの構造は、第1の
実施例と同一であり、セラミック多層配線基板の上下両
面を接続する1000個のビアホールについて導通を測
定した時の導通率である。The insulating sheet in Table 2 has 20 layers, and the structure of the via holes is the same as in the first example. be.
以上説明したように本発明は、導体ペーストを印刷した
絶縁体シート上に次の層の絶縁体シートを積層後、導体
ペーストを印刷する事により、ビアホールに充填された
導体ペーストの欠落が無くなり、ビアホールの導通不良
を防止できる効果がある。As explained above, in the present invention, by printing the conductive paste after laminating the next layer of insulating sheets on the insulating sheet printed with the conductive paste, there is no loss of the conductive paste filled in the via hole. This has the effect of preventing conduction defects in via holes.
第1図(a)〜(d)は、本発明の一実施例を説明する
ために工程順に示したセラミック多層配線基板の断面図
、第2図は、本発明の他の実施例により形成されたセラ
ミック多層配線基板の断面図、第3図(a)〜(d)は
従来のセラミック多層配線基板の製造方法を説明するた
めの工程別の断面図、第4図は第3図(c)の部分拡大
図及び印刷テーブルに付着した導体ペーストの拡大断面
図である。FIGS. 1(a) to (d) are cross-sectional views of a ceramic multilayer wiring board shown in order of process to explain one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a ceramic multilayer wiring board formed according to another embodiment of the present invention. 3(a) to 3(d) are cross-sectional views of each process for explaining a conventional method of manufacturing a ceramic multilayer wiring board, and FIG. 4 is a sectional view of FIG. 3(c). FIG. 2 is a partially enlarged view of FIG.
1a、lb、lc、ld−絶縁体シート、2a。1a, lb, lc, ld - insulator sheet, 2a.
2b、2c・・・導体ペースト、3・・・ビアホール、
4・・・ガラスペースト、5・・・印刷テーブル。2b, 2c...conductor paste, 3...via hole,
4...Glass paste, 5...Printing table.
Claims (1)
の絶縁体シートを積層し、焼成して得られるセラミック
多層配線基板の製造方法において、配線導体が形成され
た第1の絶縁体シート上に、第2の絶縁体シートを第1
の絶縁体シートの配線導体と第2の絶縁体シートに形成
されたビアホールとを接続させて積層し、第2の絶縁体
シートに形成された前記ビアホール内に導体ペーストを
印刷する工程とを含むことを特徴とするセラミック多層
配線基板の製造方法。In a method for manufacturing a ceramic multilayer wiring board obtained by laminating and firing a plurality of insulating sheets in which wiring conductors and via holes are formed at predetermined positions, on a first insulating sheet in which wiring conductors are formed, the second insulator sheet to the first
connecting and stacking the wiring conductor of the insulator sheet and the via hole formed in the second insulator sheet, and printing a conductive paste in the via hole formed in the second insulator sheet. A method for manufacturing a ceramic multilayer wiring board, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10327388A JPH01273389A (en) | 1988-04-25 | 1988-04-25 | Manufacture of ceramic multilayer interconnection substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10327388A JPH01273389A (en) | 1988-04-25 | 1988-04-25 | Manufacture of ceramic multilayer interconnection substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01273389A true JPH01273389A (en) | 1989-11-01 |
Family
ID=14349778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10327388A Pending JPH01273389A (en) | 1988-04-25 | 1988-04-25 | Manufacture of ceramic multilayer interconnection substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01273389A (en) |
-
1988
- 1988-04-25 JP JP10327388A patent/JPH01273389A/en active Pending
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