JPH05267854A - Ceramic multilayer circuit board and manufacture thereof - Google Patents

Ceramic multilayer circuit board and manufacture thereof

Info

Publication number
JPH05267854A
JPH05267854A JP4065715A JP6571592A JPH05267854A JP H05267854 A JPH05267854 A JP H05267854A JP 4065715 A JP4065715 A JP 4065715A JP 6571592 A JP6571592 A JP 6571592A JP H05267854 A JPH05267854 A JP H05267854A
Authority
JP
Japan
Prior art keywords
resistor
ceramic
boards
inner layer
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4065715A
Other languages
Japanese (ja)
Inventor
Shinichiro Inui
信一郎 乾
Eiichiro Hirose
英一郎 広瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP4065715A priority Critical patent/JPH05267854A/en
Publication of JPH05267854A publication Critical patent/JPH05267854A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily obtain a ceramic multilayer circuit board in which an accurately trimmed resistor is formed as an inner layer by providing the trimmed resistor in the inner layer interposed between a plurality of ceramic boards. CONSTITUTION:A plurality of alumina boards are prepared, through holes 2 are formed at the respective boards, and then Ag/Pd paste is filled in the holes 2 by a screen printing method. Then, a conductor wiring pattern 3 is printed, dried, baked, then a resistor 4 is printed, baked, and trimmed to form a resistor 4 having a target resistance. Thereafter, glass 5 for adhering the boards to each other is printed except the upper part of the resistor 4, conductor protrusions 6 are formed, the boards 1 are superposed to each other, the glass paste 5 is melted to adhere the boards to each other, and the boards are electrically conducted through the protrusions 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器等に使用され
るセラミック多層配線基板およびその製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic multilayer wiring board used for electronic equipment and the like and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、セラミック多層配線基板を製造す
る方法としては、 (1)アルミナ純度92〜95%のグリーンシートに、
金型等を使用して穴加工を行った後に、W,Mo等の導
体ペーストでスルーホール導体,配線を印刷し、各層の
グリーンシートを積層,圧着して1500〜1600
℃,H2+N2+水蒸気雰囲気で焼成することによって
セラミック多層配線基板を得る方法(グリーンシート積
層法、従来タイプ) (2)アルミナ、ムライト、コージェライト等のセラミ
ック成分とガラス粉末を適当な割合で混合した原料から
800〜900℃の比較的低温で焼成が可能なグリーン
シートを作成し、上記(1)と同様な方法で導体を形
成,圧着し、導体に応じた雰囲気で焼成する(Ag/P
d,Auは空気、CuはN2)ことによってセラミック
多層配線基板を得る方法(グリーンシート積層法、低温
焼成タイプ) 等があった。
2. Description of the Related Art Conventionally, as a method for manufacturing a ceramic multilayer wiring board, (1) a green sheet having an alumina purity of 92 to 95%,
After making holes using a die, etc., print through-hole conductors and wiring with a conductor paste such as W and Mo, stack green sheets of each layer, and press-bond them to 1500-1600.
Method for obtaining a ceramic multilayer wiring board by firing in an atmosphere of H2 + N2 + steam at ℃ (green sheet lamination method, conventional type) To 800 to 900 ° C., a green sheet that can be fired at a relatively low temperature is prepared, a conductor is formed and pressure-bonded in the same manner as in (1) above, and fired in an atmosphere suitable for the conductor (Ag / P
There is a method (green sheet lamination method, low temperature firing type) of obtaining a ceramic multilayer wiring substrate by using air for d and Au and N2 for Cu.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記(1)の
方法においては、焼成温度が高いこと、還元雰囲気を使
用すること等の理由により、内層の抵抗体として使用可
能な材料がなかった。また、上記(2)の方法において
は、従来アルミナ基板用として使用されてきた酸化ルテ
ニウムを主な導電成分とする厚膜抵抗体が使用可能であ
るが、この方法においても、全てのペーストが印刷,乾
燥された後に、グリーンシートが圧着,焼成されるため
に、抵抗体と基板成分との相互拡散による抵抗値の変動
が大きく、また厚膜抵抗体の抵抗値調整法として通常使
用されるレーザトリミング技術を使うことができず、実
用に足る精度をもった抵抗体を得ることができなかっ
た。
However, in the above method (1), there is no material that can be used as the resistor of the inner layer because of the high firing temperature and the use of a reducing atmosphere. Further, in the method (2), a thick film resistor having ruthenium oxide as a main conductive component, which has been conventionally used for an alumina substrate, can be used. However, even in this method, all pastes are printed. Since the green sheet is pressure-bonded and baked after being dried, there is a large variation in the resistance value due to the mutual diffusion of the resistor and the substrate component, and a laser that is usually used as a method for adjusting the resistance value of thick film resistors. The trimming technology could not be used, and a resistor with sufficient accuracy for practical use could not be obtained.

【0004】本発明は、以上に説明したような、セラミ
ック多層配線基板の内層に実用に足る抵抗体が成形でき
ないという従来技術における問題点を解決し、高精度に
トリミングされた抵抗体が内層化されたセラミック多層
配線基板及びその製造方法を提供することを目的とす
る。
The present invention solves the problem in the prior art that a practically usable resistor cannot be formed in the inner layer of the ceramic multilayer wiring board as described above, and the resistor trimmed with high precision is formed into the inner layer. It is an object of the present invention to provide a ceramic multilayer wiring board and a manufacturing method thereof.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
の本発明のセラミック多層配線基板の製造方法は、複数
枚の焼成済みのセラミック基板に、配線パターン及び抵
抗体を印刷して焼成する工程と、前記抵抗体をトリミン
グする工程と、前記セラミック基板どうしを接合するガ
ラスを、該セラミック基板上に、前記抵抗体上及び前記
セラミック基板どうしの電気的接続部を除いて印刷する
工程と、前記電気的接続部に導体突起を印刷する工程
と、脱バインダー処理工程と、前記複数枚のセラミック
基板を互いに重ね合せて焼成する工程とを備えたことを
特徴とするものである。
In order to achieve the above object, a method for manufacturing a ceramic multilayer wiring board according to the present invention comprises a step of printing wiring patterns and resistors on a plurality of fired ceramic substrates and firing them. A step of trimming the resistor, and a step of printing glass for joining the ceramic substrates together on the ceramic substrate except for the electrical connection between the resistor and the ceramic substrate, The method is characterized by including a step of printing a conductor protrusion on the electrical connection portion, a debinding processing step, and a step of stacking and firing the plurality of ceramic substrates.

【0006】また、本発明のセラミック多層配線基板
は、複数のセラミック基板に挾まれた内層に、トリミン
グされた抵抗体を備えたことを特徴とするものであり、
複数のセラミック基板に挾まれた内層の、前記抵抗体が
形成された領域を除く領域に上記複数のセラミック基板
を接合するガラスが挾み込まれてなることが好ましい。
The ceramic multilayer wiring board of the present invention is characterized in that an inner layer sandwiched between a plurality of ceramic boards is provided with trimmed resistors.
It is preferable that glass for joining the plurality of ceramic substrates is sandwiched in a region of the inner layer sandwiched between the plurality of ceramic substrates except the region where the resistor is formed.

【0007】[0007]

【作用】本発明においては、予め焼成された基板を個々
の内層基板として使用することにより、抵抗体の焼成、
トリミングが可能となる。更に、接合用のガラスを抵抗
体上部に印刷しないことによって、抵抗体と接合用ガラ
スとの相互作用を避けることができ、通常のアルミナセ
ラミック基板上に形成する場合と同様の特性の優れた抵
抗体を備えたセラミック多層基板を得ることができる。
In the present invention, by using a pre-fired substrate as an individual inner layer substrate,
Trimming is possible. Furthermore, by not printing the bonding glass on the resistor, the interaction between the resistor and the bonding glass can be avoided, and the excellent resistance with the same characteristics as when forming on a normal alumina ceramic substrate. A ceramic multilayer substrate with a body can be obtained.

【0008】[0008]

【実施例】以下に、図面を参照して、内層に150Ωの
抵抗体を有するセラミック多層配線基板の製造工程の実
施例を示す。厚み0.1mm,外形50.8×50.8
mmのアルミナ基板1を複数枚準備し(図1(a))、
このアルミナ基板1にレーザ加工機で直径0.1mmの
スルーホール2を加工した(図1(b))。次にデュポ
ン社のAg/Pdペースト6502をスクリーン印刷法
にてスルーホールに充填し(図1(c))、続いてスク
リーン印刷法にて導体配線パターンを印刷,乾燥し、8
50℃10分キープトータル1時間プロファイルにて焼
成した(図1(d))。以下の焼成,接合条件も同様で
ある。乾燥は最高温度150℃5分キープトータル15
分とした(以下の乾燥条件も同様である)。次に抵抗体
4を印刷,焼成した(図1(e))。ここでは抵抗体4
としてデュポン社の抵抗体6820(100Ω/□)を
用いた。予察実験により、脱バインダー,接合の熱処理
工程によって、抵抗値が21%ドリフトすることが判っ
ているため、目標値を124Ωとしてトリミングを行
い、トリミングされた抵抗体4’を形成した(図1
(f))。
EXAMPLE An example of a manufacturing process of a ceramic multilayer wiring board having a resistor of 150Ω in an inner layer will be described below with reference to the drawings. Thickness 0.1mm, external shape 50.8 × 50.8
A plurality of mm alumina substrates 1 are prepared (FIG. 1A),
A through hole 2 having a diameter of 0.1 mm was processed on this alumina substrate 1 by a laser processing machine (FIG. 1 (b)). Next, Ag / Pd paste 6502 manufactured by DuPont is filled in the through holes by a screen printing method (FIG. 1C), and subsequently, a conductor wiring pattern is printed by a screen printing method and dried.
Firing was performed at a profile of 50 ° C. for 10 minutes and a total of 1 hour (FIG. 1 (d)). The same applies to the following firing and joining conditions. Maximum temperature is 150 ° C for 5 minutes. Keep total 15
Minutes (the same applies to the following drying conditions). Next, the resistor 4 was printed and fired (FIG. 1E). Here, resistor 4
As the resistor, a resistor 6820 (100Ω / □) manufactured by DuPont was used. Preliminary experiments show that the resistance value drifts by 21% due to the heat treatment process of debinding and joining, so trimming was performed with a target value of 124Ω to form trimmed resistor 4 ′ (FIG. 1).
(F)).

【0009】トリミング後、抵抗体4’の上部およびそ
の後に印刷される導体突起の箇所を除いて、基板どうし
を接着するためのガラス5を印刷した(図2(g))。
ガラスはNFE社の1129TCを使用した。次にデュ
ポン社の導体ペースト6502を使用して、基板間の電
気的導通を取るための導体突起6を印刷,乾燥した(図
2(h))。次に、脱バインダーのための熱処理を最高
温度500℃,10分キープ,トータル1時間の条件で
行い、各層の基板を重ね合せて、1kgの荷重を加えな
がら接合することによって、ガラスペースト5が溶融し
て、基板どうしが接着されるとともに、導体突起6が焼
結し、基板間の電気的導通が達成された(図2
(i))。多層基板の表面に引き出した端子を使用して
内層された抵抗体の抵抗値を測定したところ、156Ω
であり、目標値150Ωに対して精度4%の抵抗体が得
られた。
After trimming, the glass 5 for adhering the substrates to each other was printed except for the upper portion of the resistor 4'and the conductive protrusions to be printed thereafter (FIG. 2 (g)).
As the glass, 1129TC manufactured by NFE was used. Next, a conductive paste 6502 manufactured by DuPont was used to print and dry the conductive protrusions 6 for establishing electrical conduction between the substrates (FIG. 2 (h)). Next, a heat treatment for debinding is performed under the conditions of a maximum temperature of 500 ° C., keeping for 10 minutes, and total time of 1 hour, and the substrates of the respective layers are superposed and bonded with each other while applying a load of 1 kg. The substrates were melted and adhered to each other, and the conductor protrusions 6 were sintered to achieve electrical conduction between the substrates (FIG. 2).
(I)). When the resistance value of the internal resistor was measured using the terminal drawn out on the surface of the multilayer board, it was 156Ω.
Therefore, a resistor having an accuracy of 4% was obtained with respect to the target value of 150Ω.

【0010】[0010]

【発明の効果】以上、本発明により高精度な内層抵抗体
が搭載されたセラミック層配線基板が構成された。
As described above, according to the present invention, the ceramic layer wiring board on which the highly accurate inner layer resistor is mounted is constructed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係るセラミック多層配線基
板の製造工程を示した図である。
FIG. 1 is a diagram showing a manufacturing process of a ceramic multilayer wiring board according to an embodiment of the present invention.

【図2】本発明の一実施例に係るセラミック多層配線基
板の製造工程を示した図である。
FIG. 2 is a diagram showing a manufacturing process of a ceramic multilayer wiring board according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 焼成済セラミック基板 2 スルーホー
ル 3 導体配線パターン 4 抵抗体 4’ トリミング後の抵抗体 5 ガラス 6 導体突起
1 Fired Ceramic Substrate 2 Through Hole 3 Conductor Wiring Pattern 4 Resistor 4'Resistor after Trimming 5 Glass 6 Conductor Protrusion

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数枚のセラミック基板に挾まれた内層
に、トリミングされた抵抗体を備えたことを特徴とする
セラミック多層配線基板。
1. A ceramic multi-layer wiring board comprising an inner layer sandwiched between a plurality of ceramic boards and trimmed resistors.
【請求項2】 複数枚のセラミック基板に挾まれた内層
の、前記抵抗体が形成された領域を除く領域に前記複数
のセラミック基板を接合するガラスが挾み込まれてなる
ことを特徴とする請求項1記載のセラミック多層配線基
板。
2. The glass for joining the plurality of ceramic substrates is sandwiched between the regions of the inner layer sandwiched between the plurality of ceramic substrates except the region where the resistor is formed. The ceramic multilayer wiring board according to claim 1.
【請求項3】 複数枚の焼成済みのセラミック基板に、
配線パターン及び抵抗体を印刷して焼成する工程と、 前記抵抗体をトリミングする工程と、 前記セラミック基板どうしを接合するガラスを、該セラ
ミック基板上に、前記抵抗体上及び前記セラミック基板
どうしの電気的接続部を除いて印刷する工程と、 前記電気的接続部に導体突起を印刷する工程と、 脱バインダー処理工程と、 前記複数枚のセラミック基板を互いに重ね合せて焼成す
る工程とを備えたことを特徴とするセラミック多層配線
基板の製造方法。
3. A plurality of fired ceramic substrates,
A step of printing a wiring pattern and a resistor and baking the same; a step of trimming the resistor; and a glass for joining the ceramic substrates together on the ceramic substrate, an electrical connection between the resistor and the ceramic substrate. The step of printing without the electrical connection portion, the step of printing a conductive protrusion on the electrical connection portion, the step of removing the binder, and the step of firing the plurality of ceramic substrates by superposing them on each other. A method for manufacturing a ceramic multilayer wiring board, comprising:
JP4065715A 1992-03-24 1992-03-24 Ceramic multilayer circuit board and manufacture thereof Pending JPH05267854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4065715A JPH05267854A (en) 1992-03-24 1992-03-24 Ceramic multilayer circuit board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4065715A JPH05267854A (en) 1992-03-24 1992-03-24 Ceramic multilayer circuit board and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05267854A true JPH05267854A (en) 1993-10-15

Family

ID=13294998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4065715A Pending JPH05267854A (en) 1992-03-24 1992-03-24 Ceramic multilayer circuit board and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05267854A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000151114A (en) * 1998-11-11 2000-05-30 Sony Corp Multilayer board and manufacture thereof
JP2010062522A (en) * 2008-09-05 2010-03-18 Samsung Electro-Mechanics Co Ltd Multilayer ceramic circuit substrate and method of manufacturing the same
JP2017527123A (en) * 2014-09-09 2017-09-14 セラムテック ゲゼルシャフト ミット ベシュレンクテル ハフツングCeramTec GmbH Multi-layer cooling body
JP2020521340A (en) * 2017-06-29 2020-07-16 ディーアイティー カンパニー リミテッドDit Co.,Ltd. Multilayer ceramic substrate and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000151114A (en) * 1998-11-11 2000-05-30 Sony Corp Multilayer board and manufacture thereof
JP2010062522A (en) * 2008-09-05 2010-03-18 Samsung Electro-Mechanics Co Ltd Multilayer ceramic circuit substrate and method of manufacturing the same
US8106306B2 (en) 2008-09-05 2012-01-31 Samsung Electro-Mechanics Co., Ltd. Ceramic multi-layer circuit substrate and manufacturing method thereof
JP2017527123A (en) * 2014-09-09 2017-09-14 セラムテック ゲゼルシャフト ミット ベシュレンクテル ハフツングCeramTec GmbH Multi-layer cooling body
JP2020521340A (en) * 2017-06-29 2020-07-16 ディーアイティー カンパニー リミテッドDit Co.,Ltd. Multilayer ceramic substrate and manufacturing method thereof

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