JPH0126548B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an insulation-separated bipolar integrated circuit, and more particularly, an object of the present invention is to take out electrodes of a substrate of an insulation-separated bipolar integrated circuit from the surface of the integrated circuit.

Higher speed, lower power consumption of bipolar integrated circuits,
A number of devices with miniaturized structures for the purpose of higher density have already been proposed, and among them, bipolar integrated circuits with insulation isolation, in which the conventional P-type isolation region is replaced with an oxide film, have been proposed due to the decrease in capacitance and miniaturization. This structure is advantageous in that it has a promising future.

Figure 1 shows a cross-sectional view of the structure of a conventional isolated bipolar IC. In the figure, 1 is a P-type semiconductor substrate, 2
is an n ⁺ buried layer, 3 is a p ⁺ buried layer as a channel stopper, 4 is an n-type epitaxial layer which is a collector region, 5 is a P-type base region, and 6 is an n ⁺ region for making a collector contact. , 7 is n ⁺
8 is an isolation oxide film for separating the transistors, 9 is an oxide film for separating the collector and the base, and 10 is an oxide film for separating the base electrode and the emitter electrode.

As you can see from the structure in Figure 1, the insulation isolation method is
Since many of the junction sides are insulating films, the junction capacitance is reduced, which is advantageous for speeding up. It has advantages such as being suitable for miniaturization of transistor cells because a dimensional margin between the isolation insulating film and the base or emitter is unnecessary. However, the conventional pn-operated isolation structure has a serious drawback in that, because there is no p-type isolation region, the potential of the substrate can only be applied from the back side. The fact that the potential of the substrate cannot be applied from the surface has the adverse effect of making latch-up more likely. That is, one major cause of latch-up in normal bipolar ICs is that the substrate potential is uniform throughout the IC and cannot be fixed at the lowest potential. Therefore, in order to prevent this, it is preferable to apply the substrate potential at locations where latch-up is likely to occur as much as possible through wiring rather than on the surface. This becomes especially noticeable when the epitaxial layer of an IC is made thinner in order to increase the size or miniaturize the IC.

The present invention corrects the above-mentioned drawbacks and proposes an isolated bipolar integrated circuit in which contact can be made with the substrate from the surface of the IC.

The configuration of the present invention will be shown below with reference to the drawings. FIG. 2 shows a sectional view of an embodiment of the present invention. 1 to 1 in the diagram
The elements up to 0 are the same as those in FIG. 1
Reference numeral 1 denotes a p-type diffusion region, which serves both as a high concentration region as a channel stopper and as a high concentration region for making contact with the substrate. 12 is an isolation insulating film formed by a selective oxidation method.
13, 14, 15, and 16 are substrate, base, emitter, and collector electrodes, respectively. In other words, the feature of FIG. 2 is that the p-type diffusion region 11 and the isolation insulating film 12
It is particularly characterized by its formation method.

Next, an embodiment of the manufacturing method of the present invention will be described with reference to FIG. First, as shown in step A, a p-type buried region 21 and an n-type buried region 22 are formed on a p-type semiconductor substrate 1.
After selectively forming the n-type epitaxial layer 23 on the epitaxial layer 23, the first base oxide film 24 is formed on the epitaxial layer 23, and then the first nitride film 25 is formed. Thereafter, the epitaxial layer 23 is selectively etched halfway using the first nitride film 25 and the first base oxide film 24 as a mask. The steps up to this point are the same as the conventional insulation separation process.

Next, as shown in step B, the second base oxide film 2
6 is formed, and further a second nitride film 27 is formed.

Next, as shown in step C, first, the second nitride film 2
After selectively removing 7 by photo-etching, the second base oxide film 26 is etched using the second nitride film 27 as a mask. Furthermore, at this time,
As shown in step C, the second nitride film 27 and the second base oxide film 26 are left in a part of the region where the epitaxial layer 23 is partially etched, which will become an isolation region in the future.

Next, in this state, isolation oxidation is performed by high pressure oxidation to separate each island region 4 formed of the epitaxial layer.
After separating the first and second nitride films 25, 27
Then, the first and second base oxide films 24 and 26 are removed. Step D shows the state at this time. In the figure, 2 is an n-type buried region, 3 is a p-type buried region forming a channel stopper, 8 and 12 are isolation insulating films, and 11 is the same p-type buried region as 3. As shown, during the oxidation of the insulating film, diffusion from the p-type buried region 21 progresses into the epitaxial layer 4, and the p-type is inverted to the surface, which becomes a contact region for taking out the electrode to the substrate. . Note that this region may not be sufficiently inverted to the p-type depending on the impurity concentration of the p-type buried region 21 and the conditions of high-pressure oxidation, so this region is also opened at the same time in the subsequent base diffusion step, and the p-type becomes p-type. In some cases, form impurities are added.

The steps up to D above are the characteristics of the present invention. Therefore, Step E and the subsequent steps are the same as those for conventional isolated bipolar integrated circuits.

That is, after step D, an isolation oxide film 9 is formed to separate the base region 5 and the collector region 4, and an oxide film is further formed on the entire surface. A hole is opened only in the base region, and p-type impurities are diffused to form the base region. form 5. At this time, as described above, holes are also opened in the contact region to the substrate at the same time to diffuse p-type impurities. After this, an oxide film is again formed on the entire surface, holes are opened only in the areas where emitter diffusion is to be performed, and n-type impurities are diffused.
Emitter 7 and collector contact region 6 are formed. Thereafter, electrode contacts are formed to complete the structure shown in FIG.

To summarize the above characteristics, after etching the epitaxial layer in the region where the isolation insulating film is to be formed, a second Si ₃ N ₄ film is provided, and then the insulating film is formed by oxidation. No isolation oxide film is formed under the Si ₃ N ₄ film of No. 2, and this portion is used as an electrode outlet to the p-type substrate.

As described above based on the embodiments, according to the present invention, an isolated type bipolar structure having a contact region to the substrate in the isolation region can be manufactured relatively easily and without requiring a large occupied area. It is possible to obtain integrated circuits such as the following. Moreover, the advantage of the present invention is that there is no process that affects each profile of the transistor, so it is possible to maintain the characteristics of the transistor as before.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a conventional isolation type bipolar integrated circuit, FIG. 2 is a sectional view showing an integrated circuit according to an embodiment of the present invention, and FIGS. 3 A to E are an embodiment of the present invention. FIG. 3 is a process cross-sectional view showing a method of manufacturing an integrated circuit. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 4, 23...n-type epitaxial layer, 5...base region, 11...p-type diffusion region, 12...isolation insulating film, 13...substrate electrode, 24...th 1 base oxide film, 25... first nitride film, 26... second base oxide film, 27... second nitride film.

Claims (1)

[Scope of Claims] 1. A first base oxide film, a first base oxide film on a semiconductor layer of a second conductivity type formed on the semiconductor substrate of the first conductivity type in which regions of the first conductivity type are selectively formed. forming a nitride film, selectively opening holes in the first nitride film and a first base oxide film, etching a portion of the semiconductor layer to form a recess, and forming a second base oxide film. A second nitride film is formed on the entire surface, the second nitride film and the second base oxide film are selectively removed, and the second nitride film is formed in a part of the recess of the semiconductor layer. selectively oxidizes a portion of the recessed portion of the semiconductor layer that is not covered with the first and second nitride films and the base oxide film, leaving behind the nitride film and the second base oxide film, and oxidizes the second nitride film. and a method for manufacturing a semiconductor device, comprising removing the second base oxide film and forming an electrode on the exposed region. 2. In the region of the semiconductor layer covered by the second nitride film and the second base oxide film and not oxidized,
2. The method of manufacturing a semiconductor device according to claim 1, wherein impurities of the first conductivity type are added at the same time as forming the base.