JPH01259566A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To improve the efficiency of write and erase operations of a reloadable fixed storage element, by installing both specific semiconductor storage element and insulated gate type transistor on one semiconductor substrate. CONSTITUTION:A logical element MOS transistor TL of LDD structure and a reloadable fixed storage element not of LDD structure--EPROM (TM) are installed on one semiconductor substrate. This means that a logical element short-channelized for high integration and a high speed operation is composed of the insulated gate type transistor TL of LDD structure for prevention of the changes of the element characteristic caused by the formation of hot carrier. The reloadable fixed storage element TM having a floating gate is not of LDD structure and a drain area 16 and a source area 17 are directly connected with the lower part of a gate 14 to enhance the electric field strength of the edge of the drain 16. This improves the efficiency of write and erase operations.

Description

[Detailed Description of the Invention] [Summary] A semiconductor device and its manufacturing method, particularly an MO3 type semiconductor device in which a rewritable semiconductor memory element having a floating gate and an LDD structure logic element are provided, and its manufacturing method. Regarding the improvement, the purpose is to improve the writing and erasing efficiency of the above-mentioned rewritable fixed memory element. A semiconductor memory element having a region and storing information by storing charge in the lower gate, and a semiconductor memory element having a single-layer gate and having the drain and source region between the drain and source region and the gate lower region. The present invention relates to a semiconductor device in which an insulated gate transistor having an offset Hi region with a lower impurity concentration than the drain and source regions having the same conductivity type is arranged on the same semiconductor substrate, and a method for manufacturing the same.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, particularly an EFROM.
Alternatively, the present invention relates to improvements in a semiconductor device in which a semiconductor memory element with a multilayer gate structure including a floating gate such as an E"FROM and an insulated gate transistor with an LDD structure are provided together, and a method for manufacturing the same.

Recently, in semiconductor ICs such as microcomputers that have both logic elements and fixed memory elements, EPRO is used as the fixed memory element in order to increase the number of data processing functions.
Semiconductor memory elements such as M and E2PROM, which have a multilayer gate structure including a floating gate and are capable of rewriting data, are increasingly being used.

On the other hand, as these semiconductor ICs become more highly integrated, the insulated gate transistors disposed as logic elements in these ICs are becoming short-channeled, and their characteristics change due to hot carriers generated when they are short-channeled. In order to prevent data processing in such a semiconductor IC in which an L[lD product structure insulated gate transistor is used, an offset region with a low impurity concentration is provided between the drain and source regions with a high impurity concentration and the lower gate region. In order to improve the speed, we are increasing the speed of logic circuit operation consisting of insulated gate transistors with LDD structure and EM? OM and E2P
It is desired to improve the rewriting efficiency of fixed storage elements such as ROM.

[Conventional technology]

Conventionally, a semiconductor device in which the above-mentioned rewritable semiconductor memory element, such as an EFROM, and an insulated gate transistor with an LDD structure as a logic element are provided together is shown in FIGS.
It was formed by the steps described below with reference to.

FIG. 4 (see al), that is, for example, a field oxide film 52 on a p-type silicon (St) substrate 51 and a p-type channel stopper 5 below the field oxide film 52.
3, the first and second element forming regions 5 are defined by
A first gate oxide film 56 is formed on the first element formation region 54 by a normal method using a substrate to be processed having a diameter of 4.55.
, a first floating gate electrode 57 made of poly-SiN, a second gate oxide film 58, and a control gate snowflake 59 made of second poly-Si are sequentially laminated to form a multilayer gate Gd of a memory element, and On the second element formation region 55, a single layer gate Gs of a logic element is formed by laminating a first gate electrode 60 made of a second polySt layer on a second gate oxide film 58, and then the above-mentioned Phosphorus (P4) is selectively applied to the first and second element forming regions 54 and 55 using the multilayer gate G4 and the single layer gate G as masks.
N-type regions 61, 62, 63, and 64, which will become drain and source offset regions, are formed by ion implantation at a low concentration.

FIG. 4 (see BL) Next, after washing out the exposed gate oxide films 56 and 58, an impurity blocking oxide film 65 is formed on the exposed Si surface, and then a layer of a thickness corresponding to the sidewall is formed on the substrate. A SiO2 film is grown in a vapor phase, and then the SiO2 film is grown by a reactive ion etching (RIE) process.
□ Etch bank the 5iOz film by etching the entire surface of the film to form the multilayer gate G.

A sidewall-like SiO□ film 66 made of the above SiO□ film is selectively formed on the side surfaces of the single-layer gate G and the single-layer gate G.

Referring to FIG. 4(C), a high concentration of arsenic (As'') is applied to the element forming regions 54 and 55 using the multilayer gate Gd and single layer gate GS including the sidewall-like 5in2 films 66 on both sides as masks.
is ion-implanted to form the first n1 type heavily doped drain region 68.
, a first n° type hot doped source region 69, a second n0 type heavily doped drain region 70, and a second n° type warm doped source region 71 are formed. Here, 67 indicates a through oxide film for preventing damage during ion implantation.

Therefore, in a conventional semiconductor device in which a rewritable semiconductor memory element having a multilayer gate such as an EPROM and a logic element consisting of an insulated gate transistor with an LDD structure are installed together, the semiconductor memory element described above inevitably has a high concentration. It had a structure in which low concentration offset regions 61 and 62 were interposed between the drain and source regions 69 and 70 and the lower region of the multilayer gate Ga where the channel was formed.

[Problem to be solved by the invention]

To achieve this, conventional EPs are installed alongside logic elements consisting of insulated gate transistors with an LDD structure on the same substrate.
In rewritable fixed memory elements such as ROM and E2PROM, due to the resistance of the low-concentration offset regions 61 and 62, a sufficient electric field is not concentrated on the drain side of the memory element, so that rewriting, writing, erasing, etc. There was a problem in that efficiency was significantly reduced.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to improve the writing and erasing efficiency of a rewritable fixed memory element that has a floating gate and is provided with an LDD structure logic element.

[Means to solve the problem]

The above problem is a semiconductor that has a multilayer gate including a floating lower gate, a drain region and a source region that are in direct contact with the lower region of the multilayer gate, and stores information by storing charge in the lower gate. Does it have a memory element, a single layer gate, a drain and a source? (2) An insulated gate transistor is provided with an offset region having the same conductivity type as the drain and source regions and a lower impurity concentration than the drain and source regions between the region and the lower gate region, and an insulated gate transistor is provided on the same semiconductor substrate. After forming a first gate insulating film on the first and second element formation regions of one conductivity type in which the semiconductor device and the semiconductor substrate are defined and exposed by an insulating film, simultaneously forming a covering body selectively covering the entire surface of the first element formation region with a conductor film and a first gate electrode selectively covering and crossing the second element formation region;
selectively introducing a first opposite conductivity type impurity for forming an offset region into the second element formation region using the first gate electrode as a mask; and forming an insulating film over the entire surface of the substrate. etching the entire surface of the insulating film using an anisotropic dry etching means to selectively leave the insulating film in a sidewall shape on the covering body and the side surface of the first gate electrode; After forming a second gate insulating film on the surface of the coating, forming a second gate electrode made of a second conductive film on the coating, and forming the coating in alignment with the second gate electrode. forming a floating third gate electrode under the second gate electrode, and applying a second opposite conductivity type impurity for forming the drain and source regions to the first element formation region. While selectively introducing the second and third gate electrodes using the second and third gate electrodes as masks, at the same time, selectively introducing four electrodes into the second element formation region using the first gate electrode including the sidewall-like insulating film as a mask. The problem is solved by a method for manufacturing a semiconductor device according to the present invention, which includes steps.

[For production]

That is, in the semiconductor device according to the present invention, since the insulated gate transistor used as the logic element is short-channeled, an offset region with a low impurity concentration is provided between the drain and source regions and the lower gate region. By suppressing the generation of hot carriers, variations in device characteristics are prevented.

In addition, a fixed memory element with a multilayer gate structure in which writing is performed by injecting hot carriers into the floating gate has a high impurity concentration without providing an offset region with a low impurity concentration between the drain and source regions and the lower gate region. The impurity-concentrated drain and source regions are placed in direct contact with the lower gate region where the channel is formed, so that the electric field strength at the gate-side edge of the drain region is sufficiently increased during writing and erasing, thereby preventing hot carriers. To make writing and erasing easier and more efficient by increasing the generation efficiency.

With the above, the information processing speed and reliability of the semiconductor device are improved.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view (
a) and a schematic plan view (b), FIGS. 2(a) to (g) are process sectional views of an embodiment of the method of the present invention, and FIGS.
fl is a process plan view of the same example.

Identical objects are indicated by the same reference numerals throughout the figures.

The semiconductor device according to the present invention is illustrated in FIGS. 1(a) and 1(b), for example.
As shown in FIG. 1, it has a structure in which an LDD structure MOS transistor (T), which is a logic element, and a rewritable fixed memory element, or EFROM (TM), which does not have an LDD structure are provided on the same semiconductor substrate.

In the figure, 1 is a p-type Si substrate, 2 is a field oxide film, 3 is a p-type channel stopper, 4 and 5 are first and second
, 6 is a first gate oxide film, 7 is a floating gate electrode of a memory element, 8 is a first gate electrode for driving a logic element, 9 and 10 are n-type offset regions, 11 is an A sidewall-like SiO□ film, 12 a second gate oxide film, 14 a control gate electrode of a memory element, and 16 a first n-type drain region 17 disposed in the memory element; A source region 18 is a second n-type drain region 19 disposed in the logic element.
This shows the n゛゛ source region of .

The semiconductor device according to the above embodiment is illustrated in FIG. 2 (
a) to (gl) and FIG. 3 (al to ([1)].

Refer to FIGS. 2(a) and 3(a). That is, as in the conventional art, for example, one surface of a p-type Si substrate is defined and exposed by a field oxide film 2 formed on the surface and a p-type channel stopper 3 below the field oxide film 2. A substrate to be processed having first and second element forming regions 4 and 5 is formed, and first a first layer is formed on the surfaces of the element forming regions 4 and 5 by thermal oxidation or the like.
After forming the gate oxide film 6, a normal vapor phase growth process,
After an impurity doping step and a patterning step, a poly-Si covering 107 made of a first poly-Si layer covering the first element forming region 4 and having conductivity is formed on the first element forming region 4, and a second
A first gate electrode 8 made of the same first poly-Si layer and crossing over the region 6 is formed on the element formation region 6 .

In FIG. 2(b) and FIG. 3 (see bll), the poly-Si coating 107, the first gate electrode 8
Then, using the field oxide film 2 as a mask, ions of phosphorus (P'') for forming an n-type offset region are selectively implanted into the second element formation region at a low concentration of about 10'6 to 1QI7c, -1.109 .110 indicates a low concentration P input region.

Refer to Figure 2 (C1 and Figure 3 (C)) Next, apply CVD-5 to a thickness of about 2,000 layers on the above substrate.
A 5iOz film is formed, and the entire surface is etched by RIB processing to etch back the CVD-5in film to form a residual sidewall-like 5iOz film 11 with a thickness of about 2000 on the side surface of the first gate electrode 8. . At this time, PolyS
A sidewall-like SiO□ film 11 is also formed on the side surface of the i-covering body 107.

The poly-Si coating 107 and the first gate electrode 8 are shown in FIG. 2 (d+ and FIG. 3 (dll)).
After forming a second gate oxide film 12 on the substrate by, for example, thermal oxidation, a second polysilicon film 12 with a thickness of about 4,000 mm is formed on the substrate.
After vapor-phase growing the i-layer and imparting conductivity to the second poly-Si layer, the second poly-Si layer is patterned using the resist pattern 13 as a mask to form a second poly-Si layer on the poly-Si coating 107. A control gate electrode 14 made of a poly-Si layer of
form.

Refer to FIG. 2 (el) and FIG. 3 (e). Next, the second element forming region 5 and the extending region of the first gate electrode 8 are covered with a resist film 15, and the resist pattern 13 and the control gate electrode 14 are covered with a resist film 15. The second gate oxide film 12 and poly-Si coating 107 are patterned using a mask, and a floating gate electrode 7 made of the first poly-Si layer is formed below the control gate electrode 14 via the second gate oxide film 12. form.

Refer to FIG. 2(f) and FIG. 3<n. Then, using the control gate electrode 7 as a mask, arsenic (As') is ion-implanted into the first element formation region 4 at a high concentration of about 10"am-', and At the same time, As'' is ion-implanted into the second element forming region 5 at the same concentration as above using the first gate electrode 8 having the sidewall-like SiO□ film 11 on the side surface as a mask, and a desired activation heat treatment is performed. A floating gate electrode 7 is formed in the first element formation region 4.
A first n-type drain region 1 directly in contact with a lower region of
6 and the source region 17, and an n-type offset region 9.10 in contact with the lower region of the first gate electrode 8 in the second element formation region 5, and an 2 n'' drain regions 18 and source regions 19 are formed.

FIG. 2 (see 0) Formation of impurity blocking oxide film 20, formation of interlayer insulating film 21, contact window 22.23.24.2
5 and the like, the word wiring 26 and bit wiring 27 of the memory element (T9) made of AI etc., and the drain wiring 28 and source wiring 29 of the logic element (TL) are formed, and the semiconductor device according to the present invention is completed. Complete.

As shown in the above embodiments, in the semiconductor device according to the present invention that is easily formed by the method of the present invention, logic elements that are short-channeled for the purpose of high integration and speeding up are caused by the generation of hot carriers. The LDD structure is used for a rewritable fixed memory element that is composed of an insulated gate transistor having an LDD structure to prevent variations in element characteristics and has a floating gate that is placed on the same substrate as the logic element. A rewritable fixed memory element is used in which the electric field strength at the end of the drain is increased by directly contacting the drain and source regions with the lower gate region without the need to form a gate, thereby increasing the efficiency of writing and erasing.

Therefore, the fixed memory element information can be rewritten efficiently and accurately, so that the information processing speed and information processing accuracy of the semiconductor device are improved.

Note that the present invention is of course applicable to the case where an E''FROM is used as a fixed memory element.

〔Effect of the invention〕

As explained above, according to the present invention, an EPROM or an E2PI that is installed together with an insulated gate transistor with an LDD structure?
The efficiency and accuracy of writing and erasing OM is improved.

Therefore, according to the present invention, it is possible to improve the operating speed and reliability of a highly integrated semiconductor IC in which an insulated gate transistor having an LDD structure, an EPROM, an EtPROM, etc. are provided together.

[Brief explanation of the drawing]

FIG. 1 is a schematic side sectional view (
a) and a schematic plan view (b), Fig. 2 (al to (g) are process sectional views of one embodiment of the method of the present invention, and Fig. 3 (al to (f) are one implementation of the method of the present invention A process plan view of the example, and FIGS. 4(a) to (C1 are process cross-sectional views of the conventional method. In the figure, =1 is a p-type Si substrate, 2 is a field oxide film, 3 is a p-type channel stopper, 4 and 5 are first and second element formation regions, 6 is a first gate oxide film, 7 is a floating gate electrode, 8 is a first gate electrode for driving a logic element, 9 and 10 are n-type 11 is a sidewall-like SiO□ film, 12 is a second gate oxide film, 14 is a control gate electrode, 16 is a first n-type drain region 17 is a first n-type source region, 18 is a first n-type drain region; The second n-type drain region 19 indicates the second n-type source region. TL is an L [IO tank structure MOS] transistor, and T2 is an EF transistor.
Indicates ROM. (Iri'1 f [Side view (b) Planar view of the Ming Dynasty's heron dispatch, the section of the tributary direction, the column of the two countries; Figure 13.

Claims (2)

[Claims] (1) Semiconductor memory that has a multilayered gate including a floating lower gate, a drain region and a source region that are in direct contact with the lower region of the multilayered gate, and stores information by storing charge in the lower gate. an insulator having an element and a gate having a single-layer structure, and an offset region having a lower impurity concentration than the drain and source regions and having the same conductivity type as the drain and source regions between the drain and source regions and the lower gate region; A semiconductor device characterized in that a gate type transistor is provided on the same semiconductor substrate. (2) After forming a first gate insulating film on the first and second element formation regions of one conductivity type formed by defining and exposing the semiconductor substrate by an insulating film, the first gate insulating film is 1
a covering body selectively covering the entire surface of the element forming region;
a step of simultaneously forming a first gate electrode that selectively covers and traverses the element formation region; and a step of selectively forming an offset region in the second element formation region using the first gate electrode as a mask. forming an insulating film on the entire surface of the substrate, etching the entire surface of the insulating film by an anisotropic dry etching means, and etching the covering body and the first gate; a step of selectively leaving the insulating film in the form of a sidewall on the side surface of the electrode; and after forming a second gate insulating film on at least the surface of the covering, forming a second conductive film on the covering. forming a second gate electrode, and patterning the coating in alignment with the second gate electrode to form a floating third gate electrode under the second gate electrode. , a second opposite conductivity type impurity for forming drain and source regions is selectively introduced into the first element forming region using the second and third gate electrodes as masks, and at the same time, forming the second element. a first region including the sidewall-like insulating film;
A method for manufacturing a semiconductor device, comprising the step of selectively introducing the gate electrode using the gate electrode as a mask.