JPH01248628A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01248628A JPH01248628A JP7941688A JP7941688A JPH01248628A JP H01248628 A JPH01248628 A JP H01248628A JP 7941688 A JP7941688 A JP 7941688A JP 7941688 A JP7941688 A JP 7941688A JP H01248628 A JPH01248628 A JP H01248628A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- hole
- chip
- insulating substrate
- element mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 19
- 239000003795 chemical substances by application Substances 0.000 abstract description 7
- 239000003822 epoxy resin Substances 0.000 abstract description 5
- 229920000647 polyepoxide Polymers 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
従来の半導体装置は、第２図に示すように、裏面に金属
層３を設けた絶縁基板１の上に半導体チップ４をマウン
ト剤５を使用して搭載し、半導体チップ４を外装樹脂体
６で被覆していた。As shown in FIG. 2, in a conventional semiconductor device, a semiconductor chip 4 is mounted on an insulating substrate 1 having a metal layer 3 on the back surface using a mounting agent 5, and the semiconductor chip 4 is mounted on an exterior resin body 6. It was covered with.
上述した従来の半導体装置は、例えばガラス繊維をエポ
キシ系樹脂で固めた熱伝導率の悪い絶縁基板上に半導体
チップを搭載しているため、パッケージの熱抵抗が大き
く、放熱が悪いため高出力の半導体チップを搭載するこ
とが出来ないという問題点があった。In the conventional semiconductor devices mentioned above, the semiconductor chip is mounted on an insulating substrate with poor thermal conductivity, such as glass fiber hardened with epoxy resin, so the thermal resistance of the package is high and heat dissipation is poor, making it difficult to achieve high output. There was a problem in that it was not possible to mount a semiconductor chip.
本発明の半導体装置は、絶縁基板と、前記絶縁基板上に
設けた素子載置部と、前記素子載置部の前記絶縁基板に
設けた貫通孔と、前記絶縁基板の裏面に設けた金属層と
、前記素子載置部の前記貫通孔をふさぐようにマウント
した半導体チップとを備えている。The semiconductor device of the present invention includes an insulating substrate, an element mounting section provided on the insulating substrate, a through hole provided in the insulating substrate of the element mounting section, and a metal layer provided on the back surface of the insulating substrate. and a semiconductor chip mounted so as to close the through hole of the element mounting section.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を説明するための断面図
である。図に示すように、絶縁基板１に設けた素子載置
部の絶縁基板１に貫通孔２を設け、絶縁基板１の裏面に
銅等の熱伝導の良い金属層３を設ける。次に、前記素子
載置部の貫通孔３をふさぐように半導体チップ４を載置
し、絶縁基板１より熱伝導率の高いエポキシ系樹脂等の
マウント剤５を用いて半導体チップ４をマウントし、半
導体チップ４をエポキシ系樹脂等の外装樹脂体６で被覆
する。FIG. 1 is a sectional view for explaining a first embodiment of the present invention. As shown in the figure, a through hole 2 is provided in an insulating substrate 1 of an element mounting portion provided on the insulating substrate 1, and a metal layer 3 having good thermal conductivity, such as copper, is provided on the back surface of the insulating substrate 1. Next, the semiconductor chip 4 is placed so as to close the through hole 3 of the element mounting part, and the semiconductor chip 4 is mounted using a mounting agent 5 such as an epoxy resin that has higher thermal conductivity than the insulating substrate 1. , the semiconductor chip 4 is covered with an exterior resin body 6 such as epoxy resin.
ここで、半導体チップ４より発生した熱は金属層３に伝
わり放熱する。Here, the heat generated by the semiconductor chip 4 is transmitted to the metal layer 3 and radiated.
第２図は本発明の第２の実施例を説明するための断面図
である。FIG. 2 is a sectional view for explaining a second embodiment of the present invention.
図に示すように、絶縁基板１の素子載置部に複数の貫通
孔２を設け、絶縁基板１の裏面及び表面の素子載置部に
金属層３を設けて、例えば金めつき等により金属３の表
面及び貫通孔２の内壁にめっき層７を形成する。次に、
前記素子載置部の貫通孔２をふさぐように半導体チップ
４を載置し、マウント剤５によりマウントする。次に、
半導体チップ４を含む表面を外装樹脂体６で被覆する。As shown in the figure, a plurality of through holes 2 are provided in the element mounting part of the insulating substrate 1, and a metal layer 3 is provided in the element mounting part on the back surface and the front surface of the insulating substrate 1. A plating layer 7 is formed on the surface of the through hole 3 and the inner wall of the through hole 2. next,
A semiconductor chip 4 is placed so as to close the through hole 2 of the element mounting portion, and mounted with a mounting agent 5. next,
The surface including the semiconductor chip 4 is covered with an exterior resin body 6.
この場合、寸法の大きな半導体チップを搭載しても絶縁
基板の強度を低下させることなく熱抵抗を下げることが
できる効果がある。In this case, even if a large-sized semiconductor chip is mounted, the thermal resistance can be reduced without reducing the strength of the insulating substrate.
以上説明したように本発明は、素子載置部に貫通孔を有
する絶縁基板に半導体チップを載置し、熱伝導率の高い
マウント剤によりマウントすることによりパッケージの
熱抵抗を下げて高出力の半導体チップを搭載した半導体
装置を実現できるという効果がある。As explained above, the present invention lowers the thermal resistance of the package by mounting a semiconductor chip on an insulating substrate having a through hole in the element mounting part and mounting it with a mounting agent having high thermal conductivity. This has the effect of realizing a semiconductor device equipped with a semiconductor chip.
第１図及び第２図は本発明の第１及び第２の実施例を説
明するための断面図、第３図は従来の半導体装置を説明
するための断面図である。
１・・・絶縁基板、２・・・貫通孔、３・・・金属層、
４・・・半導体チップ、５・・・マウント剤、６・・・
外装樹脂体、７・・・めっき層。1 and 2 are cross-sectional views for explaining first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view for explaining a conventional semiconductor device. 1... Insulating substrate, 2... Through hole, 3... Metal layer,
4... Semiconductor chip, 5... Mounting agent, 6...
Exterior resin body, 7... plating layer.
Claims (1)
前記素子載置部の前記絶縁基板に設けた貫通孔と、前記
絶縁基板の裏面に設けた金属層と、前記素子載置部の前
記貫通孔をふさぐようにマウントした半導体チップとを
備えたことを特徴とする半導体装置。an insulating substrate; an element mounting section provided on the insulating substrate;
A through hole provided in the insulating substrate of the element mounting section, a metal layer provided on the back surface of the insulating substrate, and a semiconductor chip mounted so as to close the through hole of the element mounting section. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7941688A JPH01248628A (en) | 1988-03-30 | 1988-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7941688A JPH01248628A (en) | 1988-03-30 | 1988-03-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01248628A true JPH01248628A (en) | 1989-10-04 |
Family
ID=13689266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7941688A Pending JPH01248628A (en) | 1988-03-30 | 1988-03-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01248628A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08167678A (en) * | 1994-12-09 | 1996-06-25 | Sony Corp | Semiconductor device |
-
1988
- 1988-03-30 JP JP7941688A patent/JPH01248628A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08167678A (en) * | 1994-12-09 | 1996-06-25 | Sony Corp | Semiconductor device |
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