JPH01245509A - Formation of semiconductor crystal layer - Google Patents

Formation of semiconductor crystal layer

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Publication number
JPH01245509A
JPH01245509A JP7184788A JP7184788A JPH01245509A JP H01245509 A JPH01245509 A JP H01245509A JP 7184788 A JP7184788 A JP 7184788A JP 7184788 A JP7184788 A JP 7184788A JP H01245509 A JPH01245509 A JP H01245509A
Authority
JP
Japan
Prior art keywords
silicon
film
seed
region
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7184788A
Other languages
Japanese (ja)
Inventor
Iwao Higashinakagaha
東中川 巌
Ichiro Mizushima
一郎 水島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7184788A priority Critical patent/JPH01245509A/en
Publication of JPH01245509A publication Critical patent/JPH01245509A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make it possible to single-crystallize a region wider than the region obtained by heating a substrate entirely at the same temperature by a method wherein, after an insulating film has been formed on a semiconductor substrate, an aperture is provided on the insulating film, and after an amorphous silicon layer has been formed on the whole surface, the layer is heated up for a short period from the opposite side. CONSTITUTION:A silicon oxide film 12 is formed on a silicon substrate 11, and the film 12 is removed in the stripe form of 2mum wide. A polycrystalline silicon film 14 is formed on the whole surface in such a manner that the exposed silicon surface will not be oxidized. Subsequently, the polycrystalline silicon film 14 is brought into an amorphous state by ion-implanting silicon. By heating from the rear side of a sample for one minute, for example, the single crystal region is extended by 15mum toward both sides of a seed 13.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、絶縁膜上の半導体単結晶層の形成方法に係り
、特に固相成長によって良好な半導体単結晶層を形成す
る方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming a semiconductor single crystal layer on an insulating film, and particularly to a method for forming a good semiconductor single crystal layer by solid phase growth. Regarding how to.

(従来の技術) 半導体メモリの微細化及び高速化してくるに従って、半
導体基板上のみでなくその上に絶縁膜を介した半導体単
結晶層(SOI)を形成してそこに能動素子を形成する
ことが必要になってきている。
(Prior art) As semiconductor memories become smaller and faster, active elements are formed not only on a semiconductor substrate but also on the semiconductor single crystal layer (SOI) with an insulating film interposed therebetween. is becoming necessary.

絶縁膜上に半導体単結晶を形成する方法としては、電子
ビームアニール、レーザアニールによって代表される溶
融固化の過程で単結晶を得る方法と絶縁膜に開口(シー
ド)を持たせた所に非晶質半導体膜を形成して、又は、
多結晶シリコンを形成した後イオン注入等によって、非
晶質化して、500〜600℃で、長時間加熱すること
によって、シードより順次結晶化させることによって、
単結晶層を得るものである。溶融法は、絶縁膜を介して
いるもののシリコン層が一時的に溶融するため下地基板
も相当温度が上り、下層デバイスの微細化に問題がある
。一方固相成長法は加熱時間は長いが。
There are two ways to form a semiconductor single crystal on an insulating film: one is to obtain a single crystal through the process of melting and solidification, which is represented by electron beam annealing and laser annealing, and the other is to form an amorphous crystal in a place where an opening (seed) is provided in the insulating film. forming a quality semiconductor film, or
After forming polycrystalline silicon, it is made amorphous by ion implantation, etc., and then heated at 500 to 600°C for a long time to sequentially crystallize it from the seed.
A single crystal layer is obtained. In the melting method, the silicon layer is temporarily melted even though an insulating film is interposed therebetween, so the temperature of the underlying substrate also rises considerably, which poses a problem in miniaturization of the underlying device. On the other hand, solid phase growth requires a long heating time.

温度が低いため上記の問題は発生しない。この方法は、
結晶粒に接した所に非晶質中に結晶粒が出来ることより
も、エネルギー的に容易であることによって達成されて
いる。前述の説明で明らかな様に、この半導体基板は、
全体は同一温度に保たれているため、長時間の熱処理に
よって非晶質中にも、微結晶粒が発生する。この微結晶
粒が発生すると、ここにシードよりの結晶粒が伸びてき
ても、もはやこの領域をとりこんで、単結晶領域を、増
すことは、不可能であり、ここが単結晶領域の限界とな
る。現在はこの領域が数ミクロンであるためデバイスへ
の実用化のネックになっている。
The above problem does not occur because the temperature is low. This method is
This is achieved because it is easier in terms of energy than forming crystal grains in amorphous material in contact with crystal grains. As is clear from the above explanation, this semiconductor substrate is
Since the entire structure is kept at the same temperature, microcrystalline grains are generated even in the amorphous state by long-term heat treatment. Once these microcrystalline grains are generated, even if crystal grains from the seed grow here, it is no longer possible to incorporate this region and increase the single crystal region, and this is the limit of the single crystal region. Become. Currently, this region is several microns in size, which is a bottleneck in practical application to devices.

(発明が解決しようとする課題) 本発明は、同相成長法によって半導体単結晶層を得るに
あたって、現在の単結晶領域よりも更に広い領域を単結
晶化する方法を提供し、固相成長による絶縁膜上の半導
体単結晶膜上のデバイスを実用化を図ることを目的とす
るものである。
(Problems to be Solved by the Invention) The present invention provides a method for single-crystalizing a wider area than the current single-crystal region when obtaining a semiconductor single-crystal layer by an in-phase growth method, and provides an insulating layer by solid-phase growth. The purpose is to put devices on semiconductor single crystal films into practical use.

半導体基板に絶縁膜を形成したのち、該絶縁膜に開口を
設けたのち、全面に非晶質シリコン層を形成したのち、
該非晶質シリコンの存在する反対側より短時間又は短時
間のくり返しで、加熱する。
After forming an insulating film on a semiconductor substrate, forming an opening in the insulating film, and forming an amorphous silicon layer on the entire surface,
Heating is performed from the opposite side where the amorphous silicon is present for a short time or repeatedly for a short time.

(作 用) 第1図に本発明の詳細な説明するための概略図を示す。(for production) FIG. 1 shows a schematic diagram for explaining the present invention in detail.

ここで(11)は、半導体基板、(12)は絶縁膜、(
13)は、絶縁膜中に設けられた開口(シード)であっ
て、成長すべき単結晶膜は、ここより下地半導体結晶の
方位を受取る。(15)は、加熱源であるが、加熱時間
を正確に制御するために、熱容量の小さいハロゲンラン
プ加熱法のようなものを用いるのが好ましい。
Here (11) is a semiconductor substrate, (12) is an insulating film, (
13) is an opening (seed) provided in the insulating film, from which the single crystal film to be grown receives the orientation of the underlying semiconductor crystal. Although (15) is a heating source, in order to accurately control the heating time, it is preferable to use a heating method such as a halogen lamp with a small heat capacity.

半導体層及び基板半導体として、それぞれ非晶質シリコ
ン及びシリコンを、仮定すると、常温では、シリコンの
方がシリコン酸化膜に比べて、約1000倍位、熱伝導
率は良い。温度が上ると、シリコンの熱伝導率は下り、
シリコン酸化膜の熱伝導率は上るが、それでも750℃
で約100倍の違いがある。
Assuming that amorphous silicon and silicon are used as the semiconductor layer and substrate semiconductor, respectively, silicon has a thermal conductivity about 1000 times better than a silicon oxide film at room temperature. As the temperature rises, the thermal conductivity of silicon decreases,
Although the thermal conductivity of silicon oxide film increases, it still reaches 750℃.
There is a difference of about 100 times.

従って第1図(a)のような、構成で加熱を行うと、上
層の非晶質シリコンへの熱伝達は、主として、シリコン
基板と非晶質シリコンの接触部(シード)を通じて行わ
れるため、ある−時期の温度分布は、第1図(b)の様
になる。同図に示した温度の数値は、温度の高低を、理
解しやすくするためにいれたものである。例えば、同相
成長が、700℃でドミナントに起るとすれば、700
℃の等温線までが、単結晶化している。時間の経過に従
って、700℃の等温線はより先へと進んでいく。
Therefore, when heating is performed with the configuration shown in FIG. 1(a), heat transfer to the upper layer of amorphous silicon is mainly performed through the contact area (seed) between the silicon substrate and the amorphous silicon. The temperature distribution at a certain time is as shown in FIG. 1(b). The temperature values shown in the figure are included to make it easier to understand the high and low temperatures. For example, if in-phase growth occurs dominantly at 700°C, then
The area up to the °C isotherm is single crystallized. As time progresses, the 700°C isotherm moves further along.

700℃以下の所は、結晶化しないので、このように温
度勾配をつけることにより、全体を同じ温度で加熱する
よりも広い領域を単結晶化する事が可能になる。
Since crystallization does not occur at temperatures below 700° C., by creating a temperature gradient in this way, it is possible to single-crystallize a wider area than by heating the entire area at the same temperature.

このように非晶質シリコンへの熱の伝わり方が上のよう
な理由で、原則的にはシードを経過して行われる。とこ
ろが、シリコン膜厚が、たかだかlkmであるので、シ
ードよりはなれた部分では熱抵抗としては大きい。シー
ドから十分前れた所ではシードからの熱よりも熱伝導度
の悪いシリコン酸化膜を通しての熱が多くなる場合が出
来る。このような場合は非晶質シリコン部での温度勾配
がなくなり多数の結晶粒が無秩序に発生するようになり
、もはや、単結晶にならなくなる。本発明では、この問
題を軽減する方法もいくつが考えられ、実施例の中でい
くつかにふれる予定である。
Because of the above-mentioned reasons for how heat is transmitted to amorphous silicon, it is, in principle, conducted through the seed. However, since the silicon film thickness is at most 1km, the thermal resistance is large in the portions away from the seed. At a location far enough in front of the seed, more heat may be transmitted through the silicon oxide film, which has poor thermal conductivity, than from the seed. In such a case, the temperature gradient in the amorphous silicon portion disappears, and a large number of crystal grains are generated in a disordered manner, and the crystal grains no longer form a single crystal. In the present invention, a number of methods can be considered to alleviate this problem, and some of them will be mentioned in the embodiments.

(実施例) 実施例1 本発明の一実施例を第1図(a)を用いて説明する。シ
リコン基板(11)上に0.5趨のシリコン酸化膜(1
2)を形成し、2趣幅にストライプ状に除去する。続い
て、露出しているシリコン面を酸化しない様に、全面に
多結晶シリコン膜(14)を減圧CVD法で0.5−形
成する。続いて、全面にシリコンを5O−380KV’
t’ 10” 〜101G/adイオン注入すルコとに
よって前記多結晶シリコン膜(14)を非晶質化する。
(Example) Example 1 An example of the present invention will be described using FIG. 1(a). A 0.5-thick silicon oxide film (1) is deposited on a silicon substrate (11).
2) is formed and removed in stripes with two widths. Subsequently, a polycrystalline silicon film (14) is formed on the entire surface by low pressure CVD so as not to oxidize the exposed silicon surface. Next, apply silicon to the entire surface at 5O-380KV'.
The polycrystalline silicon film (14) is made amorphous by ion implantation from t'10'' to 101 G/ad.

続いて、同図(a)に示す様な構成で、試料の裏面から
例えば1分間加熱する。しかる後、選択エッチにより、
単結晶領域を確認した所、単結晶領域はシード(13)
の両側にそれぞれ15μs延びていた。
Subsequently, the sample is heated from the back side for, for example, 1 minute using a configuration as shown in FIG. 4(a). After that, by selective sex,
After checking the single crystal region, the single crystal region is a seed (13)
They each extended for 15 μs on each side.

ここで、絶縁膜を通してとシードを通しての熱抵抗を考
慮すると、絶縁膜の厚さ及び、その」二のシリコン膜厚
は厚い方が熱抵抗の差が大きくなるので、上記実施例に
おいて、シリコン酸化膜膜厚及びシリコン膜厚を、それ
ぞれt、o 、mにとった。
Considering the thermal resistance through the insulating film and through the seed, the thicker the insulating film and the silicon film, the larger the difference in thermal resistance. The film thickness and silicon film thickness were set to t, o, and m, respectively.

これによればシードを通してのシリコンを経過する時の
熱抵抗は、半分になり、逆に、シリコン酸化膜を通して
の熱抵抗は倍になり、温度勾配はシードより更に遠くま
で保たれる。その結果、この方法での単結晶領域は、上
記実施例1よりも更に延びて50趣以上であることがわ
かった。
According to this, the thermal resistance when passing through the silicon through the seed is halved, and conversely, the thermal resistance through the silicon oxide film is doubled, and the temperature gradient is maintained further away from the seed. As a result, it was found that the single crystal region in this method was further extended than in Example 1, and was 50 crystals or more.

第2図は、シード領域付近の多結晶シリコン領域の平面
図を示したものである。第2図(a)は、実施例1で述
べたのと同様の形態で多結晶シリコンが全面についてい
る場合の平面図である。ある一定のシードを通して、熱
が伝わってくるので。
FIG. 2 shows a plan view of the polycrystalline silicon region near the seed region. FIG. 2(a) is a plan view of a case where polycrystalline silicon is coated on the entire surface in a form similar to that described in Example 1. Because heat is transmitted through certain seeds.

必要な領域のみ熱を与えることが効率的である。It is efficient to apply heat only to the necessary areas.

従って、デバイス領域の形態によって、不必要な部分の
多結晶シリコンを前爪てエツチングにより除いておくの
がのぞましい。例えば第2図(b)のようにシードの幅
方向に熱が伝達しないようにシードの幅に多結晶シリコ
ン膜を残してそれ以外をエツチングしたものである。あ
るいは、第2図(c)や第2図(d)に示すように多結
晶領域のうち。
Therefore, depending on the form of the device region, it is preferable to remove unnecessary portions of the polycrystalline silicon by etching. For example, as shown in FIG. 2(b), a polycrystalline silicon film is left in the width of the seed and the rest is etched to prevent heat from being transferred in the width direction of the seed. Or in a polycrystalline region as shown in FIG. 2(c) and FIG. 2(d).

シードから結晶領域になる領域の多結晶シリコンを残す
ことにより、単結晶領域になる見込のない多結晶領域に
、熱を与える事を避け、所望の多結晶領域を確実に単結
晶化することができる。
By leaving the polycrystalline silicon in the region that will become the crystalline region from the seed, it is possible to avoid applying heat to the polycrystalline region that is unlikely to become a single crystalline region, and to ensure that the desired polycrystalline region becomes single crystallized. can.

またこれまでの議論から明らかな様に、通常の基板の上
方から加熱する電子ビームアニールの時のシードの場合
とは逆で、シード領域は、熱抵抗の観点から、広い方が
好ましい。
Further, as is clear from the discussion so far, it is preferable that the seed region be wide from the viewpoint of thermal resistance, contrary to the case of a seed in electron beam annealing in which the substrate is heated from above.

さらに、加熱方法についても以下述べるようにするのが
望しい。つまり基板を裏面から加熱した時に有効な熱は
シードを通しての熱である。しかしながら、シードから
離れた領域では第1図(、)の熱酸化膜(12)を通し
ての熱が優先し、不規則な、結晶核が発生し、これが単
結晶領域形成の阻害要因となる。従って、ウェハーを上
面より、加熱することを補助加熱として、前記結晶核発
生のおそれのないように、例えば500℃に予備加熱し
ておき、その熱を考慮してシードを経過しての熱すなわ
ち、ビームの照射量を設定し、単結晶化を行なうとよい
。これは、熱輻射等によって表面より熱。
Furthermore, it is desirable that the heating method is also described below. In other words, when the substrate is heated from the back side, the effective heat is the heat that passes through the seeds. However, in a region away from the seed, heat through the thermal oxide film (12) shown in FIG. Therefore, heating the wafer from the top surface is used as auxiliary heating to prevent the generation of crystal nuclei, for example, by preheating the wafer to 500°C. It is preferable to set the beam irradiation amount and carry out single crystallization. This is due to heat radiation from the surface.

が逃げる影響を低減するためにも望しい。It is also desirable to reduce the effects of escaping.

また、ここで500℃の予備加熱を行うと、熱伝導率の
比は1 : 200位になる。一方、常温ではその比が
約1 : 1000なのでシリコン酸化膜は出来るだけ
、低い温度に保つ事が有利である。
Further, if preheating is performed at 500° C., the thermal conductivity ratio will be about 1:200. On the other hand, since the ratio is about 1:1000 at room temperature, it is advantageous to keep the silicon oxide film at as low a temperature as possible.

従って上面からの予備加熱も裏面からの加熱と連動して
、出来る限り酸化膜温度は上げない様に。
Therefore, preheating from the top surface is linked to heating from the back surface, and the oxide film temperature should be kept as low as possible.

すなわち必要であればパルス的な加熱をする事がのぞま
しい。
In other words, it is desirable to perform pulse heating if necessary.

〔発明の効果〕〔Effect of the invention〕

本発明によれば温度勾配をつけた状態で絶縁膜上の半導
体層の固相成長を、行うことにより、結晶成長の阻害要
因である核発生を抑えて、良質の大面積単結晶層を得る
事が可能となる。
According to the present invention, by performing solid-phase growth of a semiconductor layer on an insulating film with a temperature gradient, nucleation, which is a factor inhibiting crystal growth, is suppressed and a high-quality, large-area single crystal layer is obtained. things become possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を説明するための断面図、
第2図は、本発明の一実施例を説明するための断面図で
ある。 11・・・半導体基板、   12・・・絶縁膜。 13・・シード部、    14・・・非晶質シリコン
膜、21・・・シード、22・・・非晶質シリコン。 代理人 弁理士 則 近 憲 佑 同  松山光之
FIG. 1 is a sectional view for explaining one embodiment of the present invention,
FIG. 2 is a sectional view for explaining one embodiment of the present invention. 11... Semiconductor substrate, 12... Insulating film. 13...Seed portion, 14...Amorphous silicon film, 21...Seed, 22...Amorphous silicon. Agent Patent Attorney Noriyuki Chika Yudo Mitsuyuki Matsuyama

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に部分的に前記基板の一部を露出する開
孔部を持つ、絶縁膜を形成し、次に、全面に非晶質半導
体層を形成したのち、熱処理を行うことにより前記開孔
部から前記非晶質半導体層を単結晶化する半導体結晶層
の形成方法において前記熱処理を基板上に形成された非
晶質半導体層表面と反対の基板面から行うことを特徴と
する半導体結晶層の形成方法。
An insulating film having an opening that partially exposes a part of the substrate is formed on a semiconductor substrate, and then an amorphous semiconductor layer is formed on the entire surface, and then heat treatment is performed to close the opening. A method for forming a semiconductor crystal layer in which the amorphous semiconductor layer is single-crystallized from a portion thereof, wherein the heat treatment is performed from a surface of the substrate opposite to a surface of the amorphous semiconductor layer formed on the substrate. How to form.
JP7184788A 1988-03-28 1988-03-28 Formation of semiconductor crystal layer Pending JPH01245509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7184788A JPH01245509A (en) 1988-03-28 1988-03-28 Formation of semiconductor crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7184788A JPH01245509A (en) 1988-03-28 1988-03-28 Formation of semiconductor crystal layer

Publications (1)

Publication Number Publication Date
JPH01245509A true JPH01245509A (en) 1989-09-29

Family

ID=13472342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7184788A Pending JPH01245509A (en) 1988-03-28 1988-03-28 Formation of semiconductor crystal layer

Country Status (1)

Country Link
JP (1) JPH01245509A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5318661A (en) * 1990-08-08 1994-06-07 Canon Kabushiki Kaisha Process for growing crystalline thin film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5318661A (en) * 1990-08-08 1994-06-07 Canon Kabushiki Kaisha Process for growing crystalline thin film

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