JPS6236381B2 - - Google Patents
Info
- Publication number
- JPS6236381B2 JPS6236381B2 JP57047354A JP4735482A JPS6236381B2 JP S6236381 B2 JPS6236381 B2 JP S6236381B2 JP 57047354 A JP57047354 A JP 57047354A JP 4735482 A JP4735482 A JP 4735482A JP S6236381 B2 JPS6236381 B2 JP S6236381B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- thin film
- semiconductor
- white light
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 95
- 239000013078 crystal Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 13
- 238000009826 distribution Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に絶
縁基板上に層設された非晶質或いは多結晶半導体
を大出力白色光等で照射加熱して単結晶化させる
技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for heating an amorphous or polycrystalline semiconductor layered on an insulating substrate by irradiating and heating it with high-output white light or the like to convert it into a single crystal. It is something.
絶縁性基板上に半導体単結晶層を形成する方法
に関して、最近注目されている技術に、絶縁性基
板上に堆積した非晶質或いは多結晶シリコンにレ
ーザ光を照射して加熱し、単結晶シリコンを作製
する方法がある。即ち、グラフオエピタキシー、
ブリツジングエピタキシー、島状構造エピタキシ
ー等の方法がそれである。しかし未だ実用に耐え
るのは完成されていないのが実情であり、またレ
ーザ光加熱による単結晶化法は微小径のレーザ光
線束の走査を用いているので大面積のウエハー状
シリコン単結晶を短時間で得るのは困難であり生
産性の向上を図り難いという欠点がある。また極
く最近になつて、カーボンストリツプヒーターで
絶縁性基板上の非晶質或いは多結晶シリコンを高
温に加熱しながら、ヒーターを高速度で走査する
ことによつて単結晶シリコンを得る方法が報告さ
れているが、該方法は生産性の向上は図り易いが
絶縁性基板を1300℃以上の高温に昇温した上で遂
行されなければならないので、将来の多層積層三
次元回路素子の形成技術としては用い難い。 Regarding the method of forming a semiconductor single-crystal layer on an insulating substrate, a technique that has recently been attracting attention is a method in which amorphous or polycrystalline silicon deposited on an insulating substrate is irradiated with laser light to heat it, and the single-crystal silicon layer is heated. There is a method to create . That is, graphoepitaxy,
Examples include methods such as bridging epitaxy and island structure epitaxy. However, the reality is that it has not yet been perfected for practical use, and the single crystallization method using laser heating uses scanning with a laser beam bundle of minute diameter, so it is possible to shorten a large area of wafer-shaped silicon single crystal. It has the disadvantage that it is difficult to obtain in time and it is difficult to improve productivity. Also, very recently, a method has been developed to obtain single crystal silicon by scanning the heater at high speed while heating amorphous or polycrystalline silicon on an insulating substrate to a high temperature with a carbon strip heater. has been reported, but although this method can easily improve productivity, it must be carried out after heating the insulating substrate to a high temperature of 1300°C or higher, making it difficult to form future multilayer laminated three-dimensional circuit elements. It is difficult to use as a technology.
本発明は、絶縁性基板上に半導体素子が形成さ
れた構造の半導体装置の製造技術に於ける将来の
重要性と、不満足な現状に鑑み、新規な技術手段
を駆使することにより、実用的価値を飛躍的に向
上せしめた半導体装置の製造方法を提供すること
を目的とするものである。 In view of the future importance of manufacturing technology for semiconductor devices having a structure in which semiconductor elements are formed on an insulating substrate and the unsatisfactory current state of the art, the present invention has been developed by making full use of new technical means to achieve practical value. The object of the present invention is to provide a method for manufacturing a semiconductor device that dramatically improves the performance of semiconductor devices.
一般に非晶質半導体或いは結晶粒子の微細な多
結晶半導体等は、単結晶半導体に比較すると可視
光線に対する光吸収係数が大きく、それにより良
好な加熱、アニールが可能であることから、その
特性を利用して非晶質或いは多結晶半導体層の単
結晶化を行なうことができ、従つて従来得られな
かつた半導体装置の製造も可能になると考えられ
る。 In general, amorphous semiconductors or polycrystalline semiconductors with fine crystal grains have a larger light absorption coefficient for visible light than single crystal semiconductors, and this allows for better heating and annealing, so these characteristics can be utilized. It is believed that this makes it possible to single-crystallize an amorphous or polycrystalline semiconductor layer, thereby making it possible to manufacture semiconductor devices that could not be obtained conventionally.
そこで、可視光線として大出力の白色光を用い
た場合を考える。 Therefore, consider a case where high-output white light is used as visible light.
非晶質或い多結晶半導体層を大出力の白色光で
照射して該半導体層を高温に加熱し、単結晶化せ
しめようとする場合に、大出力の白色光を照射光
としていることから半導体層中における結晶核の
発生とその結晶成長の過程において最も重要な温
度分布の制御が困難である。そのために多数の結
晶核が半導体層中に発生し、又結晶成長が多数個
所で生じ、結果的には結晶粒子がわずかに増大し
たに過ぎない多結晶層しか得られず、大型の単結
晶半導体層を得ることは困難である。 When attempting to irradiate an amorphous or polycrystalline semiconductor layer with high-output white light to heat the semiconductor layer to a high temperature and make it into a single crystal, this is because high-output white light is used as the irradiation light. It is difficult to control the temperature distribution, which is the most important factor in the process of crystal nucleus generation and crystal growth in a semiconductor layer. As a result, many crystal nuclei are generated in the semiconductor layer, and crystal growth occurs at many locations, resulting in a polycrystalline layer with only a slight increase in crystal grains, resulting in a large single-crystal semiconductor. It is difficult to obtain layers.
ところで絶縁性基板上に非晶質或いは多結晶半
導体層を半導体層より熱伝導率の小なる絶縁性薄
膜を挾んで二層対置させて堆積し、下層の半導体
層が一部分パターン加工により除去されている構
造の場合に大出力の白色光を照射し加熱すると、
白色光が入射する側の上層の半導体層は光吸収係
数が大なるために白色光は大部分上層の半導体層
に吸収され上層の半導体層はすみやかに高温度に
上昇する。しかし上層半導体層の下部に絶縁性薄
膜を挾んで上層半導体層と類似の半導体層が存在
する場所○イは、上層半導体層の下部に絶縁性薄膜
しか存在しない場所○ロより熱伝導率が大なるため
に、上層半導体層の到達達上昇温度は場所○ロが場
所○イよりも高くなる。 By the way, an amorphous or polycrystalline semiconductor layer is deposited on an insulating substrate in two opposing layers with an insulating thin film having a lower thermal conductivity than the semiconductor layer sandwiched in between, and a portion of the lower semiconductor layer is removed by pattern processing. If the structure is irradiated with high-output white light and heated,
Since the upper semiconductor layer on the side where white light is incident has a large light absorption coefficient, most of the white light is absorbed by the upper semiconductor layer, and the temperature of the upper semiconductor layer quickly rises to a high temperature. However, the thermal conductivity of the location (○) where there is a semiconductor layer similar to the upper semiconductor layer with an insulating thin film sandwiched between the upper semiconductor layers is higher than that of the location (○) where there is only an insulating thin film under the upper semiconductor layer. Therefore, the temperature rise reached by the upper semiconductor layer is higher at location ○B than at location ○B.
このような現象から絶縁基板上に非晶質或いは
多結晶半導体層と絶縁性薄膜の積層を工夫して形
成すれば、強力な白色光の平面的な一括照射によ
る加熱処理においても、単結晶化したい半導体層
内に単結晶化に最適な温度分布を形成することが
できる。 Because of this phenomenon, if a laminated layer of an amorphous or polycrystalline semiconductor layer and an insulating thin film is formed on an insulating substrate, it will be possible to form a single crystal even in heat treatment using strong white light beam irradiation. It is possible to form an optimal temperature distribution for single crystallization in a desired semiconductor layer.
本発明は上記特性を利用するところにあり、非
晶質或いは多結晶半導体層を強力な白色光照射に
よる加熱により単結晶化する場合、単結晶化領域
に結晶成長に最適な温度分布を形成して、半導体
層内における結晶核の発生個所を制御し、更にそ
の結晶核が優先的に結晶成長する方向をも制御
し、固相結晶成長機構にもとづく大面積の単結晶
半導体膜の形成を可能とすることを基本とする。 The present invention utilizes the above characteristics, and when an amorphous or polycrystalline semiconductor layer is made into a single crystal by heating with intense white light irradiation, an optimum temperature distribution for crystal growth is formed in the single crystallized region. This enables the formation of large-area single-crystal semiconductor films based on the solid-phase crystal growth mechanism by controlling the location where crystal nuclei are generated within the semiconductor layer and also controlling the direction in which the crystal nuclei preferentially grow. The basic principle is that
以下本発明を実施例に従つて図面を参照しなが
ら詳説する。 Hereinafter, the present invention will be explained in detail according to embodiments with reference to the drawings.
第１図ａ乃至ｊは本発明の１実施例を説明する
半導体装置の製造工程断面図であり、以下工程順
に説明する。 FIGS. 1a to 1j are cross-sectional views showing the manufacturing process of a semiconductor device, which explains one embodiment of the present invention, and will be explained in the order of the steps below.
第１図ａ：いま、絶縁性基板１０として、石
英、シリコン単結晶の熱酸化シリコン、あるいは
適当な金属表面を絶縁物で覆つた基板等を用い、
その表面に非晶質或いは多結晶のシリコン半導体
層１１を蒸着法、CVD法或いはスパツタリング
法等によつて0.1〜１μｍ程度の厚さに被着堆積
する。 FIG. 1a: Now, as the insulating substrate 10, quartz, thermally oxidized silicon of silicon single crystal, or a substrate with an appropriate metal surface covered with an insulating material, etc. are used.
An amorphous or polycrystalline silicon semiconductor layer 11 is deposited on the surface to a thickness of about 0.1 to 1 μm by vapor deposition, CVD, sputtering, or the like.
第１図ｂ：次に、非晶質或いは多結晶シリコン
半導体層１１をフオト・リングラフイ法により蝕
刻し、部分的に上記半導体層１１ａを残存させ
る。場合によつては上記半導体層１１を部分的に
プラズマ陽極酸化して部分的に上記半導体層１１
ａを残存させることもできる。蝕刻後の上記半導
体層１１ａの平面形状の１例を第２図ａに示す。
半導体層１１ａは領域の中央部が除去された枠状
に蝕刻されている。 FIG. 1b: Next, the amorphous or polycrystalline silicon semiconductor layer 11 is etched by photolithography, leaving the semiconductor layer 11a partially. In some cases, the semiconductor layer 11 may be partially plasma anodized to partially form the semiconductor layer 11.
It is also possible to leave a. An example of the planar shape of the semiconductor layer 11a after etching is shown in FIG. 2a.
The semiconductor layer 11a is etched into a frame shape with the center portion of the region removed.
第１図ｃ：次に半導体層１１ａが残存した基板
１０上に、プラズマCVD法或いはスパツタリン
グ法等を用いて二酸化シリコン層等の絶縁性薄膜
１２を0.01〜１μｍ程度の厚さに形成する。絶縁
性薄膜１２の表面凹凸が大きい場合は、第１図ｄ
に示す如くドライエツチング法等を用いて絶縁性
薄膜１２の表面を平坦化する。 FIG. 1c: Next, on the substrate 10 on which the semiconductor layer 11a remains, an insulating thin film 12 such as a silicon dioxide layer is formed to a thickness of about 0.01 to 1 μm using a plasma CVD method or a sputtering method. If the surface unevenness of the insulating thin film 12 is large,
As shown in FIG. 2, the surface of the insulating thin film 12 is planarized using a dry etching method or the like.
第１図ｅ：ほぼ平坦な絶縁性薄膜１２上に次に
非晶質或いは多結晶シリコン半導体層１３を蒸着
法、CVD法或いはスパツタリング法等によつて
0.5〜５μｍ程度の厚さに被着堆積する。 FIG. 1e: Next, an amorphous or polycrystalline silicon semiconductor layer 13 is formed on the almost flat insulating thin film 12 by vapor deposition, CVD, sputtering, etc.
It is deposited to a thickness of about 0.5 to 5 μm.
第１図ｆ：次に、上記非晶質或いは多結晶シリ
コン半導体層１３をフオト・リソグラフイ法によ
り蝕刻し、部分的に該半導体層１３ａを残存させ
る。その際図に示す如く上記半導体層１３ａの残
存層の外縁部が半導体層１１ａの残存層の外縁部
とほぼ一致するようにする。 FIG. 1f: Next, the amorphous or polycrystalline silicon semiconductor layer 13 is etched by photolithography, leaving the semiconductor layer 13a partially. At this time, as shown in the figure, the outer edge of the remaining layer of the semiconductor layer 13a is made to substantially coincide with the outer edge of the remaining layer of the semiconductor layer 11a.
第１図ｇ：次にプラズマCVD法或いはスパツ
タリング法等を用いて半導体層１３ａを被つて二
酸化シリコ層等の絶縁性薄膜１４を0.01〜１μｍ
程度の厚さに形成する。なお絶縁性薄膜１４は場
合によつては形成されなくても良い。 Figure 1g: Next, using a plasma CVD method or a sputtering method, the semiconductor layer 13a is covered with an insulating thin film 14 such as a silicon dioxide layer with a thickness of 0.01 to 1 μm.
Form to a certain thickness. Note that the insulating thin film 14 may not be formed depending on the case.
第１図ｈ：そして、上記絶縁性薄膜１４で被わ
れた基板に強力は白色光１５を照射して加熱し、
非晶質或いは多結晶シリコンからなる半導体層１
３ａを単結晶シリコン１６に交換する。白色光１
５の照射加熱初期においては、半導体層１３ａ内
の温度分布は、第１図ｉ中に破線で示すように基
板中央部の温度が周辺部よりも高い山型となる。
それは半導体層１３ａの中央部の下層部は熱伝導
率が小さな二酸化シリコンのみが存在するために
半導体層１３ａの中央部は白色光１５の照射加熱
により温度が上昇し易いが、半導体層１３ａの周
辺部の下層部には熱伝導率が二酸化シリコンより
約１桁大きな半導体層１１ａが存在するために半
導体層１３ａの周辺部は温度上昇しにくく、結果
的に前記温度分布が得られる。 FIG. 1h: Then, the substrate covered with the insulating thin film 14 is heated by irradiating it with intense white light 15.
Semiconductor layer 1 made of amorphous or polycrystalline silicon
3a is replaced with single crystal silicon 16. white light 1
At the initial stage of irradiation heating in step 5, the temperature distribution within the semiconductor layer 13a takes on a mountain shape in which the temperature at the center of the substrate is higher than at the periphery, as shown by the broken line in FIG. 1i.
This is because only silicon dioxide with low thermal conductivity exists in the lower layer of the central part of the semiconductor layer 13a, so the temperature in the central part of the semiconductor layer 13a tends to rise due to heating by irradiation with the white light 15, but the temperature around the semiconductor layer 13a increases. Since the semiconductor layer 11a whose thermal conductivity is about one order of magnitude higher than that of silicon dioxide exists in the lower layer of the semiconductor layer 13a, the temperature around the semiconductor layer 13a is difficult to rise, and as a result, the temperature distribution described above is obtained.
固相結晶成長機構では前記温度分布下では半導
体層１３ａの中央部に結晶核が発生する。白色光
の照射加熱中期においては結晶核が成長するとも
にその部分の光吸収係数が小さくなつて行くので
半導体層１３ａの中央部の温度は低下し始める。
そして結晶化が中央部から周辺部へ伸長していく
につれて周辺部も同様に温度が低下しようとする
が、白色光１５が半導体１１ａに強く吸収される
ようになり、半導体層１１ａが温度上昇していく
ため、半導体層１３ａの周辺部は中央部の温度よ
り高くなり半導体層１６は鞍型の温度分布（第１
図ｊ）を持つようになる。 In the solid phase crystal growth mechanism, crystal nuclei are generated in the center of the semiconductor layer 13a under the above temperature distribution. In the middle stage of white light irradiation and heating, crystal nuclei grow and the light absorption coefficient of that portion decreases, so the temperature at the center of the semiconductor layer 13a begins to decrease.
As the crystallization extends from the center to the periphery, the temperature of the periphery also tends to decrease, but the white light 15 is now strongly absorbed by the semiconductor 11a, causing the temperature of the semiconductor layer 11a to rise. As a result, the peripheral part of the semiconductor layer 13a becomes higher in temperature than the central part, and the semiconductor layer 16 has a saddle-shaped temperature distribution (first
Figure j).
なお半導体層１１ａは半導体層１３ａの単結晶
化前後において最高温度でも600℃以下であるた
め初期の膜質はほとんど変化しない。従つて半導
体層１１ａは非晶質或いは多結晶層として別の用
途に利用できる。 Note that since the maximum temperature of the semiconductor layer 11a is 600° C. or less before and after the single crystallization of the semiconductor layer 13a, the initial film quality hardly changes. Therefore, the semiconductor layer 11a can be used for other purposes as an amorphous or polycrystalline layer.
この温度分布変化によつて半導体層１３ａの中
央部から周辺部へと結晶成長が促進され、大型単
晶化が完了する。それとともに白色光１５の照射
が遮断される。光照射時間は数秒から数分間であ
る。 This change in temperature distribution promotes crystal growth from the center to the periphery of the semiconductor layer 13a, completing the formation of a large single crystal. At the same time, the irradiation of the white light 15 is blocked. The light irradiation time is from several seconds to several minutes.
なお単結晶化する半導体層１３ａが数mm角の比
較的広面積領域に達する場合には第２図ｂの平面
図に示す如く半導体層１１ａを適切な幅で適切な
個数の帯状乃至は矩形状に形成することが望まし
い。 In addition, when the semiconductor layer 13a to be made into a single crystal reaches a relatively wide area of several mm square, the semiconductor layer 11a is formed into an appropriate number of strips or rectangles with an appropriate width as shown in the plan view of FIG. 2b. It is desirable to form the
以上詳説した如く、本発明の白色光照射加熱下
で半導体層内に温度分布を形成する方法と、その
温度分布下で固相結晶成長機構による結晶核発生
を制御し、また結晶成長方向を制御する方法を採
用すれば、絶縁膜上に大型の単結晶半導体層を形
成することができる。しかも、1000℃以下での膜
形成が可能であるため、本発明の方法が基本的に
重要な役割を果す積層型デバイスを実現して行く
上で多大の効果を期待することができる。 As explained in detail above, the method of the present invention for forming a temperature distribution in a semiconductor layer under white light irradiation heating, controlling the generation of crystal nuclei by a solid phase crystal growth mechanism under the temperature distribution, and controlling the direction of crystal growth. By adopting this method, a large single crystal semiconductor layer can be formed on an insulating film. Moreover, since the film can be formed at a temperature of 1000° C. or lower, great effects can be expected in the realization of stacked devices in which the method of the present invention plays a fundamentally important role.
第１図ａ〜ｊは本発明の１実施例を説明する半
導体装置の製造工程断面図である。第２図ａ，ｂ
は本発明の１実施例を説明する半導体装置の製造
工程の平面図である。
１０……絶縁性基板、１１，１１ａ……半導体
層、１２……絶縁性薄膜、１３，１３ａ……半導
体層、１４……絶縁性薄膜、１５……白色光、１
６……単結晶シリコン。
FIGS. 1a to 1j are cross-sectional views showing the manufacturing process of a semiconductor device, illustrating one embodiment of the present invention. Figure 2 a, b
1 is a plan view of a manufacturing process of a semiconductor device explaining one embodiment of the present invention; FIG. 10... Insulating substrate, 11, 11a... Semiconductor layer, 12... Insulating thin film, 13, 13a... Semiconductor layer, 14... Insulating thin film, 15... White light, 1
6...Single crystal silicon.
Claims (1)
第１半導体層を堆積し、中心部分が取り除かれた
状態に該第１半導体層をパターン加工する工程
と、 上記中心部分が取り除かれた状態にパターン加
工された第１半導体層上及び絶縁性基板上を被覆
する第１絶縁性薄膜層を形成する工程と、 該第１絶縁性薄膜上に非晶質または多結晶から
なる第２半導体層を堆積し、該第２半導体層を上
記中心部分が取り除かれた状態にパターン加工さ
れた第１半導体層のパターン外縁と外縁がほぼ対
応するようにパターン加工して、第２半導体層が
上記中心部分が取り除かれた状態にパターン加工
された第１半導体層と重なるように形成する工程
と、 上記工程後の絶縁性基板上に白色光を照射して
加熱する工程と からなり、上記中心部分が取り除かれた状態にパ
ターン加工された第１半導体層の存在によつて上
記白色光照射加熱下で上記第２半導体層内におけ
る結晶核の発生個所及び該結晶核による結晶成長
を制御する温度分布を上記第２半導体層内に形成
して上記第２半導体層を単結晶化せしめることを
特徴とする半導体装置の製造方法。 ２ 前記第１絶縁性薄膜の形成工程は表面の平坦
化工程を含むことを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。 ３ 前記第２半導体層上に更に第２絶縁性薄膜を
形成して、該第２絶縁性薄膜を介して白色光を照
射することを特徴とする特許請求の範囲第１項又
は第２項記載の半導体装置の製造方法。 ４ 前記第１半導体層をパターン加工する工程
は、第２半導体層の形状に対応させて、適宜間隔
で間欠的に第１半導体層を残存させて形成する工
程を含むことを特徴とする特許請求の範囲第１項
記載の半導体装置の製造方法。[Claims] 1. A step of depositing a first semiconductor layer made of amorphous or polycrystalline material on an insulating substrate, and patterning the first semiconductor layer with the center portion removed; forming a first insulating thin film layer covering the first semiconductor layer patterned with a portion removed and the insulating substrate; A second semiconductor layer is deposited, and the second semiconductor layer is patterned so that the outer edge of the pattern of the first semiconductor layer, which has been patterned with the center portion removed, approximately corresponds to the outer edge of the first semiconductor layer. A step of forming a second semiconductor layer so as to overlap the patterned first semiconductor layer with the center portion removed, and a step of heating the insulating substrate by irradiating white light on the insulating substrate after the above step. Due to the presence of the first semiconductor layer patterned with the center portion removed, the location where crystal nuclei are generated in the second semiconductor layer under the white light irradiation heating and the crystal growth due to the crystal nuclei. A method of manufacturing a semiconductor device, characterized in that the second semiconductor layer is made into a single crystal by forming a temperature distribution in the second semiconductor layer to control the temperature distribution. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first insulating thin film includes a step of planarizing the surface. 3. According to claim 1 or 2, a second insulating thin film is further formed on the second semiconductor layer, and white light is irradiated through the second insulating thin film. A method for manufacturing a semiconductor device. 4. A patent claim characterized in that the step of patterning the first semiconductor layer includes a step of forming the first semiconductor layer so as to remain intermittently at appropriate intervals in accordance with the shape of the second semiconductor layer. A method for manufacturing a semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57047354A JPS58165314A (en) | 1982-03-26 | 1982-03-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57047354A JPS58165314A (en) | 1982-03-26 | 1982-03-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58165314A JPS58165314A (en) | 1983-09-30 |
| JPS6236381B2 true JPS6236381B2 (en) | 1987-08-06 |
Family
ID=12772799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57047354A Granted JPS58165314A (en) | 1982-03-26 | 1982-03-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58165314A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02101767A (en) * | 1988-10-11 | 1990-04-13 | Agency Of Ind Science & Technol | Semiconductor device |
-
1982
- 1982-03-26 JP JP57047354A patent/JPS58165314A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58165314A (en) | 1983-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH084067B2 (en) | Method for manufacturing semiconductor device | |
| JPS6089953A (en) | Manufacture of layered semiconductor device | |
| JPS61244020A (en) | Oriented monocrystalline silicon film with restricted defecton insulation support | |
| JPS5939790A (en) | Production of single crystal | |
| JPS62160712A (en) | Manufacture of semiconductor device | |
| JPH027415A (en) | Formation of soi thin film | |
| US4678538A (en) | Process for the production of an insulating support on an oriented monocrystalline silicon film with localized defects | |
| JPS6236381B2 (en) | ||
| JPS58139423A (en) | Lateral epitaxial growing method | |
| JPS6159820A (en) | Manufacture of semiconductor device | |
| JPH05326692A (en) | Manufacture of semiconductor device | |
| JPS5825220A (en) | Manufacture of semiconductor substrate | |
| JP2745055B2 (en) | Method for manufacturing single crystal semiconductor thin film | |
| JPH03286520A (en) | Manufacture of thin crystalline semiconductor film | |
| JP2695462B2 (en) | Crystalline semiconductor film and method for forming the same | |
| JPH0368532B2 (en) | ||
| JPH03250620A (en) | Manufacture of semiconductor device | |
| JPH03228324A (en) | Growth of thin polycrystalline si film | |
| JPS6184825A (en) | Manufacture of semiconductor substrate | |
| JPH01297814A (en) | Manufacture of single crystal | |
| JPS61201414A (en) | Manufacture of semiconductor single crystal layer | |
| JPH02267931A (en) | Manufacture of semiconductor device | |
| JPH027414A (en) | Formation of soi thin film | |
| JPS5978999A (en) | Manufacture of semiconductor single crystal film | |
| JPH0722120B2 (en) | Method for manufacturing semiconductor device |