JPH01224726A - Production of active matrix element for liquid crystal display - Google Patents

Production of active matrix element for liquid crystal display

Info

Publication number
JPH01224726A
JPH01224726A JP63051879A JP5187988A JPH01224726A JP H01224726 A JPH01224726 A JP H01224726A JP 63051879 A JP63051879 A JP 63051879A JP 5187988 A JP5187988 A JP 5187988A JP H01224726 A JPH01224726 A JP H01224726A
Authority
JP
Japan
Prior art keywords
film
diode
etching
patterning
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63051879A
Other languages
Japanese (ja)
Inventor
Shinji Nishiura
西浦 真治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP63051879A priority Critical patent/JPH01224726A/en
Publication of JPH01224726A publication Critical patent/JPH01224726A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To reduce the number of formed film layers and the number of patterning masks and to produce an element with a low cost by patterning a lower Cr electrode by wet etching and laminating an a-Si film and an upper Cr film and patterning the upper Cr film by wet etching and patterning the a-Si film and insulating the side face of the a-Si film of a diode. CONSTITUTION:After a Cr film 30 formed on a transparent insulating substrate 10 directly or through a transparent conductive film is patterned by the wet etching method, an a-Si film 40 and a Cr film 50 are laminated on the Cr film 30. A resist film is used as the mask to pattern the upper Cr film 50 by the wet etching method, thereby forming upper electrodes of diodes 11 and 12. Thereafter, the resist film and the upper Cr film 50 are used as the mask to form an a-Si film pattern of each diode by etching, and the resist film is incinerated by plasma etching in atmospheric oxygen, and the side face of the a-Si film is oxidized to form an insulating film. Thus, a low-cost active matrix element for liquid crystal display is obtained which has a small number of formed film layers and a small number of masks and does not use a CCl4 dry etching device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、走査線とデータ線の間に逆並列接続したアモ
ルファスシリコン (以下a −3tと記ス)ダイオー
ドが液晶駆動用tBiと直列に接続された液晶テレビな
どのための液晶表示用アクティブマトリクス素子の製造
方法に関する。
Detailed Description of the Invention [Industrial Field of Application] The present invention is characterized in that an amorphous silicon (hereinafter referred to as a-3t) diode connected in antiparallel between a scanning line and a data line is connected in series with tBi for driving a liquid crystal. The present invention relates to a method of manufacturing an active matrix element for a liquid crystal display for a connected liquid crystal television or the like.

〔従来の技術〕[Conventional technology]

液晶テレビの画質を向上させるために、a −3tトラ
ンジスタまたはダイオードを用いたアクティブマトリク
ス駆動の液晶テレビの開発が行われ、製品が市場に出回
りつつある。この種の装置のうちで、ダイオードを用い
るタイプのものは、工程数が少なく低コスト比が容品で
あり、またダイオードを逆並列接続してリングダイオー
ド構成とすt・ るため、安定性にすぐれているという特徴がある。
In order to improve the image quality of liquid crystal televisions, active matrix driven liquid crystal televisions using a-3T transistors or diodes have been developed, and products are now on the market. Among these types of devices, those that use diodes have a small number of steps, are low in cost, and are stable because the diodes are connected in antiparallel to form a ring diode configuration. It has excellent characteristics.

第2図にダイオードを用いたアクティブマトリクス型液
晶表示装置の等価回路図を示す、それぞれ別のガラス基
板に形成された走査411とデータ線2はマトリクス状
をなし、マトリクス走査駆動をすることにより交点に存
在する液晶4を電気的に順次111Mしていくものであ
る。アクティブマトリクス素子は、交点となる液晶駆動
用電極と走査線!の間にそれぞれ数個直列に接続したダ
イオードを並列に接続し、リングダイオード3を形成し
たものを介在させたものである。
Fig. 2 shows an equivalent circuit diagram of an active matrix type liquid crystal display device using diodes. The scanning lines 411 and data lines 2 formed on separate glass substrates form a matrix, and by performing matrix scanning driving, the intersection points are The liquid crystals 4 present in 111M are sequentially electrically converted to 111M. The active matrix element intersects the liquid crystal drive electrode and the scanning line! A ring diode 3 is formed by connecting several series-connected diodes in parallel between the two diodes.

第3図(Ml〜(8)は従来の図8に示す構造のように
2直列のa−51ダイオードをもつアクティブマトリク
ス素子の製造工程を示し、図aにおいてはNaフリーの
硼珪酸系ガラスまたはソーダガラスの上に5108を浸
漬またはスパッタ法等で被覆したガラス基板10の上に
蒸着法またはスパッタ法で形成したITO(インジウム
すず酸化物)+5nO1等の透明導電膜20.スパッタ
法を用いての約1000人の厚さのCr1130.プラ
ズマCVD法を用いて形成したpin接合を有する約4
000人の厚さのa−5l膜40、それぞれスパッタ法
を用いての厚さ約1000人のCr成膜0および厚さ約
3000人のAjl180を形成した。 pin接合は
、約500 人の厚さの9層、約3000人の厚さの1
11 (ノンドープN)および約500 人の厚さの0
層からなる8次に、フォトリソグラフィ法を用いてCr
11250.  a −3t膜40. Cr成膜0をパ
ターニングし、二つのダイオード11.12をCr成膜
1.a −5l膜41゜Cr成膜1とCr成膜2.a 
−31膜4L Cr成膜2で形成する(図b)、このフ
ォトリソグラフィ法は、所望のダイオードパターンのレ
ジスト膜を形成し、これをマスクとして先ず(HzPO
* + HNOs + CHi(:0OH)溶液により
M膜80をパターニングする。このレジスト膜をA71
2で補強したマスクを用いてプラズマエツチングにより
Cr成膜0.a −5l膜40. Cr成膜oツパター
ニングをする。先ず、Cr11950をCC1a と0
.の混合ガスを真空状態で導入し、真空度0.1〜0.
5 Torr、電力200〜1000 Wの条件でプラ
ズマエツチングし、次いでcp、と0.の混合ガスを導
入し、0.05Torr。
Fig. 3 (Ml to (8) shows the manufacturing process of an active matrix element having two series A-51 diodes as in the conventional structure shown in Fig. 8; in Fig. 3, Na-free borosilicate glass or A transparent conductive film 20 of ITO (indium tin oxide) + 5nO1 etc. formed by vapor deposition or sputtering on a glass substrate 10 in which 5108 is coated on soda glass by dipping or sputtering. Cr1130 with a thickness of about 1000. Approx.
An A-5L film 40 with a thickness of about 1,000 people, a Cr film 0 with a thickness of about 1,000 people and an AJI film 180 with a thickness of about 3,000 people were formed using sputtering. The pin junction consists of 9 layers approximately 500 people thick and 1 layer approximately 3000 people thick.
11 (non-doped N) and 0 with a thickness of about 500
The 8-order layer consists of Cr using photolithography method.
11250. a-3t membrane 40. The Cr film 0 is patterned, and the two diodes 11 and 12 are patterned using the Cr film 1. a-5l film 41°Cr film formation 1 and Cr film formation 2. a
-31 film 4L Cr film formation 2 (Figure b). This photolithography method involves forming a resist film with a desired diode pattern, and using this as a mask, first (HzPO
* The M film 80 is patterned using a +HNOs+CHi (:0OH) solution. This resist film is A71
Cr film was formed by plasma etching using the mask reinforced in step 2. a-5l membrane 40. Cr film is formed and patterned. First, Cr11950 is converted into CC1a and 0
.. A mixed gas of
Plasma etching was performed under the conditions of 5 Torr and power of 200 to 1000 W, followed by cp and 0.5 Torr. A mixed gas of 0.05 Torr was introduced.

lk−の条件でa−5iJIQ40をプラズマエンチン
グし、i後に再びCC7,とO,の混合ガスを用いて0
.1〜0、5 Torr、300〜700 Wの条件で
Cr成膜0のエツチングを行う。
A-5iJIQ40 was plasma-etched under the conditions of lk-, and after i, it was etched again using a mixed gas of CC7 and O.
.. Etching of the Cr film 0 is performed under conditions of 1 to 0, 5 Torr, and 300 to 700 W.

次に、フォトリングラフィ法により、レジストマスクを
用いて塩化第二鉄と塩酸の混液によって透明導電120
のエツチングをし、透明i膜パターン21.22.25
を形成する (図cLこのあと、N11.と5l)II
の混合ガスをプラズマ分解するプラズマCVD法により
ダイオード保護用のSiN膜を形成し、SF、とCs 
(J F sの混合ガスを用いてのプラズマエツチング
によるフォトリソグラフィ法でSIN 膜パターン61
.62.63を形成する (図d)、さらにスパッタ法
を用いて1000人の厚さのCr膜と500o人〜ln
の厚さのり膜の2Nからなる金属膜を積層し、フォトリ
ソグラフィ法により金属膜パターン71,72.73を
形成する。この結果、ダイオード11とダイオード12
とが直列接続され、画素電極25と走査&I73の間に
挿入される (図e)、金属膜としてCr膜とA7膜の
積層膜を用いるのは、Mのエツチングのときの雰囲気が
ITO膜に損傷を与えるのを防ぐためである。
Next, using a photolithography method, a transparent conductive film was formed using a mixed solution of ferric chloride and hydrochloric acid using a resist mask.
21.22.25
(Figure cL, after this, N11. and 5l) II
A SiN film for protecting the diode is formed by plasma CVD method in which a mixed gas of SF and Cs is decomposed by plasma.
(The SIN film pattern 61 was formed by photolithography using plasma etching using a mixed gas of JFs.
.. 62.63 (Figure d), and then use a sputtering method to form a 1000mm thick Cr film and a 500mm thick Cr film.
A metal film made of a 2N adhesive film having a thickness of 2N is laminated, and metal film patterns 71, 72, and 73 are formed by photolithography. As a result, diode 11 and diode 12
are connected in series and inserted between the pixel electrode 25 and the scanning &I 73 (Figure e).The reason why a laminated film of a Cr film and an A7 film is used as the metal film is that the atmosphere during etching of M is similar to that of the ITO film. This is to prevent damage.

〔発明が解決しようとする!!1!題〕第3図で説明し
た従来の液晶表示用アクティブマトリクス素子の%i造
工程には次の問題点がある。
[Invention tries to solve it! ! 1! [Problem] The conventional manufacturing process for active matrix elements for liquid crystal displays as explained in FIG. 3 has the following problems.

+11成膜眉がI T 0FI20. Cr1li30
.  a−5te4o、 Cr成膜0.  A7膜80
.  SiN膜 (パターン61,62.63を形成)
および二層膜(パターン?1,72.73を形成)のた
めのCr膜、kI膜の8W!iの多数になる。
+11 film eyebrows IT 0FI20. Cr1li30
.. a-5te4o, Cr film formation 0. A7 membrane 80
.. SiN film (patterns 61, 62, and 63 are formed)
and 8W of Cr film and kI film for double layer film (forming pattern ?1,72.73)! becomes the majority of i.

(2)ダイオード11.12の形成のためにCr成膜0
.a−31膜40. Cr1i30の3711のパター
ニングをプラズマエツチングで行う際、サイドエツチン
グのためにひさしができないように、異方性の強い反応
性イオンエツチングモードの条件とする必要があり、そ
のため電力も大きく、電位的にも基板を接地側と反対の
電極に搭載する必要もあってエツチング装置上問題が多
い。
(2) Cr film is formed to form diodes 11 and 12.
.. a-31 membrane 40. When patterning 3711 of Cr1i30 by plasma etching, it is necessary to use a reactive ion etching mode with strong anisotropy to avoid side etching, which requires high power and potential. It is also necessary to mount the substrate on the electrode opposite to the ground side, which causes many problems with the etching equipment.

(31Crのエツチングに用いるCC7,のために、a
ラジカルが生じてCrを腐食するので、ステンレス鋼を
装置に用いることができないという制限があり、また乙
により真空ポンプの油が劣化するためその対策が必要と
なる。
(For CC7, used for etching 31Cr, a
There is a restriction that stainless steel cannot be used in the device because radicals are generated and corrode Cr, and since the oil in the vacuum pump deteriorates due to Cr, countermeasures are required.

本発明の課題は、上述の問題点をとり除き、成膜層数、
マスク数が少なく、CCl2系のドライエツチング装置
を用いない、低コストの液晶表示用アクティブマトリク
ス素子の製造方法を提供することにある。
The object of the present invention is to eliminate the above-mentioned problems, reduce the number of film layers,
It is an object of the present invention to provide a low-cost method for manufacturing an active matrix element for a liquid crystal display, which requires a small number of masks and does not use a CCl2-based dry etching device.

(!ill!Jを解決するための手段〕上記の!l!J
の解決のために、本発明は、走査線とデータ線の間に逆
並列接続のa−3lダイオードが液晶駆動用電極と直列
に接続されるアクティブマトリクス素子のダイオードの
形成の際に、透明絶縁基板上に直接または透明導電膜を
介して形成したCr膜を湿式エツチング法でパターニン
グ後、その上にa−3l膜およびCr膜を積層成膜し、
レジスト膜をマスクとして上部Cr膜を湿式エツチング
法でパターニングして各ダイオードの上部電極を形成後
、レジスト膜および上部Cr1IIIをマスクにしての
エツチングにより各ダイオードのa −5l膜パターン
を形成し、酸素雰囲気中でのプラズマエツチングにより
レジスト膜を灰化すると共に、a−3illl側面を酸
化して絶縁膜を形成するものとする。
(Means for solving !ill!J) The above !l!J
In order to solve this problem, the present invention provides a method for forming a diode of an active matrix element in which an anti-parallel A-3L diode is connected between a scanning line and a data line in series with a liquid crystal driving electrode. After patterning the Cr film formed directly on the substrate or via a transparent conductive film by wet etching, an A-3L film and a Cr film are laminated thereon,
After patterning the upper Cr film by wet etching using the resist film as a mask to form the upper electrode of each diode, an a-5L film pattern of each diode is formed by etching using the resist film and the upper Cr1III as a mask. The resist film is ashed by plasma etching in an atmosphere, and the side surfaces of the a-3ill are oxidized to form an insulating film.

〔作用〕[Effect]

Cr1lQのエツチングを湿式エツチングで行うためC
c14系ガスや弗素系ガスを用いたドライエツチング、
反応性イオンエツチングが不要となり、下部Cr119
のパターニングも別に行うため、このCr膜を接続配線
あるいはITO電極あるいは配線の保−謹にも利用でき
る。またレジスト膜の沃化と同時にa−31膜側面に絶
縁膜が形成されるため、絶縁膜の成膜、パターニングが
不要になる。
Since etching of Cr1lQ is done by wet etching,
Dry etching using C14 gas or fluorine gas,
Reactive ion etching is no longer required, and the lower Cr119
Since the patterning is also performed separately, this Cr film can also be used for connection wiring, ITO electrodes, or wiring. Further, since an insulating film is formed on the side surface of the a-31 film at the same time as the iodization of the resist film, formation and patterning of the insulating film are not required.

〔実施例〕〔Example〕

第1図+al〜(flは本発明の第一の実施例の工程を
示し、第3図と共通の部分には同一の符号が付されてい
る0図aにおいては、ガラス基板1oの上に電子ビーム
またはスパッタ蒸着法によりITO膜20を1000〜
2000人の厚さに成膜し、その上にスパッタ法でCr
成膜0を1000〜2000人の厚さに成膜した。
Figure 1+al~(fl indicates the process of the first embodiment of the present invention, and parts common to those in Figure 3 are given the same reference numerals.) The ITO film 20 is formed by electron beam or sputter deposition method to
A film was formed to a thickness of 2,000 yen, and Cr was deposited on top of it by sputtering.
Film formation 0 was formed to a thickness of 1000 to 2000 layers.

次にフォトリングラフィ法により図示しないレジストパ
ターンを形成し、これをマスクとしてCr11130を
硝酸第二セリウムアンモンと過塩素酸の混合液でエツチ
ングしてC「膜のパターン31,32.35を形成し、
ひきつ゛づき塩化第二鉄と塩酸の混液でITO膜20を
エツチングしてCr1lQと同一のパターン21゜22
、25を形成した (図b)0次いで、反応層に真空度
0−1〜I Torr、電力500W 〜lk−の条件
で生成した11.プラズマ内に5分放置後、プラズマC
VD法を用いてpin接合を有するa−311a40を
、約4000 人の厚さに全面成膜、ひきつづいてスパ
ッタ法を用いてCr成膜0を1000〜2000人の厚
さでその上に蒸着した く図c)、この積層膜の上にフ
ォトリングラフィ法を用いて図示しないレジストパター
ンを被着させ、Cr成膜0を硝酸第二セリウムアンモン
と過塩素酸の混合液を用いてダイオードの上部電臘とな
るCr膜パターン51 、52を形成し、レジストパタ
ーン+ Cr1llパターンをマスクにしてa −5t
lliをドライエツチングして各ダイオードのa −5
tl1141.42のパターンを形成した。ドライエツ
チングはSF4と(:、(JP、の混合ガスを用いて真
空度0.1〜0、5 Torr、電力200 W〜I 
KWの条件で行った。その後反応槽に酸素ガスを導入し
て真空度0.1〜0、5 Torr、電力300〜I 
K−の条件で放電し、レジスト膜の灰化を行った(図d
)、この結果5.Cr1PJ31゜a −3IIf14
1. Cr成膜1よりなるダイオード11と、Cr成膜
2.  a −51膜42+ Cr成膜2よりなるダイ
オード12が構成される1次にスパッタ蒸着によりアル
ミニウム膜80を全面に5000人〜1−の厚さに被着
しく図e)、その上にフォトリソグラフィ法により図示
しないレジストパターンを形成、HsPOsとHHOs
の混液でエツチングしてM配線パターン81.82およ
び走査線パターン83を形成した。さらに硝酸第二セリ
ウムアンモンと過塩素酸の混合液でエツチングすること
により、ITO!i上のulパターン81.82,83
.  a−st′Bバター741.42で覆われティな
いCr1Lが除去され、Cr成膜1からM配線82の下
の部分34. Cr成膜2から走査線83の下の部分3
3が分離され、ITOからなる画素電極25の上にはM
配線81の下の部分にのみCrH35が残る (図r>
Next, a resist pattern (not shown) is formed by photolithography, and using this as a mask, Cr11130 is etched with a mixture of ceric ammonium nitrate and perchloric acid to form C" film patterns 31, 32, and 35. ,
Subsequently, the ITO film 20 was etched with a mixture of ferric chloride and hydrochloric acid to form a pattern 21°22 identical to that of Cr1lQ.
, 25 was formed (Figure b) 0. Next, 11. After leaving it in the plasma for 5 minutes, plasma C
A-311A40 having a pin junction was deposited on the entire surface using the VD method to a thickness of about 4,000 layers, and then a Cr film 0 was deposited on it using a sputtering method to a thickness of 1,000 to 2,000 layers. In Figure c), a resist pattern (not shown) is deposited on this laminated film using the photolithography method, and the Cr film 0 is deposited on the upper part of the diode using a mixed solution of ceric ammonium nitrate and perchloric acid. Form Cr film patterns 51 and 52 that will serve as electrical connections, and use the resist pattern + Cr1ll pattern as a mask to form a-5t
a-5 of each diode by dry etching
A pattern of tl1141.42 was formed. Dry etching was performed using a mixed gas of SF4 and (:, (JP,
It was conducted under KW conditions. After that, oxygen gas was introduced into the reaction tank, the degree of vacuum was 0.1~0, 5 Torr, and the electric power was 300~I.
The resist film was ashed by discharging under K- conditions (Figure d)
), this result 5. Cr1PJ31゜a -3IIf14
1. A diode 11 made of a Cr film 1, a Cr film 2. a-51 film 42+ A diode 12 is formed by forming a Cr film 2. First, an aluminum film 80 is deposited on the entire surface by sputter deposition to a thickness of 5000 to 1- (Fig. e), and then photolithography is applied thereon. Form a resist pattern (not shown) by the method, HsPOs and HHOs
M wiring patterns 81 and 82 and scanning line patterns 83 were formed by etching with a mixed solution of. Furthermore, by etching with a mixture of ceric ammonium nitrate and perchloric acid, ITO! ul pattern on i 81, 82, 83
.. The untied Cr1L covered with the a-st'B butter 741.42 is removed, and the portion 34. Part 3 below the scanning line 83 from the Cr film formation 2
3 is separated, and on the pixel electrode 25 made of ITO, M is separated.
CrH35 remains only under the wiring 81 (Figure r>
.

この第一の実施例においては次の利点がある。This first embodiment has the following advantages.

(11成膜層はI T O11A20. Cr成膜0.
  a −5tll!140. Cr111150、 
Af膜8017)5Nテ、層数が第3図の場合に比し3
N減少する。
(The 11th film layer is ITO11A20.Cr film 0.
a-5tll! 140. Cr111150,
Af film 8017) 5Nte, the number of layers is 3 compared to the case in Figure 3.
N decreases.

(21Crのドライエツチングが不要となり、Uラジカ
ルにより装置1真空排気系等に生ずる支障が解消する。
(Dry etching of 21Cr becomes unnecessary, and problems caused by U radicals to the vacuum evacuation system of the apparatus 1 are eliminated.

(3)基板を接地側の電極上に搭載してのSF4とc、
cIF。
(3) SF4 and c with the board mounted on the ground side electrode,
cIF.

ノ混合ガス系を用いてa−sagのプラズマエ。Plasma of A-SAG using mixed gas system.

チングが可能となり、反応性イオンエツチング法に比し
装置が簡単になる。
etching, and the equipment is simpler than reactive ion etching.

(4)ダイオードパターン形成後のレジスト膜除去をプ
ラズマアッシングで行うことにより、各ダイオードのa
−3i膜の側面が絶縁化され、SIN絶縁膜の成膜およ
びパターニングが不要となった。
(4) By using plasma ashing to remove the resist film after forming the diode pattern, each diode's a
The side surfaces of the -3i film are insulated, making it unnecessary to form and pattern a SIN insulating film.

絶縁化はa−3t膜側面の酸化によると考えられるが、
これでパターニング用のマスクは従来の4枚から3枚に
減少する。
The insulation is thought to be due to oxidation of the side surface of the a-3t film,
This reduces the number of patterning masks from the conventional four to three.

第4図(at〜fdlは本発明の第二の実施例の工程を
示し、第1図1第3図と共通の部分には同一の符号が付
されている。先ず、ガラス基板1oの上にスパッタ法に
より厚さ1000〜2000人のCr成膜0を成膜した
 (図8)0次にフォトリソグラフィ法によりレジスト
パターンを形成し、それをマスクにしてC「膜30を硝
酸第二セリウムアンモンと過塩素酸の混合液でエツチン
グしCr膜パターン31.32を形成する (図b>、
次いで、第1図1第3におけると同様な方法でpin接
合を有するa−5l膜40を約4000人の厚さに、さ
らにCr成膜0を1000〜2000人の厚さに積層し
たのち、フォトリソグラフィ法を用いてレジストパター
ンを形成し、硝酸第二セリウムアンモンと過塩素酸の混
合液を用いてダイオードの上部電極51.52を形成し
、ひきつづきレジストパターン、Cr膜パターンをマス
クにして第1図1第3と同じ条件のドライエツチングで
各ダイオードのa −3illlパターン41.42を
形成、さらに反応槽にO8を導入し、同じく第1図(d
iと同じ条件でレジストのプラズマアッシングを行った
 (図c)、最後にスパッタ蒸着により1000〜20
00人のITO膜を成膜し、フォトリソグラフィ法によ
りレジストパターンを形成し、塩化第二鉄と塩酸の混液
を用いてエツチングし、ITOの画素電極25とそれに
つながりダイオード11の上部Cr電8i51に接触す
るITO配線21. ダイオード11の下部C4tM3
1とダイオード12の上部Cr電極52に接触し、両ダ
イオードを直列接続する夏To配線22およびC「電極
32の延長部に接触するITO走査腺23のパターニン
グを行った。
FIG. 4 (at to fdl shows the steps of the second embodiment of the present invention, and the same parts as in FIG. 1 and FIG. 3 are given the same reference numerals. A Cr film 30 with a thickness of 1,000 to 2,000 layers was formed by sputtering (Figure 8).Next, a resist pattern was formed by photolithography, and using this as a mask, the Cr film 30 was coated with ceric nitrate. Form Cr film patterns 31 and 32 by etching with a mixture of ammonium and perchloric acid (Figure b>,
Next, the A-5L film 40 having a pin junction was laminated to a thickness of about 4000 wafers in the same manner as in FIG. A resist pattern is formed using a photolithography method, and upper electrodes 51 and 52 of the diode are formed using a mixture of ceric ammonium nitrate and perchloric acid. 1 A-3ill patterns 41 and 42 of each diode were formed by dry etching under the same conditions as in Figure 1 (d).
Plasma ashing of the resist was performed under the same conditions as in i (Figure c), and finally sputter deposition was performed to obtain a
A resist pattern is formed by photolithography, and etched using a mixture of ferric chloride and hydrochloric acid to form an ITO pixel electrode 25 and the upper Cr electrode 8i51 of the diode 11 connected to it. Contacting ITO wiring 21. Lower part of diode 11 C4tM3
Patterning was carried out for the summer To wire 22 that contacts the upper Cr electrode 52 of the diode 1 and the diode 12 and connects both diodes in series, and the ITO scanning wire 23 that contacts the extension of the C electrode 32.

この第二の実施例の利点は第一の実施例につぃて挙げた
利点のほかに次のものがある。
The advantages of this second embodiment are, in addition to those listed for the first embodiment, as follows.

(1)成膜層がCr成膜  a  St膜+Cr成膜ヨ
びITO膜の4層のみでさらに層数が1111少する。
(1) Cr film formation a The number of layers is 1111 fewer because there are only 4 layers: St film + Cr film + ITO film.

(2)第一の実施例に比較して上部Cr膜極の後退がな
く、光の素子に与える影響が少なくなった。
(2) Compared to the first example, the upper Cr film pole did not recede, and the influence on the optical element was reduced.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ダイオードを形成する下部Cr電極の
パターニングを湿式エツチングで行ったのち、a−5l
膜、上部Cr膜を積層し、上部Cr膜のパターニングも
湿式で行い、そのあとa −3i膜のパターニングを行
い、パターニングに使用したレジスト膜の灰化のための
01中でのプラズマエツチングによりダイオードのa 
−3l成膜面の絶縁化を行うことにより、成膜層数の減
少、パターニングマスクも3枚に減少するほか、Cr1
llのパターニングにU系あるいはF系ガスを用いたド
ライエツチング、反応性イオンエツチングなど高価な装
置を必要とする方法をとらないので設備費も減少し、ア
クティブマトリクス素子を低コストで製造する上に極め
て有効である。
According to the present invention, after patterning the lower Cr electrode forming the diode by wet etching,
The upper Cr film was layered, and the upper Cr film was patterned using a wet method. After that, the a-3i film was patterned, and the diode was formed by plasma etching in 01 to ash the resist film used for patterning. a of
By insulating the -3l film formation surface, the number of film formation layers is reduced and the number of patterning masks is reduced to three, as well as Cr1
Since dry etching using U-based or F-based gases and reactive ion etching, which require expensive equipment, are not used for patterning the 1100 µm, equipment costs are also reduced, making it possible to manufacture active matrix elements at low cost. Extremely effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第一の実施例の工程を順に示す断面図
、第2図はダイオードを備えたアクティブマトリクス基
板を用いた液晶表示装置の等価回路図、第3図は従来の
アクティブマトリクス素子製造方法の工程を順に示す断
面図、第4図は本発明の第二の実施例の工程を順に示す
断面図である。 10ニガラス基ヰ反、20:rTOIQ、21.22+
 I TO配線、23+ITO走査線、25+ITO画
素電極、30、31.32.50.51.52: Cr
膜、40.41.42: a−51膜、81,82:A
7配線、83:A7走査線。 第1図 第2図 第3図 第4図
FIG. 1 is a cross-sectional view showing the steps of the first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a liquid crystal display device using an active matrix substrate equipped with diodes, and FIG. 3 is a diagram of a conventional active matrix. FIG. 4 is a cross-sectional view sequentially showing the steps of the device manufacturing method, and FIG. 4 is a cross-sectional view sequentially showing the steps of the second embodiment of the present invention. 10 Nigarasu group, 20:rTOIQ, 21.22+
ITO wiring, 23+ITO scanning line, 25+ITO pixel electrode, 30, 31.32.50.51.52: Cr
Membrane, 40.41.42: a-51 membrane, 81,82:A
7 wiring, 83: A7 scanning line. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1)走査線とデータ線の間に逆並列接続のアモルファス
シリコンダイオードが液晶駆動用電極と直列接続される
アクティブマトリクス素子のダイオード形成の際に、透
明絶縁基板上に直接または透明導電膜を介して形成した
クロム膜を湿式エッチング法でパターニング後、その上
にアモルファスシリコン膜およびクロム膜を積層成膜し
、レジスト膜をマスクとして上部クロム膜を湿式エッチ
ング法でパターニングして各ダイオードの上部電極を形
成後、前記レジスト膜および上部クロム膜をマスクにし
てエッチングして各ダイオードのアモルファスシリコン
膜パターンを形成し、酸素雰囲気中でのプラズマエッチ
ングによりレジスト膜を灰化すると共にアモルファスシ
リコン膜側面を酸化して絶縁膜を形成することを特徴と
する液晶表示用アクティブマトリクス素子の製造方法。
1) When forming the diode of an active matrix element in which amorphous silicon diodes are connected in antiparallel between the scanning line and the data line and are connected in series with the liquid crystal driving electrode, the amorphous silicon diode is placed directly on a transparent insulating substrate or through a transparent conductive film. After patterning the formed chromium film using a wet etching method, an amorphous silicon film and a chromium film are layered on top of it, and the upper chromium film is patterned using a wet etching method using the resist film as a mask to form the upper electrode of each diode. After that, etching is performed using the resist film and the upper chromium film as masks to form an amorphous silicon film pattern for each diode, and the resist film is ashed by plasma etching in an oxygen atmosphere, and the sides of the amorphous silicon film are oxidized. A method for manufacturing an active matrix element for a liquid crystal display, the method comprising forming an insulating film.
JP63051879A 1988-03-04 1988-03-04 Production of active matrix element for liquid crystal display Pending JPH01224726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63051879A JPH01224726A (en) 1988-03-04 1988-03-04 Production of active matrix element for liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63051879A JPH01224726A (en) 1988-03-04 1988-03-04 Production of active matrix element for liquid crystal display

Publications (1)

Publication Number Publication Date
JPH01224726A true JPH01224726A (en) 1989-09-07

Family

ID=12899168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63051879A Pending JPH01224726A (en) 1988-03-04 1988-03-04 Production of active matrix element for liquid crystal display

Country Status (1)

Country Link
JP (1) JPH01224726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924862B2 (en) * 2001-09-08 2005-08-02 Lg.Philips Lcd Co., Ltd. Method for fabricating liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924862B2 (en) * 2001-09-08 2005-08-02 Lg.Philips Lcd Co., Ltd. Method for fabricating liquid crystal display device

Similar Documents

Publication Publication Date Title
US5366588A (en) Method of manufacturing an electrically conductive pattern of tin-doped indium oxide (ITO) on a substrate
JPS63316470A (en) Manufacture of thin film transistor
US6905917B2 (en) Thin film transistor array panel for liquid crystal display and method for manufacturing the same
JPH0862628A (en) Liquid crystal display element and its production
JP2001166336A (en) Method of producing liquid crystal display device and method of forming wires in liquid crystal display device
JP2001183639A (en) Method of manufacturing thin film transistor array substrate
JPH01224726A (en) Production of active matrix element for liquid crystal display
JP2004241395A (en) Method of patterning multilayer film and multilayer wiring electrode
JPH1082997A (en) Production of active matrix liquid crystal display device and active matrix liquid crystal display device
JPH01259565A (en) Thin film transistor and manufacture of the same
JPH05119331A (en) Active matrix substrate and its production
JP2000165002A (en) Electronic device board therefor, its manufacture and electronic device
JPH07134312A (en) Liquid crystal display device and its production
JPH01224725A (en) Active matrix element for liquid crystal display
JPH0346630A (en) Production of thin-film diode
JPH0266520A (en) Manufacture of active matrix element for liquid crystal display
JPH028819A (en) Manufacture of active matrix element
JPH0227319A (en) Manufacture of thin film diode in liquid crystal display device
JPH022636A (en) Manufacture of thin film transistor array
JPH01180523A (en) Thin-film transistor matrix and its production
KR101258256B1 (en) method for fabricating Array substrate for liquid crystal display
JP2781383B2 (en) Method for manufacturing thin film transistor array
JPH11258634A (en) Production of array substrate for display device
KR0133863B1 (en) Thin film transistor
JPH07191346A (en) Production of thin film transistor array