JPH028819A - Manufacture of active matrix element - Google Patents
Manufacture of active matrix elementInfo
- Publication number
- JPH028819A JPH028819A JP63159968A JP15996888A JPH028819A JP H028819 A JPH028819 A JP H028819A JP 63159968 A JP63159968 A JP 63159968A JP 15996888 A JP15996888 A JP 15996888A JP H028819 A JPH028819 A JP H028819A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- photoresist
- semiconductor film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000992 sputter etching Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 241001464057 Electroma Species 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマトリックス状に配置した各画素に設けたスイ
ッチング素子を制御することにより、液晶を駆動して画
像表示を行なう、液晶表示装置におけるアクティブマト
リックス素子の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is an active device in a liquid crystal display device that drives a liquid crystal to display an image by controlling switching elements provided in each pixel arranged in a matrix. The present invention relates to a method for manufacturing a matrix element.
アモルファスルミｎダイオードを液晶駆動のスイッチン
グ素子として使用したものが、例えば特開昭６３−１４
１２８号公報に記載されている。For example, a device using an amorphous lumi n diode as a switching element for driving a liquid crystal is disclosed in Japanese Patent Application Laid-open No. 63-14.
It is described in Publication No. 128.
これは第３図に示すように、一方の基板に走査電極６４
と画素電極とを設け、この走査電極３４と画素電極との
間に複数のダイオード４０をリング状に接続する。他方
の基板にはデータ電極３６を設け、２枚の基板間に液晶
４２を封入し、ダイオード４０を制御して画像表示を行
な５゜このダイオードの構造を第４図の断面図に示す。As shown in FIG.
and a pixel electrode are provided, and a plurality of diodes 40 are connected in a ring shape between the scanning electrode 34 and the pixel electrode. A data electrode 36 is provided on the other substrate, a liquid crystal 42 is sealed between the two substrates, and a diode 40 is controlled to display an image.The structure of this diode is shown in the sectional view of FIG.
なお第４図は１つのダイオードを図示しである。Note that FIG. 4 shows one diode.
基板１２上に透明導電膜１４からなる走査電極６４と画
素電極３８とを設け、画素電極３８上に半導体膜２４を
設ける。この半導体膜２４はアモルファスシリコンから
なり、導電型がｐｉｎ構造を有する。半導体膜２４と画
素電極６８との間には金属膜２２を設ける。この金属膜
２２は基板１２下面からの透過光が半導体膜２４に照射
されたとき、半導体膜２４ｐｉｎ接合にリーク電流が流
れ、ダイオードがスイッチング素子としての機能を果さ
ず、表示画像品位が低下することを防止するための遮光
膜として設けである。さらに半導体膜２４と走査電極６
４とを接続する配線６２を形成する。この第４図に示す
ダイオードは、透明導電膜１４のパターニングと、半導
体膜２４のパターニングと、配線６２のパターニングと
により製造される。すなわち３枚のマスクでダイオード
素子が形成できる。A scanning electrode 64 made of a transparent conductive film 14 and a pixel electrode 38 are provided on the substrate 12, and a semiconductor film 24 is provided on the pixel electrode 38. This semiconductor film 24 is made of amorphous silicon and has a pin conductivity type. A metal film 22 is provided between the semiconductor film 24 and the pixel electrode 68. When the semiconductor film 24 is irradiated with transmitted light from the bottom surface of the substrate 12, a leakage current flows through the semiconductor film 24 pin junction, the diode does not function as a switching element, and the quality of the displayed image deteriorates. It is provided as a light shielding film to prevent this. Furthermore, the semiconductor film 24 and the scanning electrode 6
4 is formed. The diode shown in FIG. 4 is manufactured by patterning the transparent conductive film 14, the semiconductor film 24, and the wiring 62. That is, a diode element can be formed using three masks.
しかしながら第４図に示す従来例におけるダイオードは
、基板１２下面からの透過光を遮光するために設けた金
属膜２２が、半導体膜２４下面の一部の領域しか形成さ
れていない。このため半導体膜２４には光照射に起因す
るリーク電流が流れダイオードがスイッチング素子とし
ての機能を果さず、したがって表示画像品位に対する対
応は充分ではない。なお第４図に示すダイオード構造に
おいて、半導体膜２４下面の全面に金属膜２２を形成せ
ず一部領域にのみ金属膜２２を形成しているのは、側面
部にて金属膜２２と配線３２とが短絡してしまうので、
半導体膜２４下面の一部領域にのみ金属膜２２を形成し
ている。However, in the conventional diode shown in FIG. 4, the metal film 22 provided to block light transmitted from the bottom surface of the substrate 12 is formed only in a part of the bottom surface of the semiconductor film 24. For this reason, a leakage current due to light irradiation flows in the semiconductor film 24, and the diode does not function as a switching element, so that the display image quality is not sufficiently improved. In the diode structure shown in FIG. 4, the reason why the metal film 22 is not formed on the entire lower surface of the semiconductor film 24 but only in a partial region is because the metal film 22 and the wiring 32 are formed on the side surface. This causes a short circuit between the
The metal film 22 is formed only in a partial region of the lower surface of the semiconductor film 24.
上記課題を解決して半導体膜における光照射に起因する
リーク電流発生を抑えるための製造方法を提供すること
が本発明の目的である。It is an object of the present invention to provide a manufacturing method for solving the above problems and suppressing the occurrence of leakage current caused by light irradiation in a semiconductor film.
上記目的を達成するため本発明におけるアクティブマト
リックス素子は、下記記載の製造工程により製造する。In order to achieve the above object, the active matrix element of the present invention is manufactured by the manufacturing process described below.
基板上の全面に透明導電膜を形成しこの透明導電膜上に
第１のホトレジストを形成しこの第１のホトレジストを
マスクにして透明導電膜をエツチングして走査電極と画
素電極とを形成する工程と、全面に金属膜と半導体膜と
を順次形成しこの半導体膜上に第２のホトレジストを形
成する工程と、この第２のホトレジストをマスクにして
半導体膜と金属膜とを所定形状にエツチングする工程と
、全面に絶縁膜を形成する工程と、この絶縁膜な異方性
イオンエツチングによりエツチングして半導体膜と金属
膜との側面に絶縁膜からなる側壁絶縁膜を形成する工程
と、全面に導電膜を形成しこの導電膜上に第３のホトレ
ジストを形成しこの第３のホトレジストをマスクにして
導電膜をエツチングして配線を形成し第３のホトレジス
ト開口部の半導体膜と金属膜とを除去する工程とを有す
る。A step of forming a transparent conductive film on the entire surface of the substrate, forming a first photoresist on the transparent conductive film, and etching the transparent conductive film using the first photoresist as a mask to form a scanning electrode and a pixel electrode. a step of sequentially forming a metal film and a semiconductor film over the entire surface and forming a second photoresist on the semiconductor film; and etching the semiconductor film and the metal film into a predetermined shape using the second photoresist as a mask. a step of forming an insulating film on the entire surface; a step of etching this insulating film by anisotropic ion etching to form a sidewall insulating film made of an insulating film on the side surfaces of the semiconductor film and metal film; A conductive film is formed, a third photoresist is formed on the conductive film, and the conductive film is etched using the third photoresist as a mask to form wiring, and the semiconductor film and metal film in the third photoresist opening are separated. and a step of removing.
以下図面を用いて本発明の詳細な説明する。 The present invention will be described in detail below using the drawings.
第１図（ａｌ〜（ｆ）は本発明におけるアクティブマト
リックス素子の製造方法を工程順に示す断面図、第２図
は本発明のアクティブマトリックス素子を示す平面図で
ある。なお第１図は第２図におけるＡ−Ａ断面を示す。1A to 1F are cross-sectional views showing the method for manufacturing an active matrix device according to the present invention in order of steps, and FIG. 2 is a plan view showing the active matrix device according to the present invention. The AA cross section in the figure is shown.
以下第１図および第２図を交互に参照して説明する。The following description will be given with reference to FIG. 1 and FIG. 2 alternately.
まず第１図［ａｌに示すように、透明ガラスからなる基
板１２にスパッタリング法あるいは蒸着法により、透明
導電膜１４として酸化インジウムスズ（ＩＴＯ）を厚さ
１５０ｎｍ〜２００ｎｍ形成する。その後感光性樹脂を
全面に塗布して、マスクを用いて露光、および現像を行
ない第１のホトレジスト１６を形成する。この第１のホ
トレジスト１６の平面パターン形状は、第２図の実線４
４に示す。第１のホトレジスト１６をエツチングのマス
クとして透明導電膜１４を、塩化第二鉄と塩酸との混合
溶液でエツチングして、画素電極３８と走査電極３４と
を形成する。その後硫酸と過酸化水素との混合溶液中で
、第１のホトレジスト１６を除去する。First, as shown in FIG. 1 [al], indium tin oxide (ITO) is formed as a transparent conductive film 14 to a thickness of 150 nm to 200 nm on a substrate 12 made of transparent glass by sputtering or vapor deposition. Thereafter, a photosensitive resin is applied to the entire surface, exposed to light using a mask, and developed to form a first photoresist 16. The planar pattern shape of the first photoresist 16 is indicated by the solid line 4 in FIG.
4. Using the first photoresist 16 as an etching mask, the transparent conductive film 14 is etched with a mixed solution of ferric chloride and hydrochloric acid to form a pixel electrode 38 and a scanning electrode 34. Thereafter, the first photoresist 16 is removed in a mixed solution of sulfuric acid and hydrogen peroxide.
次に第１図（ｂｌに示すように、スパッタリング法ある
いは蒸着法により、金属膜２２としてモリブデンを１１
００ｎ程度の厚さで形成する。金属膜２２としてはモリ
ブデン以外にタンタル、チタニウム、タングステン、り
α−ム、アルミニウム、あるいはこれらの材料を主成分
とする複合合金、もしくはこれらの材料の積層膜で構成
しても良い。Next, as shown in FIG. 1 (bl), molybdenum is coated with 11
It is formed with a thickness of about 00n. In addition to molybdenum, the metal film 22 may be made of tantalum, titanium, tungsten, aluminum, aluminum, a composite alloy containing these materials as main components, or a laminated film of these materials.
その後プラズマ気相成長法により、アモルファスシリコ
ンからなる半導体膜２４を厚さ３ Ｑ Ｑ ｎｍ〜５０
０ｎｍ形成する。この半導体膜２４の形成方法は電子サ
イクロトン共鳴気相成長法、熱化学気相成長法、スパッ
タリング法、蒸着法を用いても良い。半導体膜２４は、
金属＠２２側からｐ型、ｉ型すなわち真性半導体、ｎ型
のダイオード構造を有する。この半導体膜２４の導電型
としては、上記のｐｉｎ構造のほかに” ’ ｐｓ Ｉ
） １％ ｎｐ槽構造も良い。その後感光性樹脂を全面
に形成して、マスクを用いて露光、および現像を行ない
第２のホトレジスト１８を形成する。この第２のホトレ
ジスト１８の平面パターン形状は、第２図の破線４６で
示す。その後第２のホトレジスト１８をエツチングのマ
スクとし、ドライエツチング装置として例えば反応性イ
オンエツチング装置で、エツチングガスとして四フッ化
炭素と酸素との混合ガスを用いて、半導体膜２４と金属
膜２２とをエツチングする。その後第２のホトレジスト
１８を除去する。Thereafter, a semiconductor film 24 made of amorphous silicon is formed to a thickness of 3 Q Q nm to 50 nm by plasma vapor phase epitaxy.
0 nm is formed. The semiconductor film 24 may be formed by electron cycloton resonance vapor deposition, thermal chemical vapor deposition, sputtering, or vapor deposition. The semiconductor film 24 is
It has a diode structure of p-type, i-type, that is, an intrinsic semiconductor, and n-type from the metal@22 side. In addition to the above-mentioned pin structure, the conductivity type of this semiconductor film 24 is "' ps I
) 1% NP tank structure is also good. Thereafter, a photosensitive resin is formed on the entire surface, exposed to light using a mask, and developed to form a second photoresist 18. The planar pattern shape of this second photoresist 18 is indicated by a broken line 46 in FIG. Thereafter, using the second photoresist 18 as an etching mask, the semiconductor film 24 and the metal film 22 are etched using a dry etching device such as a reactive ion etching device and using a mixed gas of carbon tetrafluoride and oxygen as an etching gas. Etching. Thereafter, the second photoresist 18 is removed.
次に第１図（Ｃ）に示すように、化学気相成長法あるい
はスパッタリング法により、絶縁膜２６として酸化シリ
コン膜を膜厚３００ｎｍ程度全面に形成する。絶縁膜２
６としては酸化シリコン膜以外に、窒化シリコン膜も使
用できる。Next, as shown in FIG. 1C, a silicon oxide film is formed as an insulating film 26 over the entire surface by chemical vapor deposition or sputtering to a thickness of about 300 nm. Insulating film 2
As 6, a silicon nitride film can also be used in addition to a silicon oxide film.
次に第１図（ｄ）に示す、ように、異方性イオンエツチ
ング法により、絶縁膜２６をエツチングして金属膜２２
と半導体膜２４との側面に側壁絶縁膜２８を形成する。Next, as shown in FIG. 1(d), the insulating film 26 is etched using an anisotropic ion etching method, and the metal film 22 is etched.
A sidewall insulating film 28 is formed on the side surfaces of the semiconductor film 24 and the semiconductor film 24 .
異方性イオンエツチング法においては、エツチング反応
を引き起こすイオンが、基板１２に対して垂直方向に加
速されながら反応するので、第１図（Ｃ１に示す絶縁膜
２６は基板１２の垂直方向にのみエツチングされ、第１
図（ｄｌに示すよ５に金属膜２２と半導体膜２４の側面
に、絶縁膜２６からなる側壁絶縁膜２８が形成される。In the anisotropic ion etching method, the ions that cause the etching reaction react while being accelerated in the direction perpendicular to the substrate 12. Therefore, the insulating film 26 shown in FIG. and the first
As shown in FIG. 5, a sidewall insulating film 28 made of an insulating film 26 is formed on the side surfaces of the metal film 22 and the semiconductor film 24.
なお透明導電膜１４からなる走査電極６４側面にも絶縁
膜が形成される。Note that an insulating film is also formed on the side surface of the scanning electrode 64 made of the transparent conductive film 14.
次洗第１図（ｅ）に示すように、全面に導電膜６０トシ
てモリブデンをスパッタリング法により、厚さ１１００
ｎ〜２０００ｎｍ形成する。モリブデン以外に導電膜６
０としてはモリブデンシリサイド、アルミニウム、ある
いはシリコンを添加したアルミニウムも使用可能である
。その後感光性樹脂を全面に形成し、マスクを用いて露
光、および現像を行ない第３のホトレジスト２０を形成
する。Next, as shown in Fig. 1(e), a conductive film of 60 layers was deposited on the entire surface and molybdenum was sputtered to a thickness of 1100 mm.
A thickness of n to 2000 nm is formed. Conductive film 6 other than molybdenum
As zero, molybdenum silicide, aluminum, or aluminum added with silicon can also be used. Thereafter, a photosensitive resin is formed on the entire surface, exposed to light using a mask, and developed to form a third photoresist 20.
この第３のホトレジスト２０の平面パターン形状は、第
２図の一点鎖線４８で示す。The planar pattern shape of this third photoresist 20 is indicated by a dashed-dotted line 48 in FIG.
次に第１図（ｆｌに示すように、第３のホトレジスト２
０をエツチングのマスクとして導電＠６０をリン酸と硝
酸との混合溶液によりエツチングし、半導体膜２４と走
査電極３４、および第２図に示す半導体膜２４と画素電
極６８とを接続する配線６２を形成する。さらにこの第
３のホトレジスト２０をエツチングのマスクとして、反
応性イオンエツチング装置で四フッ化炭素と酸素との混
合ガスを用いて、第３のホトレジスト２０に覆われてい
ない領域、すなわち第３のホトレジスト２０開口部の半
導体膜２４と金属膜２２とをエツチングして除去する。Next, as shown in FIG.
Using 0 as an etching mask, the conductive layer 60 is etched with a mixed solution of phosphoric acid and nitric acid to form the wiring 62 connecting the semiconductor film 24 and the scanning electrode 34, and the semiconductor film 24 and the pixel electrode 68 shown in FIG. Form. Furthermore, using this third photoresist 20 as an etching mask, a mixed gas of carbon tetrafluoride and oxygen is used in a reactive ion etching apparatus to remove the area not covered with the third photoresist 20, that is, the third photoresist. The semiconductor film 24 and metal film 22 in the opening 20 are removed by etching.
なお第２図に示すように、走査電極６４は配線抵抗を低
くするため、透明導電膜と導電膜との積層構造になって
いる。As shown in FIG. 2, the scanning electrode 64 has a laminated structure of a transparent conductive film and a conductive film in order to reduce wiring resistance.
液晶表示体は、上述の素子基板と対向基板の両基板に一
般的な手法により液晶配向処理を行ない、２枚の基板を
貼り合せた後、液晶を注入して完成する。A liquid crystal display body is completed by subjecting both the above-described element substrate and counter substrate to liquid crystal alignment treatment using a general method, bonding the two substrates together, and then injecting liquid crystal.
以上の説明で明ら力・なよ５に、半導体膜と金属膜との
側面に自己整合によって、絶縁膜からなる側壁絶縁膜を
形成することにより金属膜と配線との絶縁を行なうこと
ができる。したがって半導体膜下面の全面に遮光性を有
する金属膜を形成することが可能となり、基板下面から
の透過光がこの金属膜によって遮断されて半導体膜に照
射されず、光照射に起因するリーク電流発生が防止され
液晶表示装置の表示画像品位が向上する。さらに半導体
膜と金属膜との側面、および走査電極と画素電極との側
面に側壁絶縁膜が形成されるため、段差が緩和されて半
導体膜と金属膜との段差部、および走査電極段差部と画
素電極段差部での配線の断線を防止する効果を有する。From the above explanation, it is clear that insulation between the metal film and the wiring can be achieved by forming a sidewall insulating film made of an insulating film by self-alignment on the side surfaces of the semiconductor film and the metal film. . Therefore, it is possible to form a metal film with light-shielding properties on the entire bottom surface of the semiconductor film, and the light transmitted from the bottom surface of the substrate is blocked by this metal film and is not irradiated onto the semiconductor film, resulting in the generation of leakage current due to light irradiation. This improves the display image quality of the liquid crystal display device. Furthermore, since a sidewall insulating film is formed on the side surfaces of the semiconductor film and the metal film, and on the side surfaces of the scanning electrode and the pixel electrode, the level difference is reduced and the level difference between the semiconductor film and the metal film and the scanning electrode level difference are reduced. This has the effect of preventing wire breakage at the pixel electrode step portion.
さらにそのうえ半導体膜の側面に側壁絶縁膜が形成され
るため、従来例に比較して側面部における配線を介して
の、ｐｎ接合のリーク電流を低減することができる効果
をもつ。Furthermore, since the sidewall insulating film is formed on the side surface of the semiconductor film, it has the effect of reducing the leakage current of the pn junction via the wiring on the side surface compared to the conventional example.
第１図（ａｌ〜げ）は本発明におけるアクティブマトリ
ックス素子の製造方法を工程Ｊ＠に示す断面図、第２図
は本発明におけるアクティブマトリックス素子を示す平
面図、第３図はダイオードリングを用いたアクティブマ
トリックス素子を示す回路図。
第４図は従来例におけるアクティブマトリックス素子を
示す断面図である。
１４・・・・・・透明導電膜、２２・・・・・・金属膜
、２４・・・・・・半導体膜、２６・・・・・・絶縁膜
、２８・・・・・・側壁絶縁膜、３０・・・・・・導電
膜、６２・・・・・・配線、３４・・・１４、透明庫電
腫
２２、金属膜
２４、半環体ル更
２６、他Ｒ展
２８、便ｊ壁肥縁漂
３０、導電膜
３２、配線
第１＠
！FIG. 1 (al-ge) is a cross-sectional view showing the method for manufacturing an active matrix element according to the present invention in step J@, FIG. 2 is a plan view showing the active matrix element according to the present invention, and FIG. FIG. 2 is a circuit diagram showing an active matrix element. FIG. 4 is a sectional view showing a conventional active matrix element. 14...Transparent conductive film, 22...Metal film, 24...Semiconductor film, 26...Insulating film, 28...Side wall insulation Membrane, 30... Conductive film, 62... Wiring, 34...14, Transparent cell electroma 22, Metal film 24, Hemicyclic body 26, Other R exhibition 28, Stool j Wall thickening 30, conductive film 32, wiring 1st @!
Claims (1)
１のホトレジストを形成し該第１のホトレジストをマス
クにして前記透明導電膜をエッチングして走査電極と画
素電極とを形成する工程と、全面に金属膜と半導体膜と
を順次形成し該半導体膜上に第２のホトレジストを形成
する工程と、該第２のホトレジストをマスクにして前記
半導体膜と金属膜とを所定形状にエッチングする工程と
、全面に絶縁膜を形成する工程と、該絶縁膜を異方性イ
オンエッチングによりエッチングして前記半導体膜と金
属膜との側面に前記絶縁膜からなる側壁絶縁膜を形成す
る工程と、全面に導電膜を形成し該導電膜上に第３のホ
トレジストを形成し該第３のホトレジストをマスクにし
て前記導電膜をエッチングして配線を形成し前記第３の
ホトレジスト開口部の前記半導体膜と金属膜とを除去す
る工程とを有することを特徴とするアクティブマトリッ
クス素子の製造方法。A transparent conductive film is formed on the entire surface of the substrate, a first photoresist is formed on the transparent conductive film, and the transparent conductive film is etched using the first photoresist as a mask to form a scanning electrode and a pixel electrode. a step of sequentially forming a metal film and a semiconductor film on the entire surface and forming a second photoresist on the semiconductor film; and forming the semiconductor film and the metal film into a predetermined shape using the second photoresist as a mask. a step of etching, a step of forming an insulating film on the entire surface, and a step of etching the insulating film by anisotropic ion etching to form a sidewall insulating film made of the insulating film on the side surface of the semiconductor film and metal film. A conductive film is formed on the entire surface, a third photoresist is formed on the conductive film, and the conductive film is etched using the third photoresist as a mask to form wiring. 1. A method of manufacturing an active matrix element, comprising the step of removing a semiconductor film and a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63159968A JPH028819A (en) | 1988-06-28 | 1988-06-28 | Manufacture of active matrix element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63159968A JPH028819A (en) | 1988-06-28 | 1988-06-28 | Manufacture of active matrix element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH028819A true JPH028819A (en) | 1990-01-12 |
Family
ID=15705106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63159968A Pending JPH028819A (en) | 1988-06-28 | 1988-06-28 | Manufacture of active matrix element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH028819A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04284951A (en) * | 1991-03-13 | 1992-10-09 | Nippon Steel Corp | Pouring method in belt type continuous casting |
| US5238861A (en) * | 1990-05-15 | 1993-08-24 | France Telecom Etablissement Autonome De Droit Public(Centre National D'etudes Des Telecommunications) | Method for manufacturing an active matrix display screen with storage capacitors |
-
1988
- 1988-06-28 JP JP63159968A patent/JPH028819A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5238861A (en) * | 1990-05-15 | 1993-08-24 | France Telecom Etablissement Autonome De Droit Public(Centre National D'etudes Des Telecommunications) | Method for manufacturing an active matrix display screen with storage capacitors |
| JPH04284951A (en) * | 1991-03-13 | 1992-10-09 | Nippon Steel Corp | Pouring method in belt type continuous casting |
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