JPH0346630A - Production of thin-film diode - Google Patents

Abstract

PURPOSE:To decreases the number of laminations to 6 layers and provide the lower cost and higher yield by the shortening of the process for production by forming the thin-film diodes connected in series with diodes in two stages by the simple method of a patterning stage using 3 sheets of resists. CONSTITUTION:A transparent electrode layer 14, light shielding film 16, 1st semiconductor layer 18, and 1st conductive layer 2 on a substrate are patterned by using the 1st resist 30 and a 2nd semiconductor layer 22 is formed over the entire surface. The 2nd semiconductor layer 22 is patterned by using the 2nd resist 32. The light shielding film 16, 1st semiconductor layer 18 and 1st conductive layer 20 in the aperture of the 2nd resist 32 are removed and a 2nd conductive layer 24 is formed over the entire surface. The 2nd conductive layer 24 is patterned by using the 3rd resist 34. The unnecessary light shielding film, 1st conductive layer, 1st conductive layer, and 2nd semiconductor layer in the aperture of the 3rd resist 34 are then removed. The reproducibility and stability are improved and the lower cost and the higher yield are obtd. by the simple method of patterning using 3 times of the resist and the six layers in the entire stage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] In recent years, the technology of liquid crystal display devices has made remarkable progress, and they are now widely used as flat panel displays.

In particular, the active mask (IJ) system, in which a switching element is arranged and driven for each pixel, has high display performance and is capable of high-density, large-capacity display, so it is being used in televisions, information terminals, and the like.

The present invention relates to a method of manufacturing a thin film diode used as a switching element of the above active matrix type liquid crystal display element.

[Conventional technology]

2. Description of the Related Art Active matrix liquid crystal display devices using thin film diodes (for example, amorphous silicon p1n diodes), which are two-terminal devices, have been proposed as switching elements for active matrix liquid crystal display devices. As shown in FIG. 4, a row electrode 66 and a pixel electrode are provided on one substrate, and a plurality of diodes 42 are connected in a ring shape between the row electrode 66 and the pixel electrode. A column electrode 68 is provided on the other substrate, a liquid crystal 44 is sealed between the two substrates, and the diode 42 is controlled to display an image.
ng (hereinafter referred to as DR method).

The threshold voltage vth (hereinafter referred to as vth) is the most important value as one of the values indicating the switching performance of the diode 42, and if the above-mentioned vth is low, sufficient liquid crystal driving ability cannot be obtained and high image quality of the liquid crystal display cannot be achieved. Have difficulty. In particular, in the above-mentioned amorphous silicon Luminium diode, the 5 vth
The stability is extremely good, but when Vth is 0.5V to 0
, 6■, which is so low that sufficient liquid crystal driving ability cannot be obtained with the one-stage DR system using the diode 42 shown in FIG. Therefore, when using a thin film diode with excellent Vth stability, such as an amorphous silicon Luminium n diode, as a switching element, it is better to connect diodes 42 in series in multiple stages as shown in Figure 5 (a) and (b). It is possible to obtain vth. FIG. 5(a) shows the DR method when two stages of diodes 42 are connected in series.
Figure (bJ) is a DR system in which four stages of diodes 42 are connected in series.

FIG. 3 shows a structural cross-sectional view of a conventional thin film diode in which two stages of diodes 42 shown in FIG. 5(a) are connected in series. A transparent electrode layer 14 is formed on the entire surface of the substrate 12.
The resist is patterned to form row electrodes 66 and pixel electrodes 40 made of transparent electrode layers. Next, a light shielding layer 16, a first semiconductor layer 18, a first conductive layer 20 and a second conductive layer are formed on the entire surface.
A semiconductor layer 22 and a bonding layer 26 are sequentially formed and patterned on the pixel electrode 40 using a second resist. At this time, it should be noted that etching is performed using a second resist with a five-layer structure consisting of a light-shielding layer 16, a first semiconductor layer 18, a first conductive layer 20, a second semiconductor layer 22, and a bonding layer 26. Therefore, an optimal etching method and etching conditions are required for each layer. If the etching method and etching conditions are not optimized, the cross-sectional shape of the five-layer structure using the second resist will not have the same shape as shown in Figure 3, and there will be differences in pattern dimensions for each layer. , unevenness occurs on the side surface of the five-layer structure. When this unevenness occurs, the step coverage of the interlayer insulating layer 28 formed in a subsequent process is significantly deteriorated. The first semiconductor layer 18 and the second semiconductor layer 22 are made of amorphous silicon or lanali, and have a pin conduction type. The light-shielding layer 16 provided between the pixel electrode 40 and the first semiconductor layer 18 causes photoactivation in the first semiconductor layer 18 when the first semiconductor layer 18 is irradiated with transmitted light from the bottom surface of the substrate 12. This is installed to prevent current generation and deterioration of the diode's switching performance. The first conductive layer 20 provided between the first semiconductor layer 18 and the second semiconductor layer 220 prevents reverse junction between the n layer of the first semiconductor layer 18 and the p layer of the second semiconductor layer 22. First semiconductor layer 18 and second semiconductor layer 2
This is installed to improve the bondability with 2. Further, the bonding layer 26 provided on the second semiconductor layer 22 is formed by etching the interlayer insulating layer 28 when patterning the interlayer insulating layer 28 to be formed in a later step using a third resist. This is provided in order to prevent deterioration of the surface of 22 and to improve the bonding property between the second semiconductor layer 22 and the second conductive layer 24 that will be formed in a later step. Next, an interlayer insulating layer 28 is formed over the entire surface and patterned using a third resist. This interlayer insulating layer 28 is provided to prevent the second conductive layer 24 formed in a later step from being electrically short-circuited with the pixel electrode 40. When patterning the interlayer insulating layer 28 using the third resist, the etching shape of the interlayer insulating layer 28 at the opening on the bonding layer 26 is important, and the etching shape is formed into a reverse tapered shape by over-etching. In this case, the step coverage of the second conductive layer 24 formed in a subsequent process is significantly deteriorated. Next, a second conductive layer 24 is formed on the entire surface and patterned using a fourth resist, and the second conductive layer 24 connects the second semiconductor layer 22 and the row electrode 66 via the bonding layer 26. Perform wiring. At this time, as is clear from the above explanation and FIG. 3, the second conductive layer 24 needs sufficient step coverage on the side surface of the seven layers laminated, and the formation conditions for the second conductive layer 24 are sufficient. Caution is required. As described above, the thin film diodes connected in series in two stages shown in FIG. 3 can be formed into a diode element by four resist patterning steps and a laminated structure of as many as eight layers.

[Problem to be solved by the invention]

However, the manufacturing process of the thin film diode connected in series in two stages in the conventional example shown in FIG. 3 has the following problems.

(a) Using a second resist, the light-shielding layer 16, the first semiconductor layer 18, the first conductive layer 20, and the second
When patterning the five-layer structure shown in FIG. 3, consisting of the semiconductor layer 22 and the bonding layer 26, each layer requires an optimal etching method and etching conditions, and the etching process is extremely long. Furthermore, it is difficult to optimize the cross-sectional shape of the five-layer structure.

(b) If the cross-sectional shape of the five-layer structure described in (a) is not optimized, unevenness is likely to occur on the side surface of the five-layer structure due to the difference in pattern dimensions for each layer, and the step coverage of the interlayer insulating layer 28 may deteriorate. It deteriorates significantly and cannot function as interlayer insulation.

←→ When patterning the interlayer insulating layer 28 using the third resist, the interlayer insulating layer 28 in the opening on the bonding layer 26
If it is difficult to optimize the etching and the overetching time is long, the etching shape of the opening on the bonding layer 26 tends to be reverse tapered, and the step coverage of the second conductive layer 24 at the opening is It deteriorates significantly and easily breaks.

Furthermore, if the overetching time is short, a portion of the interlayer insulating layer 28 remains in the opening, and the bonding between the bonding layer 26 and the second conductive layer 24 becomes insufficient, resulting in a loss of electrical contact and a tendency to disconnect. .

2) The second conductive layer 24 is required to have sufficient step coverage on the side surface on which it is laminated as shown in FIG. The conductive layer 24 is made sufficiently thicker than the total thickness of the seven layers (approximately 2
(at least twice as long), the process becomes longer, and material costs are expected to increase.In addition, the increase in internal stress due to the increase in film thickness cannot be ignored, and peeling is likely to occur.

(Hane) The manufacturing process is long due to the patterning process using resist four times in the entire manufacturing process and the laminated structure of eight layers.
Furthermore, due to the problems described in (a) to (a) above, high yield, good reproducibility, stability, and cost reduction cannot be expected.

By solving the problems mentioned in (A) to (2) above, the manufacturing process is short, the number of layers in the entire manufacturing process is small, low cost, high yield can be obtained, and the manufacturing process has excellent stability and reproducibility. It is an object of the present invention to provide a method for manufacturing a thin film diode.

[Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a thin film diode of the present invention includes forming a transparent electrode layer, a light shielding layer, a first semiconductor layer, and a first conductive layer on the entire surface of a substrate. A step of sequentially forming a transparent electrode layer, a light-shielding layer, a first semiconductor layer, and a first conductive layer using a first resist, and forming a second semiconductor layer on the entire surface and patterning the transparent electrode layer using a first resist. a step of patterning the second semiconductor layer using a resist, a step of removing the light-shielding layer, the first semiconductor layer, and the first conductive layer in the opening of the second resist; and a step of patterning the second semiconductor layer over the entire surface. a step of forming a conductive layer and turning the second conductive layer using a third resist; It is characterized by a step of removing the second semiconductor layer, and is a simple manufacturing method with three resist patterning steps and six layers in total, with excellent reproducibility and stability, low cost, and high It becomes possible to provide thin film diodes with high yield.

〔Example〕

The present invention will be described in detail below using the drawings.

FIGS. 1(a) to (fl) are cross-sectional views showing the manufacturing method of thin film diodes connected in two rows in the DR method used in the present invention in order of process, and FIG. 2 is a plan view showing the thin film diodes in the present invention. .In addition, Fig. 1 is similar to Fig. 2.
A cross section is shown. This will be explained below using FIGS. 1 and 2.

First, as shown in FIG. 1 (aJ), indium tin oxide (ITO) is formed as a transparent electrode layer 14 to a thickness of 100 nm to 200 nm on a substrate 12 made of transparent glass by sputtering or vacuum evaporation. Chromium is sequentially formed to a thickness of 50 nm to 1100 nm as the light shielding layer 16. Thereafter, a first semiconductor layer 18 made of amorphous silicon is formed by 30 nm by Glazma chemical vapor deposition.
It is formed to a thickness of 0 nm to 500 nm, and then tantalum is formed to a thickness of 20 nm to 50 nm as the first conductive layer 20 by sputtering or vacuum evaporation. The transparent electrode layer 14 and the light shielding layer 16 may be formed by a continuous sputtering method or a continuous vacuum evaporation method using the same vacuum chamber. As the light shielding layer 16,
As mentioned above, it is provided to prevent incident light from the substrate 12 side, so in addition to the chromium used in this example, tantalum, titanium, tungsten, aluminum, or a composite alloy containing these materials as main components, or a composite alloy of these materials is used. A similar effect can be obtained by using a laminated film of materials. In addition, methods for forming the first semiconductor layer 18 and the second semiconductor layer 22, which will be described later in the step of FIG. Furthermore, the first semiconductor layer 1
8 and the second semiconductor layer 22, the conduction type is p from the light shielding layer 16 side.
It has a pin diode structure of type, l type, that is, an intrinsic semiconductor, and n type. The conduction types of the first semiconductor layer 18 and the second semiconductor layer 22 include a pin structure, a nip structure, and a nip structure.
, pn, or np tank structure, any structure may be used as long as it has a rectifying characteristic.

The first conductive layer 20 prevents reverse junction between the surface layer of the first semiconductor layer 18, that is, the n layer, and the bottom layer, that is, the p layer of the second semiconductor layer 22, and layer 2
This is provided for the purpose of improving the bondability with 2. Therefore, the first conductive layer 20 may be made of chromium, titanium, tungsten, molybdenum, or an alloy of molybdenum and silicon other than tantalum used in this embodiment. Next, using the first resist 60, the transparent electrode layer 14, the light shielding layer 16, the first semiconductor layer 18, and the first conductive layer 20 are etched and patterned as shown in FIG. .

The shape of the planar pattern from the resist 60 is shown by the solid line 46 in FIG. At this time, the row electrode 66 made of the transparent electrode layer 14 and the pixel electrode 40 are simultaneously formed using the first resist 60. Further, the first stage thin film diode is formed in the above process. Patterning using the first resist 60 is performed by a photoresist process using a normal photosensitive resin, and the transparent electrode layer 1 made of indium tin oxide is
A mixed solution of ferric chloride and hydrochloric acid was used for etching No. 4, and a mixed aqueous solution of cerium ammonium nitrate and perchloric acid was used for etching the light shielding layer 16 made of chromium. Furthermore, the first semiconductor layer 18 and the first conductive layer 20 made of amorphous silicon are etched using a reactive ion etching method using a mixed gas of carbon tetrafluoride and oxygen as an etching gas. Two layers, the conductive layer 20 and the first semiconductor layer 18, were etched successively.

The first semiconductor layer 18 and the first conductive layer 20 may be etched by a dry etching method such as a sputter etching method, an ion beam etching method, an electron cyclotron resonance etching method, or a wet etching method using a reaction solution. good.

Next, as shown in FIG. 1(b), amorphous silicon is formed on the entire surface as a 20th semiconductor layer 22 with a thickness of 1.50 nm to 500 nm by the plasma chemical vapor deposition method described above. The second semiconductor layer 22 is patterned using the second resist 62. The second semiconductor layer 22 was etched using the reactive ion etching method using the aforementioned mixed gas of carbon tetrafluoride and oxygen as the etching gas. The planar pattern shape of the second resist 62 is indicated by a broken line 48 in FIG. As is clear from FIG. 1 (1)), the second semiconductor layer 22 has a structure that covers the entire thin film diode on the pixel electrode 40, and the second semiconductor layer 22 also has the function of interlayer insulation. ing. Therefore, it is possible to omit the interlayer insulating layer 28 in the conventional thin film diode described in FIG. Further, the short circuit between the light shielding layer 16 and the first conductive layer 20 due to the p layer of the second semiconductor layer 22 in contact with the side wall portion of the first semiconductor layer 18 is caused by the doping concentration of the p layer of the second semiconductor layer 22 and By optimizing the film thickness, it becomes completely negligible.

Next, as shown in FIG. 1C, the unnecessary light shielding layer 16 and the first semiconductor layer 18 formed on the row electrode 66 and the pixel electrode 40 in the opening of the second resist 62 are removed. The conductive layer is removed using the second resist 62 by etching as described in the step of FIG. 1(a). Figure 1 (bl
Since the reactive ion etching method is used to etch the second semiconductor layer 22 shown in FIG. It may also be performed by consecutively etching three layers.

Next, as shown in FIG. 1(d), a second conductive layer 24 of molybdenum is formed with a thickness of 400 nm to 600 nm on the entire surface by sputtering or vacuum evaporation, and a third resist 64 is formed. The row electrodes 66 and the pixel electrodes 40 are wired by patterning. The planar pattern shape of the third resist 64 is shown by the dashed-dotted line 50 in FIG. This second conductive layer 24 was etched using a mixed solution of phosphoric acid, acetic acid, and nitric acid. As is clear from FIG. 1(d), there is no interlayer insulating layer 28 shown in FIG. 3, and the stepped portion on the pixel electrode 40 and the stepped portion of the second semiconductor layer 240 have an independent structure. The step coverage of the conductive layer 24 is very good. Furthermore, by omitting the interlayer insulating layer 28, damage caused by etching of the interlayer insulating layer 28 onto the surface of the second semiconductor layer 22 is eliminated, and the second semiconductor layer 22 is etched.
The bonding property between the semiconductor layer 22 and the second conductive layer 24 is good, and the bonding layer 26 described in FIG. 3 is not required. In addition to molybdenum, molybdenum silicide, aluminum, or aluminum added with silicon can also be used as the second conductive layer 24.

Next, as shown in FIG. 1(c), a third resist 34 is used to remove unnecessary light shielding layer 16 within the opening of this third resist 34.
Then, the first semiconductor layer 18, the first conductive layer 20, and the second semiconductor layer 22 are removed. Second semiconductor layer 2 after the removal
The planar pattern of No. 2 is indicated by diagonal lines 52 in FIG. Note that the first
The planar pattern of the semiconductor layer 18 is indicated by diagonal lines 54. 1st
As described in the steps of FIGS. (b) and (C), the first semiconductor layer 18, the second conductive layer 20, and the second semiconductor layer 22 are etched using reactive ions using the same reaction chamber. An etching method may also be used.

Next, as shown in FIG. 1 (fl), the third resist 64 is removed to complete the thin film diode according to the present invention.As shown in FIG. It has a laminated structure of layer 14 and second conductive layer 24.

Note that in order to form a DR in which four stages of diodes 42 are connected in series as shown in FIG. It is possible depending on the situation.

The element substrate and counter substrate formed by the above steps are subjected to liquid crystal alignment treatment using a normal method, and after the two substrates are bonded together, liquid crystal is injected and sealed to form a DR active matrix liquid crystal display panel. is completed.

〔Effect of the invention〕

As is clear from the above description, according to the method for manufacturing a thin film diode of the present invention, a thin film diode in which diodes are connected in series in two stages can be formed by a simple patterning process using three resists. The number of laminations in the entire manufacturing process is also very small at 6 layers. Therefore, it is easy to reduce manufacturing costs and increase yield by shortening the manufacturing process. Furthermore, in patterning using the first resist, since a four-layer structure consisting of a transparent electrode layer, a light-shielding layer, a first semiconductor layer, and a first conductive layer is etched, the five-layer structure described in the conventional example, especially the film thickness. Compared to a structure in which thick first and second semiconductor layers are laminated, it is easier to optimize the etching method and etching conditions for each layer, and it is easier to obtain a good cross-sectional shape. Furthermore, due to the above effect, the step coverage of the second semiconductor layer formed on the first conductive layer is also extremely good, and the function of the second semiconductor layer as an interlayer insulation is further improved. In addition, in patterning using the second resist, the second
It is extremely easy to etch only the semiconductor layer.

Furthermore, since the structure does not include the interlayer insulating layer in the conventional example, there is no disconnection in the second conductive layer due to etching of the interlayer insulating layer.

Furthermore, since there is no interlayer insulating layer and the step portion on the pixel electrode and the step portion of the second semiconductor layer are independent structures, and the thickness of the step portion is thin, the step cover of the second conductive layer is The properties are very good, and there is almost no disconnection in the second conductive layer.

Due to the above-described effects, the manufacturing process of the thin film diode according to the present invention has excellent stability and reproducibility.

It is clear that the method for manufacturing a thin film diode according to the present invention is effective not only for the DR active matrix liquid crystal display element of this example, but also for other display elements using thin film diodes and thin film diode applied elements. be.

[Brief explanation of drawings]

Figures 1 (at to f) are cross-sectional views showing the manufacturing method of a thin film diode according to the present invention in order of steps, Figure 2 is a plan view showing a thin film diode according to the present invention, and Figure 3 is a thin film diode in a conventional example. Figure 4 is a cross-sectional view, and Figure 4 is a circuit diagram showing a thin film diode using the diode ring method.
Figure (a) is a circuit diagram showing a diode ring in which diodes are connected in series in two stages, and Figure 5 (bl is a circuit diagram showing a diode ring in which diodes are connected in series in four stages.) 14... Transparent electrode layer , 16... Light shielding layer, 18... First semiconductor layer, 20... First conductive layer, 22... Second semiconductor layer, 24... Second conductive layer, 60... First resist, 62... Second resist, 64... Third resist. Figure 2 U 6 0

Claims (1)

[Claims] A transparent electrode layer, a light shielding layer, a first semiconductor layer, and a first conductive layer are sequentially formed on the entire surface of the substrate, and a first resist is used to form the transparent electrode layer, the light shielding layer, the first semiconductor layer, and the first conductive layer. forming a second semiconductor layer over the entire surface and patterning the second semiconductor layer using a second resist; a step of removing the light shielding layer, the first semiconductor layer, and the first conductive layer; a step of forming a second conductive layer on the entire surface and patterning the second conductive layer using a third resist; A method for manufacturing a thin film diode, comprising the step of removing the light shielding layer, the first semiconductor layer, the first conductive layer, and the second semiconductor layer within the opening of the third resist.