JPH01220328A - Semiconductor electron emission element - Google Patents

Semiconductor electron emission element

Info

Publication number
JPH01220328A
JPH01220328A JP63045471A JP4547188A JPH01220328A JP H01220328 A JPH01220328 A JP H01220328A JP 63045471 A JP63045471 A JP 63045471A JP 4547188 A JP4547188 A JP 4547188A JP H01220328 A JPH01220328 A JP H01220328A
Authority
JP
Japan
Prior art keywords
semiconductor
electron
type semiconductor
schottky electrode
schottky
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63045471A
Other languages
Japanese (ja)
Other versions
JP2788243B2 (en
Inventor
Takeo Tsukamoto
健夫 塚本
Toshihiko Takeda
俊彦 武田
Haruto Ono
治人 小野
Nobuo Watanabe
信男 渡辺
Masahiko Okunuki
昌彦 奥貫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP4547188A priority Critical patent/JP2788243B2/en
Priority to EP89301863A priority patent/EP0331373B1/en
Priority to DE68918134T priority patent/DE68918134T2/en
Publication of JPH01220328A publication Critical patent/JPH01220328A/en
Priority to US07/807,613 priority patent/US5138402A/en
Application granted granted Critical
Publication of JP2788243B2 publication Critical patent/JP2788243B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/308Semiconductor cathodes, e.g. cathodes with PN junction layers

Abstract

PURPOSE:To stabilize an electron emission by making the impurity density of the P type semiconductor to which a Schottky electrode is joined to be in the density range in which an avalanche breakdown is made to occur, and impressing reverse bias voltage to the Schottky electrode and the P type semiconductor. CONSTITUTION:A Schottky diode is formed with a Schottky electrode 5 joined to a P type semiconductor 1, and the joining part of the diode is reversely biased. This enables a vacuum level to a lower energy level than the conduction band of the P type semiconductor, and a large energy difference can be obtained. Moreover an avalanche amplification is made to occur in this condition. This enables a much electron to be produced, and the emission efficiency of the electron can be improved. The impurity density of a semiconductor used is made in the density range in which an avalanche breakdown occurs. And the material having a low work function is used to a Schottky electrode material.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体電子放出素子に係り、特にアバランシェ
増幅を起こさせ、ホット化した電子を放出させる半導体
電子放出素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor electron-emitting device, and more particularly to a semiconductor electron-emitting device that causes avalanche amplification and emits hot electrons.

〔従来の技術] 従来、半導体電子放出素子のうち、アバランシェ増幅を
用いたものは、米国特許第4259878号および米国
特許第4303130号に記載されているように、p型
半導体層とn型半導体層が接するように形成して、ダイ
オード構造とし、このダイオードの両端に逆バイアス電
圧をかけてアバランシェ増幅を起して電子をホット化し
、セシウム等を付着させて表面の仕事関数を低下させた
n型半導体層表面より電子が放出されるように構成され
たものが知られている。
[Prior Art] Conventionally, among semiconductor electron-emitting devices, those using avalanche amplification have a p-type semiconductor layer and an n-type semiconductor layer, as described in U.S. Pat. No. 4,259,878 and U.S. Pat. No. 4,303,130. A reverse bias voltage is applied to both ends of this diode to cause avalanche amplification to make the electrons hot, and cesium etc. are deposited to lower the work function of the surface. Some devices are known that are configured so that electrons are emitted from the surface of the semiconductor layer.

[発明が解決しようとする問題点] 上記従来例では、電子放出部の仕事関数を低下させるた
めに、電子放出部表面にセシウム及びセシウム−酸素化
合物を形成させているが、上記セシウム材料は化学的に
極めて活性なため、(1)超高真空(〜lO″″’ t
arr以上)で使用しなければ安定な動作をしない、(
2)寿命が真空度によって変化する。(3)効率が真空
度によって変化をする等の問題点があった。またpn界
面で生成されたホットエレクトロンは、n型半導体層を
通過するときに散乱によりエネルギーを失うために、n
型半導体層は極めて薄く作成(200Å以下)する必要
がある。このため、極めて薄いn9半導体層を均一、高
濃度、かつ低欠陥で作成するには半導体製造プロセス上
の問題点が多数存在し、素子を安定に作製することは困
難であった。
[Problems to be Solved by the Invention] In the above-mentioned conventional example, cesium and a cesium-oxygen compound are formed on the surface of the electron-emitting region in order to lower the work function of the electron-emitting region. (1) Ultra-high vacuum (~lO""'t
arr or higher), it will not operate stably unless it is used at (
2) The lifespan changes depending on the degree of vacuum. (3) There were problems such as efficiency changing depending on the degree of vacuum. In addition, hot electrons generated at the p-n interface lose energy due to scattering when passing through the n-type semiconductor layer, so
The type semiconductor layer needs to be made extremely thin (200 Å or less). For this reason, there are many problems in the semiconductor manufacturing process to create an extremely thin n9 semiconductor layer with uniformity, high concentration, and low defects, and it has been difficult to stably manufacture devices.

[fi’f点を解決するための手段] 本発明の半導体電子放出素子は、ショットキー電極が接
合されたp型半導体の不純物濃度をアバランシェ降伏を
生じさせるような濃度範囲とし、前記ショットキー電極
と前記p型半導体とに逆バイアス電圧を印加して、前記
ショットキー電極から電子を放出させたことを特徴とす
る。
[Means for solving the fi'f point] In the semiconductor electron-emitting device of the present invention, the impurity concentration of the p-type semiconductor to which the Schottky electrode is bonded is set in a concentration range that causes avalanche breakdown, and the Schottky electrode A reverse bias voltage is applied to and the p-type semiconductor to cause electrons to be emitted from the Schottky electrode.

[作用] 本発明はP型半導体にショットキー電極を接合してショ
ットキーダイオードを形成し、前記p型半導体の不純物
濃度をアバランシェ降伏を生じさせるような濃度範囲と
して、かかるショットキーダイオードに逆バイアス電圧
を印加させ、アバランシェ増幅を起こすことにより、シ
ョットキー電極の表面から電子を安定して放出させるも
のである。
[Function] The present invention connects a Schottky electrode to a P-type semiconductor to form a Schottky diode, sets the impurity concentration of the P-type semiconductor to a concentration range that causes avalanche breakdown, and reverse biases the Schottky diode. By applying a voltage and causing avalanche amplification, electrons are stably emitted from the surface of the Schottky electrode.

なお・前記ショットキー電極を低仕事関数材料とすれば
、電子放出面の仕事関数が低下するために、電子を安定
して放出させることが可能となる。
Note that if the Schottky electrode is made of a low work function material, the work function of the electron emitting surface will be lowered, making it possible to stably emit electrons.

以下、本発明の半導体電子放出素子の作用についてエネ
ルギーバンド図を用いて説明する。
Hereinafter, the operation of the semiconductor electron-emitting device of the present invention will be explained using an energy band diagram.

第4図は、本発明の半導体電子放出素子における半導体
表面のエネルギーバンド図である。
FIG. 4 is an energy band diagram of the semiconductor surface in the semiconductor electron-emitting device of the present invention.

なお、ここでは、ショットキー電極の構成材料として低
仕事関数材料を用いた場合について説明する。
Note that here, a case will be described in which a low work function material is used as a constituent material of the Schottky electrode.

第4図に示すように、p型半導体(図中、pはp型半導
体部分を示す)および低仕事関数材料(図中、Tは低仕
事関数材料部分を示す)との接合のnnを一逆バイアス
することによって、真空準位EVACをp55半導の伝
導帯ECより低いエネルギー準位とすることができ、大
きなエネルギー差ΔEを得ることができる。この状態で
7バランシ工増幅を起こすことにより、p型半導体にお
いては少数キャリアであった電子を多数生成することが
可能となり、電子の放出効率を高めることが出来る。ま
た空乏層内の電界が電子にエネルギーを与えるために、
電子がホット化されて格子系の温度よりも運動エネルギ
ーが大きくなり1表面の仕事関数よりも大きなポテンシ
ャルを持つ電子が、散乱によってエネルギーを大きく失
すずに表面から飛び出すことが可能となる。
As shown in FIG. 4, the nn of the junction between the p-type semiconductor (in the figure, p indicates the p-type semiconductor part) and the low work function material (in the figure, T indicates the low work function material part) is equal to nn. By applying a reverse bias, the vacuum level EVAC can be set to an energy level lower than the conduction band EC of the p55 semiconductor, and a large energy difference ΔE can be obtained. By performing seven-balance amplification in this state, it becomes possible to generate a large number of electrons, which are minority carriers in a p-type semiconductor, and the electron emission efficiency can be increased. Also, since the electric field in the depletion layer gives energy to the electrons,
When the electrons become hot, their kinetic energy becomes greater than the temperature of the lattice system, and the electrons, which have a potential greater than the work function of one surface, can escape from the surface without losing much energy due to scattering.

本発明の半導体電子放出素子に用いる半導体材料として
は、Si、 Ge、 GaAs、 GaP、 GaAI
P、 GaAsP。
Semiconductor materials used in the semiconductor electron-emitting device of the present invention include Si, Ge, GaAs, GaP, and GaAI.
P, GaAsP.

GaAlAs、 SiC,BPなどがあるが、p型半導
体を形成出来るものであればどのような半導体材料であ
ってもよい0間接型半導体でバンドギヤー2プEが大き
い方が電子放出の効率が良い。
GaAlAs, SiC, BP, etc. can be used, but any semiconductor material can be used as long as it can form a p-type semiconductor.The larger the band gear 2pE of a zero-indirect semiconductor, the better the electron emission efficiency. .

使用する半導体の不純物濃度はアバランシェ降伏が生じ
る濃度範囲であり、この場合、トンネル効果が降伏特性
を支配する限界の濃度で使用することで電子のホット化
に寄与する最大の効率が得られる。従ってトンネル降伏
が生じる濃度以下にドーピングしなければならない。
The impurity concentration of the semiconductor used is within the concentration range where avalanche breakdown occurs, and in this case, maximum efficiency in contributing to hot electrons can be obtained by using the impurity concentration at the limit where the tunnel effect dominates the breakdown characteristics. Therefore, doping must be done to a concentration below that at which tunnel breakdown occurs.

本発明の半導体電子放出素子に用いるショットキー電極
材料は、p型半導体に対して明確にショットキー特性を
示す材料でなければならない、一般に仕事関数φ讐にと
n!2半導体に対するショットキーバリア八イトφBm
との間には直線関係が成り立っているCJze、 27
4p  7B(b) JOHNWILEL & 5ON
S)、 SiではφBn= 0.235φIIIk−0
,55と表わされ、他の半導体の同様に仕事関数が小さ
くなるにつれてφBnは低下する。また一般にp型半導
体に対するシ璽ットキーバリアφBFとφBnとの間に
は、 一φB!Iとなる。前述の式から計算されるように。
The Schottky electrode material used in the semiconductor electron-emitting device of the present invention must be a material that clearly exhibits Schottky characteristics for p-type semiconductors, and generally has a work function φ and n! Schottky barrier eightite φBm for two semiconductors
There is a linear relationship between CJze, 27
4p 7B(b) JOHNWILEL & 5ON
S), for Si, φBn = 0.235φIIIk-0
, 55, and similarly to other semiconductors, as the work function becomes smaller, φBn decreases. In addition, in general, there is one φB! between the shutter barrier φBF and φBn for p-type semiconductors. Becomes I. As calculated from the above formula.

仕事関数の低い材料を用いることでpg!1半導体に対
して良好なショットキーダイオードを作製することが出
来る。このような低仕事関数材料としてはIA、2A、
3A族及びランタノイド系の金属や、IA、2A、3A
族及びランタノイド系のシリサイド、IA、2A、3A
族及びランタノイド系のホウ化物、IA、2A、3A族
及びランタノイド系の炭化物などがあり、これらの材料
の仕事関数は1.5〜4vであり、すべてp型半導体に
対して良好なショットキー電極材料となる。
pg! by using materials with a low work function! A good Schottky diode can be manufactured using one semiconductor. Such low work function materials include IA, 2A,
Group 3A and lanthanide metals, IA, 2A, 3A
Group and lanthanoid silicides, IA, 2A, 3A
These include group and lanthanide borides, IA, 2A, 3A groups and lanthanide carbides, and the work functions of these materials are 1.5 to 4V, making them all good Schottky electrodes for p-type semiconductors. Becomes a material.

以上述べた半導体材料及び半導体濃度、ショットキー電
極材料を用いることで良好なショットキー型の半導体電
子放出素子が作製出来る。
By using the semiconductor material, semiconductor concentration, and Schottky electrode material described above, a good Schottky type semiconductor electron-emitting device can be manufactured.

[実施例] 以下1本発明の実施例について図面を用いて詳細に説明
する。
[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図(A) (B)は1本発明の半導体電子放出素子
の第一実施例の概略的構成図であり、第1図(轟)は平
面図、第1図(B)はA−A部の断面図である。
1(A) and 1(B) are schematic configuration diagrams of a first embodiment of a semiconductor electron-emitting device of the present invention, FIG. 1 (Todoroki) is a plan view, and FIG. 1(B) is an A- It is a sectional view of part A.

第1図(^)(B)に示すように、p型半導体基板1(
本実施例では5t(100))上に3X1016(cm
−3)の不純物濃度を持つpy!!半導体層(以下、p
層と記す)をCVD法によりエピタキシャル成長させて
形成し、フォトリソグラフィーのレジストプロセスによ
り所定の位置のフォトレジストを開口して、Pイオンを
打ち込み、これを7ニールしてn型半導体領域3を形成
し、同様にレジストプロセスにより所定の位置のフォト
レジストを開口して、Bイオンを打ち込み、これを7ニ
ールしてp型半導体領域4を形成する。
As shown in FIG. 1 (^) (B), a p-type semiconductor substrate 1 (
In this example, 3X1016 (cm) on 5t (100)
-3) with an impurity concentration of py! ! Semiconductor layer (hereinafter referred to as p
layer) is formed by epitaxial growth using the CVD method, the photoresist is opened at a predetermined position using a photolithography resist process, P ions are implanted, and this is annealed for 7 times to form an n-type semiconductor region 3. Similarly, the photoresist is opened at a predetermined position by a resist process, B ions are implanted, and the p-type semiconductor region 4 is formed by seven anneals.

次に、ショットキー電極5となる低仕事関数材料トI、
CGd (φWk=3.I V)を100人蒸着し、3
50℃、10分熱処理を行ない、 Gd5izとした。
Next, a low work function material I, which will become the Schottky electrode 5,
CGd (φWk=3.I V) was deposited by 100 people, and 3
Heat treatment was performed at 50°C for 10 minutes to obtain Gd5iz.

この時のバリア八イトφHPは0.7vで良好なショッ
トキーダイオードとなる。さらに5i02及びポリシリ
コンを堆積し、フォトリソグラフィー技術を用いて電子
放出用の開口部を形成し選択エツチングにより、ショッ
トキー電極5上に5iO2J!6を介して、引き出し電
極7を形成した。8はp型半導体基板1の他方にA文を
蒸着したオーミックコンタクト用の電極である。9はシ
ョットキー電極5と電極8との間に逆バイアス電圧Vd
を印加するための電源であり、10はショットキー電極
5と引き出し電極7との間に電圧Vgを印加するための
電源である。
At this time, the barrier eight φHP is 0.7V, making it a good Schottky diode. Furthermore, 5iO2J! and polysilicon are deposited, an opening for electron emission is formed using photolithography, and 5iO2J! is formed on the Schottky electrode 5 by selective etching. 6, an extraction electrode 7 was formed. Reference numeral 8 denotes an electrode for ohmic contact, which is formed by vapor depositing pattern A on the other side of the p-type semiconductor substrate 1. 9 is a reverse bias voltage Vd between the Schottky electrode 5 and the electrode 8.
10 is a power source for applying a voltage Vg between the Schottky electrode 5 and the extraction electrode 7.

上記構成において、逆バイアス電圧Vdをショットキー
ダイオードにかけることにより、p型半導体望城4とシ
ョットキー電極5との界面で7バランシ工増幅が生じ、
生成されたホットエレクトロンは極めて薄く形成された
ショットキー電極5を通り抜けて真空領域にしみ出し、
引き出し電極7による電界によって素子外部へ引き出さ
れる0以上述べたように本実施例によれば、逆バイアス
電圧によってΔEを増大させるため、低仕事関数材料と
してCsやCg−0等に限定されることなく、前述の広
い範囲の材料を選択することが可能となり、より安定し
た材料を用いることができる。また電子放出表面が低仕
事関数材料のショットキー電極となるため表面電極形成
のプロセスが簡略化され、信頼性と安定性のよい半導体
電子放出素子の作製が可能となった。
In the above configuration, by applying the reverse bias voltage Vd to the Schottky diode, 7 balancer amplification occurs at the interface between the p-type semiconductor cell 4 and the Schottky electrode 5,
The generated hot electrons pass through the extremely thin Schottky electrode 5 and leak into the vacuum region.
0 or more drawn out to the outside of the element by the electric field of the extraction electrode 7 As described above, according to this embodiment, since ΔE is increased by the reverse bias voltage, the low work function material is limited to Cs, Cg-0, etc. Therefore, it becomes possible to select materials from the wide range mentioned above, and more stable materials can be used. Furthermore, since the electron emitting surface is a Schottky electrode made of a low work function material, the process of forming the surface electrode is simplified, making it possible to manufacture a semiconductor electron emitting device with good reliability and stability.

第2図は1本発明の半導体電子放出素子の第二実施例の
概略的構成図である。
FIG. 2 is a schematic diagram of a second embodiment of a semiconductor electron-emitting device according to the present invention.

本実施例は、前述した第一実施例の半導体電子放出素子
における素子間でのクロストークを防ぐように構成した
ものである。
The present embodiment is configured to prevent crosstalk between elements in the semiconductor electron-emitting device of the first embodiment described above.

なお本実施例では、電子放出の効率が高くなるようにA
皇0.5Ga0.5Ag(Egが約1.8)が使用され
ている。
In this example, A is set so that the electron emission efficiency is high.
0.5Ga0.5Ag (Eg is about 1.8) is used.

第2図に示すように、半絶縁性のGaAg(100)基
板12aにBeを1018(cm−3)  ドープしな
がら、  All O,5GaO,5AgのPG層13
をエピタキシャル成長させ1次いでBeを1016(c
層″″3)ドープしながらAll G、5Ga0.5A
sの2層2をエビタキャル成長させる。
As shown in FIG. 2, a semi-insulating GaAg (100) substrate 12a is doped with Be at 1018 (cm-3) while a PG layer 13 of All O, 5GaO, 5Ag is formed.
was epitaxially grown and then Be 1016 (c
Layer ""3) All G, 5Ga0.5A while doping
Evitacally grow two layers 2 of s.

次いでFIB (フォーカストイオンビーム)にて、p
◆争層11の不純物濃度が10”(c■−3)になるよ
うにBeを約180 keVで深い層に打ち込み、p層
4の不純物濃度が5X1017(c層−3)になるよう
にBeを約40keVで比較的薄い層に打ち込む、さら
にn層3の不純物濃度が1018(cm−3)になるよ
うにSiを約80 keVで打ち込む、また、プロトン
又はホウ素イオンを200ksV以上の加速電圧で打ち
込んで、素子分離領域12bを形成した。
Next, in FIB (focused ion beam), p
◆Be is implanted into a deep layer at approximately 180 keV so that the impurity concentration of the layer 11 becomes 10" (c-3), and Be is implanted so that the impurity concentration of the p-layer 4 becomes 5×1017 (c-layer-3). Si is implanted into a relatively thin layer at approximately 40 keV, and Si is implanted at approximately 80 keV so that the impurity concentration of the n-layer 3 is 1018 (cm-3). Also, protons or boron ions are implanted at an accelerating voltage of 200 ksV or higher. By implanting, element isolation regions 12b were formed.

次に800℃、30分でアルシン+N2 +H2気流中
で7ニールを行い、適当なマスキングを行なった後に、
BaBB (φWk= 3.4eV)を約100人蒸着
し、温度600℃で30分アニールすることによりショ
ットキー電極5を形成した。第1図(A) (B)に示
した第一実施例の場合と同様に引き出し電極7を形成し
、最後に表面酸化処理を行なって、BaBBの表面の1
/3を酸化してBad(φl1k= 1.11)を形成
した。この時のパリ7ノ\イトφOpは0.9vで良好
なショットキー特性を示し、Siよりも高い電流密度を
とることが可能な半導体電子放出素子となった・ 以上述べた本実施例によれば、素子間を絶縁することで
、基板上に多数の半導体電子放出素子を作製した場合に
素子間のクロストークを減少し、個々の素子を独立駆動
させることが可能となる。
Next, 7 anneals were performed at 800℃ for 30 minutes in arsine + N2 + H2 air flow, and after appropriate masking,
BaBB (φWk=3.4 eV) was deposited by about 100 people and annealed at a temperature of 600° C. for 30 minutes to form a Schottky electrode 5. Extracting electrodes 7 are formed in the same manner as in the first embodiment shown in FIGS.
/3 was oxidized to form Bad (φl1k=1.11). At this time, the Paris 7 node φOp was 0.9 V, which showed good Schottky characteristics, and the semiconductor electron-emitting device was able to take a higher current density than Si. According to this example described above, For example, by insulating the elements, crosstalk between the elements can be reduced when a large number of semiconductor electron-emitting elements are fabricated on a substrate, and each element can be driven independently.

また半導体にワイドギャップ化合物半導体を用い表面に
ホウ化物を用いることで、極めて密着性良好で、仕事関
数の低く、ショットキーのバリアが大きい良好なショッ
トキー電極を形成し、電子放出効率を増大させることが
出来る。
In addition, by using a wide-gap compound semiconductor as the semiconductor and boride on the surface, a Schottky electrode with extremely good adhesion, low work function, and large Schottky barrier is formed, increasing electron emission efficiency. I can do it.

第3図(A) (B)は、上記第二実施例の半導体電子
放出素子をライン状に多数形成した場合の概略的構成図
であり、第3図(A)は平面図、第3図(B)はC−C
a1lの断面図である。
3(A) and 3(B) are schematic configuration diagrams when a large number of semiconductor electron-emitting devices of the second embodiment are formed in a line, and FIG. 3(A) is a plan view, and FIG. 3(A) is a plan view. (B) is C-C
It is a sectional view of a1l.

なお、第3図(A)中のB−8部の断面図は第2図に示
した第二実施例の断面図と同一である。また、半導体電
子放出素子の構成は第二実施例と同様であるので詳細説
明は略すものとする。
Note that the sectional view of section B-8 in FIG. 3(A) is the same as the sectional view of the second embodiment shown in FIG. Further, since the configuration of the semiconductor electron-emitting device is the same as that of the second embodiment, detailed explanation will be omitted.

第3(A)(B)に示すように、半絶縁性ノGaAs(
10G)基板12aにPG層4a〜4h、ショツトキー
電極5a〜5h、素子 オン打ち込みにより作成した。
As shown in Section 3 (A) and (B), semi-insulating GaAs (
10G) PG layers 4a to 4h and Schottky electrodes 5a to 5h were formed on a substrate 12a by device-on implantation.

上記構成において、電子放出部にはlライン状に4a〜
4hで示されるように多数の半導体電子放出素子が形成
されており、5a〜5hで示されるように、多数の電極
に個々に逆バイアスをかけることで1個々の電子源を独
立に制御することが可能である。
In the above configuration, the electron emitting portion has L-line shapes 4a to 4a.
As shown in 4h, a large number of semiconductor electron-emitting devices are formed, and as shown in 5a to 5h, each electron source can be independently controlled by applying a reverse bias to a large number of electrodes. is possible.

[発明の効果] 以上詳細に説明したように1本発明による半導体電子放
出素子によれば,p型半導体にショットキー電極を接合
させてショットキーダイオードを形成し、該ダイオード
の接合部を逆バイアスすることにより,真空準位E’1
lACをp型半導体の伝導帯ECより低いエネルギー準
位とすることができ、従来より大きなエネルギー差ΔE
を容易に得ることが出来る.さらにアバランシェ増幅を
起こさせることにより,p5!半導体中で少数キャリア
である電子を多数発生し放出電流を増大し、さらに薄い
空乏層に高電界をかけて電子をホット化することで,容
易に電子を真空中に引き出すことが出来る。
[Effects of the Invention] As described in detail above, according to the semiconductor electron-emitting device according to the present invention, a Schottky diode is formed by joining a Schottky electrode to a p-type semiconductor, and the junction of the diode is reverse biased. By doing so, the vacuum level E'1
It is possible to set lAC to a lower energy level than the conduction band EC of a p-type semiconductor, resulting in a larger energy difference ΔE than before.
can be easily obtained. By causing further avalanche amplification, p5! By generating a large number of electrons, which are minority carriers, in a semiconductor and increasing the emission current, and then heating the electrons by applying a high electric field to a thin depletion layer, it is possible to easily extract the electrons into a vacuum.

またセシウム等と比較して仕事関数φ社の大きな材料を
ショットキー電極材料として利用できるため、表面材料
の選択範囲が従来より大幅に広くなり、安定した材料を
用いて大きな電−子放出効率を達成することができる。
In addition, since materials with a larger work function than cesium etc. can be used as Schottky electrode materials, the selection range of surface materials is much wider than before, and stable materials can be used to achieve high electron emission efficiency. can be achieved.

また、半導体電子放出素子の作製において,従来からの
半導体形成技術及び薄膜形成技術を利用することが出来
るため,確立した技術を用いて安価に高精度に本発明素
子を作成できるなどの利点が存在する。
In addition, since conventional semiconductor formation technology and thin film formation technology can be used in the production of semiconductor electron-emitting devices, there are advantages such as the ability to fabricate the device of the present invention at low cost and with high precision using established technology. do.

本発明の半導体電子放出素子は,デイスプレィ、EB描
画装置,真空管に好適に用いられ、また電子線プリンタ
ー、メモリー等にも適用が可能である。
The semiconductor electron-emitting device of the present invention is suitably used in displays, EB drawing devices, vacuum tubes, and can also be applied to electron beam printers, memories, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(^)(B)は、本発明の半導体電子放出素子の
第一実施例の概略的構成図である。 第2図は1本発明の半導体電子放出素子の第二実施例の
概略的構成図である。 第3図(A) (B)は、上記第二実施例の半導体電子
放出素子をライン状に多数形成した場合の概略的構成図
である。 第4図は、本発明の半導体電子放出素子における半導体
表面のエネルギーバンド図である。 tap型半導体基板、2,11,13.:P型半導体層
、3:n型半導体領域、 4.4a〜4h:p型半導体領域、 5.5a〜5hニジヨツトキー電極、 6 : 5i02  層、7:引き出し電極。 8ニオ−ミックコンタクト用の電極、 9.10:電源、12 a : GaAs  基板。 12b:素子分離領域。 代理人  弁理士 山 下 積 平 第1図 (B) 第2図 第4図 第3図
FIG. 1(^)(B) is a schematic diagram of a first embodiment of a semiconductor electron-emitting device of the present invention. FIG. 2 is a schematic diagram of a second embodiment of a semiconductor electron-emitting device according to the present invention. FIGS. 3(A) and 3(B) are schematic configuration diagrams when a large number of semiconductor electron-emitting devices of the second embodiment are formed in a line. FIG. 4 is an energy band diagram of the semiconductor surface in the semiconductor electron-emitting device of the present invention. tap type semiconductor substrate, 2, 11, 13. : P type semiconductor layer, 3: n type semiconductor region, 4.4a to 4h: p type semiconductor region, 5.5a to 5h rainbow key electrode, 6: 5i02 layer, 7: extraction electrode. 8. Electrode for niohmic contact, 9.10: Power supply, 12a: GaAs substrate. 12b: Element isolation region. Agent Patent Attorney Seki Yamashita Figure 1 (B) Figure 2 Figure 4 Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)ショットキー電極が接合されたp型半導体の不純
物濃度をアバランシェ降伏を生じさせるような濃度範囲
とし、 前記ショットキー電極と前記p型半導体とに逆バイアス
電圧を印加して、前記ショットキー電極から電子を放出
させた半導体電子放出素子。
(1) The impurity concentration of the p-type semiconductor to which the Schottky electrode is bonded is set to a concentration range that causes avalanche breakdown, and a reverse bias voltage is applied to the Schottky electrode and the p-type semiconductor to form the Schottky electrode. A semiconductor electron-emitting device that emits electrons from an electrode.
(2)前記ショットキー電極が低仕事関数材料からなる
請求項1記載の半導体電子放出素子。
(2) The semiconductor electron-emitting device according to claim 1, wherein the Schottky electrode is made of a low work function material.
(3)前記p型半導体の不純物をマスクレスイオン注入
で注入した請求項1記載の半導体電子放出素子。
(3) The semiconductor electron-emitting device according to claim 1, wherein the p-type semiconductor impurity is implanted by maskless ion implantation.
JP4547188A 1988-02-27 1988-02-27 Semiconductor electron-emitting device and semiconductor electron-emitting device Expired - Lifetime JP2788243B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP4547188A JP2788243B2 (en) 1988-02-27 1988-02-27 Semiconductor electron-emitting device and semiconductor electron-emitting device
EP89301863A EP0331373B1 (en) 1988-02-27 1989-02-24 Semiconductor electron emitting device
DE68918134T DE68918134T2 (en) 1988-02-27 1989-02-24 Semiconductor electron emitting device.
US07/807,613 US5138402A (en) 1988-02-27 1991-12-13 Semiconductor electron emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4547188A JP2788243B2 (en) 1988-02-27 1988-02-27 Semiconductor electron-emitting device and semiconductor electron-emitting device

Publications (2)

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JPH01220328A true JPH01220328A (en) 1989-09-04
JP2788243B2 JP2788243B2 (en) 1998-08-20

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Country Link
US (1) US5138402A (en)
EP (1) EP0331373B1 (en)
JP (1) JP2788243B2 (en)
DE (1) DE68918134T2 (en)

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JPH0395826A (en) * 1989-09-07 1991-04-22 Canon Inc Semiconductor electron emitting element
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US5760417A (en) * 1991-09-13 1998-06-02 Canon Kabushiki Kaisha Semiconductor electron emission device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0395822A (en) * 1989-09-07 1991-04-22 Canon Inc Semiconductor electron emitting element and its manufacture
JPH0395825A (en) * 1989-09-07 1991-04-22 Canon Inc Semiconductor electron emitting element
JPH0395827A (en) * 1989-09-07 1991-04-22 Canon Inc Semiconductor electron emitting element
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JPH03129633A (en) * 1989-10-13 1991-06-03 Canon Inc Electron emission element
JPH03129632A (en) * 1989-10-13 1991-06-03 Canon Inc Electron emission element
JPH03129634A (en) * 1989-10-13 1991-06-03 Canon Inc Manufacture of electron emission element
US5414272A (en) * 1990-10-13 1995-05-09 Canon Kabushiki Kaisha Semiconductor electron emission element
US5760417A (en) * 1991-09-13 1998-06-02 Canon Kabushiki Kaisha Semiconductor electron emission device
US7577078B2 (en) 2002-12-14 2009-08-18 Samsung Electronics Co., Ltd. Magnetic recording medium and apparatus and method for reading data from the magnetic recording medium using parallel and anti-parallel magnetization direction in separate magnetic layers

Also Published As

Publication number Publication date
DE68918134T2 (en) 1995-01-26
EP0331373A3 (en) 1990-08-22
US5138402A (en) 1992-08-11
EP0331373B1 (en) 1994-09-14
JP2788243B2 (en) 1998-08-20
DE68918134D1 (en) 1994-10-20
EP0331373A2 (en) 1989-09-06

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