JP2000294804A - Schottky barrier diode and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Schottky barrier diode and it manufacturing method which has a low on-voltage and a little leakage current in the reverse bias. SOLUTION: Stripe-like p-buried regions 43a, 43b are, e.g. buried at varied depths and offset in plane in an n-epitaxial layer 42 on an n+-substrate 41. An anode electrode 45 forming a Schottky junction is provided on the surface of the n-epitaxial layer 42 and also contacted to the surface of a p-contact region 44 formed in the epitaxial layer 42, i.e., the buried regions 43a, 43b are held at the same potential as that of the anode electrode 45 through the p- contact region 44.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Schottky barrier diode (hereinafter abbreviated as SBD) utilizing a rectifying action at a metal / semiconductor interface.

[0002]

2. Description of the Related Art An SBD has the following characteristics as compared with a pn diode utilizing the rectifying action of a pn junction. (1) Since the barrier height can be controlled by the metal, the ON voltage can be controlled. (2) Since it is a majority carrier element, there is no accumulation of minority carriers and high-speed switching is possible. (The pn diode is a bipolar element in which minority carriers are accumulated.) Until now, the SBD using silicon has been used in a relatively low withstand voltage region of around 100 V mainly for the purpose of lowering the on-resistance. Recently, S of silicon carbide (hereinafter referred to as SiC)
The BD is expected to be a device capable of high-voltage and high-speed switching by utilizing the feature of the above (2).

[0003] However, SBD has a major obstacle due to physical principles. That is, if the barrier height is reduced to reduce the on-resistance, the leakage current at the time of reverse bias increases. In order to solve this problem, several new structures have been proposed.

FIG. 8 shows an SBD to be announced by F. Dahlquist et al.
[F. Dahlquist, CM.Zettering, M. Oestling, K. Rottn
er, Abstracts of Int.Conf.On silicon carbide, II
I-nitride, and Related Materials 1997, pp.134-13
5] is a partial sectional view of FIG.

A p-type anode region 13 is formed in a stripe shape on the surface layer of an n-type epitaxial layer 12 on an n ⁺ substrate 11, and an anode electrode 15 for forming a Schottky junction is brought into contact with the surface. 16 is an ohmic cathode electrode. The purpose of this is to
When a reverse bias is applied to the device, a depletion layer extending from the pn junction is used. The Schottky junction portion of the anode electrode 15 is covered with the depletion layer to cut off the current, thereby reducing the leakage current in the reverse direction of the SBD.

FIG. 9 shows an SBD announced by KJ Schoen et al.
[KJSchoen, JPHenning, JMWoodall, JACoope
r, Jr., and MRMelloch, Abstracts of Int. Conf. O
n silicon carbide, III-nitride, and Related Materi
als 1997, pp. 419-420].

In this example, a trench 28 is provided in the surface layer of the n-epitaxial layer 22, and a second barrier metal 25b of, for example, Ni, which is a metal having a high barrier height, is provided on the bottom and side walls thereof. The first barrier metal 25a of, for example, Ti, which is a metal, is brought into contact. Thus, when the SBD is biased in the forward direction, a main current flows through the Schottky junction of the first barrier metal 25a having a low barrier height. In the case of reverse bias, the depletion layer spreads from the side wall of the trench 28 where Ni, which is the second barrier metal 25b, is in Schottky junction, and a large leak current of the Schottky junction in the first barrier metal 25a is suppressed. . In this way, a reduction in the reverse leakage current can be realized with a low ON voltage.

[0008]

However, these structures have not completely solved the problem of SBD. First, an SB of the type using a pn junction shown in FIG.
In D, the effective area of the Schottky junction is reduced by the p anode region 13 as is apparent from the figure. In an actual device, an example was shown in which the area was reduced by 50% or 66%. As described above, when the utilization rate of the semiconductor substrate surface is low, even if the metal having a low barrier height is used as a Schottky electrode to reduce the on-voltage, the effective area is reduced and the current density is increased. Causes the on-voltage to rise. In addition, since current concentrates on the Schottky junction, heat is remarkably generated in a high current region, which may cause deterioration of the junction.

On the other hand, in the trench type SBD of FIG. 9, a trench shape must be formed as shown in FIG. Usually, such a trench structure is formed by a dry etching technique such as reactive ion etching (hereinafter referred to as RIE). At this time, a phenomenon occurs such that damage is caused by ion bombardment at the time of RIE, and characteristics of the Schottky junction are deteriorated.

In a low-breakdown-voltage element, the width Wm of the convex portion is 2 to 3 in order to spread the depletion layer in the convex portion between the trenches 28.
In particular, in a device having a high impurity concentration of the n-epitaxial layer 22, the depletion layer does not spread so much. To make this structure work effectively, trenches are formed at a very narrow pitch of submicron. Have to do it.

Not only is it difficult to form trenches at a submicron pitch, it is extremely difficult. In addition, as the width Wm of the projection is reduced, the area of the Schottky junction with a low barrier height is reduced. There is also a problem that the on-voltage increases.

In order to overcome these problems, the inventor has previously proposed an SBD having an embedded region in Japanese Patent Application No. 10-124900. FIG. 10 is a partial sectional view of the SBD. In FIG. 10, a p buried region 33 is buried in an n epitaxial layer 32 on an n ⁺ substrate 31 of SiC. An anode electrode 35 for forming a Schottky junction is provided on the surface of the n epitaxial layer 42. This anode electrode 35 is also in contact with the surface of p contact region 34 formed in the surface layer of n epitaxial layer 32. That is, the p buried region 33 is
, The same potential as the anode electrode 35 is obtained. On the lower surface of the n ⁺ substrate 31, a cathode electrode 36 is provided. In the SBD 30, current concentration at the portion of the Schottky junction can be prevented, and the leakage current at the time of reverse bias is effectively suppressed by the p buried region 33. 37 is an anode electrode 35
This is a guard ring for expanding the depletion layer around.

However, in the example shown in FIG. 10, the distance between the p-buried regions 33 is an important parameter of the leak current, so that it is necessary to control the distance to about 1 μm, for example. However, in order to form such an inter-p buried region 33, in the ion implantation step, a mask having a thickness of several microns is required in order to perform selective ion implantation. And the actual production involves considerable difficulties.

The distance between the p-buried regions 33 in the example of FIG. 10 is equivalent to the distance between the p-anode regions of FIG. 8 and the width of the trench protrusion in the trench structure of FIG. It is the same that matters. Thus, the fact that the distance between the current conducting portions is limited by the mask pattern and it is difficult to make the distance very close is actually a fundamental problem common to the above three types of structures.

In view of such circumstances, an object of the present invention is to provide an SBD which has a low on-voltage, a small leakage current at the time of reverse bias, and is easy to manufacture, and a method of manufacturing the same.

[0016]

The present invention solves the above problems by forming two types of p regions having different depths and controlling a current path by a difference between the depths.
That is, in a Schottky barrier diode in which a metal anode electrode forming a Schottky junction is arranged on the surface of the first conductivity type semiconductor layer and an ohmic cathode electrode is provided on the back surface side of the first conductivity type semiconductor layer, Two or more second conductivity type buried regions having different depths are provided in the first conductivity type semiconductor layer below at least one of them at a depth not reaching the surface so that the depletion layer is continuous at the time of reverse bias. And the buried region of the second conductivity type has the same potential as the anode electrode.

In this case, since the current path is controlled by the difference in the depth of the buried region of the second conductivity type, the width of the current path can be controlled very accurately, and the leakage current characteristic is excellent. It becomes a Schottky barrier diode.

It is assumed that a first conductive type semiconductor layer is provided above the uppermost second conductive type buried region. By doing so, the current can be dispersed and uniformized. Further, the utilization efficiency of the surface of the semiconductor substrate can be increased, and the current concentration as in the related art can be suppressed.

A first conductivity type high concentration region having an impurity concentration higher than that of the first conductivity type semiconductor layer is provided above the uppermost second conductivity type buried region. By providing the first conductivity type high concentration region, the current can be further dispersed and uniformized.

It is assumed that the anode electrode is in contact with the surface of the high concentration region of the first conductivity type. By doing so, the barrier height can be reduced. A second conductivity type contact region that connects the second conductivity type buried region and the anode electrode is provided above a part of the second conductivity type buried region. By doing so, the second conductivity type buried region can be set to the same potential as the anode electrode. The first conductivity type semiconductor layer may be either silicon carbide or silicon.

As a method of manufacturing the above-described Schottky barrier diode, particularly, a method of forming the second conductivity type buried regions having different depths, the second conductivity type impurity is ion-implanted, and then the first conductivity type semiconductor layer is formed. Epitaxial growth
The second conductivity type impurity is ion-implanted into the surface layer of the first conductivity type semiconductor layer or the second conductivity type impurity is ion-implanted from the surface of the first conductivity type semiconductor layer by changing the acceleration voltage. Or two or more second conductivity type buried regions having different depths may be formed, or a thin mask may be selectively provided on the surface of the first conductivity type semiconductor layer and ions of the second conductivity type may be ion-implanted so as to have different depths. One or more second conductivity type buried regions are formed. Whichever method you take,
A Schottky barrier diode having the second conductivity type buried regions having different depths can be manufactured.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. In the following, a layer, a region, or the like entitled with n or p means that electrons and holes are majority carriers, respectively.

Embodiment 1 FIG. 1 is a partial sectional view of a SiCSBD according to a first embodiment of the present invention. In the figure, p buried regions 43a and 43b are buried in the surface layer of the n epitaxial layer 42 on the n ⁺ substrate 41 and in the n epitaxial layer 42, respectively. An anode electrode 45 for forming a Schottky junction is provided on the surface of the n epitaxial layer 42. This anode electrode 45 is also in contact with the surface of p contact region 44 formed in the surface layer of n epitaxial layer 42. That is, the p buried region 43 b is set at the same potential as the anode electrode 45 via the p contact region 44. An ohmic cathode electrode 46 is provided on the lower surface of the n ⁺ substrate 41.
The description of the p guard ring for achieving a high withstand voltage is omitted.

For example, in the case of a 1000 V class SiCSBD, examples of the dimensions of each part are as follows. The impurity concentration and the thickness of the n ⁺ substrate 41 are 2 × 10 ¹⁸ cm, respectively.
^-3 , 250 μm, that of the n epitaxial layer 42
× 10 ¹⁶ cm ^-3 , 10 μm. p embedded region 43
The width and thickness of a and 43b are 6 μm and 0.7 μm, respectively.
And the maximum impurity concentration is 1 × 10 ²⁰ cm ⁻³ . The vertical spacing between the p-embedded regions 43a and 43b is 2 μm.
It is. The width and thickness of the p contact region 44 are respectively
6 μm, 2 μm, maximum impurity concentration is 1 × 10 ²⁰ cm
It is ^-3 . The anode electrode 45 is composed of a 0.1 μm titanium layer and a 1 μm aluminum layer.

It is preferable that the widths of the p-embedded regions 43a and 43b are as narrow as possible. However, appropriate dimensions and impurity concentrations are determined by patterning accuracy and conductance, and are usually about 1 to 10 μm. In addition, since the interval between the p buried regions 43 is determined by the width of the depletion layer, it is necessary to individually design each of the breakdown voltage structures.

FIG. 3A is a plan view seen through the anode electrode 45 of the SBD chip of FIG. The stripe-shaped p buried region 43a of the surface layer is indicated by a dotted line.
Although the deeper p-embedded region 43b is not shown, it is also formed in a stripe shape and shifted from the p-embedded region 43a of the surface layer. The outer ring of the anode electrode 45 is a p guard ring 47.

FIG. 3B is a cross-sectional view taken along the line AA, showing a state where the p buried regions 43a and 43b are in contact with the p contact region 44, and a p guard ring 47.
Can be seen. P buried region 43a in the surface layer
A ring-shaped p-contact region 44 is provided below the peripheral portion, and an anode electrode 45 is in contact with the surface thereof. The p contact region 44 does not necessarily have to be only in the peripheral portion. Further, the p-buried region 43a of the surface layer and the p guard ring 47 may have the same surface concentration and the same junction depth.

The feature of the SBD of this embodiment is that the p buried regions 43a and 43b electrically short-circuited to the anode electrode.
Are embedded in the semiconductor surface layer and the inside thereof in two steps, and in a displaced arrangement from each other.

The effect of this structure will be described with reference to the operation diagram of FIG. FIG. 2 is a slightly enlarged cross-sectional view of FIG. 1, and a current path is indicated by an arrow 6. As can be seen from this figure, the current flows through the regions sandwiched between the p buried regions 43a and 43b having different depths. Therefore, the width of the current path is controlled as the difference between the depths of the p buried regions 43a and 43b.
It is characterized in that a submicron distance can be easily controlled as compared with the above-described patterning, and a very narrow current path can be set.

In actual production, the difference between the depths is equal to 0.
The thickness can be set to about 2 to 1 μm, and an optimum value can be set depending on the impurity concentration of the n epitaxial layer 42. That is, the extent of the depletion layer varies depending on the impurity concentration of the n-type region.

Further, at the time of reverse bias, the depletion layer 5 spreads from the p buried regions 43a and 43b buried inside the semiconductor, and is not affected by the surface or the like. There are also benefits that you can do. In an actual prototype SBD, it was confirmed that the leak current was reduced to about 1/4 of the conventional value.

Next, a method of manufacturing the SBD of the first embodiment will be described. FIGS. 4A to 4E are cross-sectional views of main manufacturing steps in the order of the manufacturing steps. A silicon oxide film 8a is formed on an n epitaxial layer 42 grown about 8 μm on an n ⁺ substrate (not shown), patterned by photolithography, and ion-implanted, for example, boron ions 3a for a deep p buried region 43b. [FIG. 4 (a)]. The accelerating voltage is 50 keV,
The dose was 1 × 10 ¹⁵ cm ⁻² .

The ions to be implanted are p-type impurities. In the case of silicon, boron is usually used, and in the case of SiC, boron or aluminum is used. At the same acceleration voltage, boron is more deeply implanted, but aluminum is more easily activated in SiC. The dose does not significantly affect the SBD characteristics, but is usually in the range of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² in order to lower the conductance of the p-buried region 43. However, in the case of SiC, high-temperature implantation may be performed due to the problem of activation of the ion-implanted impurities. At this time, since the mask for ion implantation needs to withstand high temperatures, a high-melting-point metal film such as silicon, an oxide film, or titanium is used.

Next, a heat treatment is performed at 1700 ° C. for 30 minutes to activate, and then the remaining 2 μm of the n epitaxial layer 42 is
m is epitaxially grown [FIG. Next, the silicon oxide film 8b is again formed on the n epitaxial layer 42.
Is formed and patterned by photolithography, and boron ions 3a for the p-contact region 44 are ion-implanted [FIG. The accelerating voltage is 200,5
00 and 800 keV, and the dose was 1 × 10 ¹⁵ cm ⁻² each.

Next, patterning is again performed by photolithography, and boron ions 3a for the p-buried region 43a in the surface layer are ion-implanted (FIG. 4D). The accelerating voltage is 50 keV and the dose is 1 × 1
It was set to 0 ¹⁵ cm ^-2 . With this method, a mask can be formed using the silicon oxide film 8b of FIG. 3C again.

Subsequently, a heat treatment is performed at 1700 ° C. for 30 minutes [FIG. The implanted impurities are activated, and p
The buried regions 43a and 43b and the p-contact region 44 are formed.

Thereafter, titanium is sputter-deposited at 0.1 μm and aluminum is sputter-deposited at 1 μm to form an anode electrode. Further, aluminum is vapor-deposited on the back surface of the n ⁺ substrate to form a cathode electrode, thereby completing the SBD shown in FIG. FIG.
The manufacturing methods (a) to (e) are extremely simple and can be easily manufactured without the need for expensive equipment and difficult steps as in conventional RIE.

Further, this manufacturing method is characterized in that boron ion implantation for the p buried region 43 can be performed at a relatively low accelerating voltage as compared with a manufacturing method described later. That is, since high-energy ion implantation equipment is very expensive, such expensive equipment is not required, and there is an advantage that an ordinary low-energy apparatus can be used. In addition, a mask for ion implantation with a low acceleration voltage does not need to be so thick.

Embodiment 2 FIGS. 5 (a) to 5 (d)
Example 2 SB having a structure similar to that of FIG. 1 according to another manufacturing method
FIG. 4 is a cross-sectional view showing the order of manufacturing steps in the manufacturing method of D. The lower part of the SBD is omitted due to space limitations.

10 on n ⁺ substrate not shown
A silicon oxide film 8a is formed on the n-epitaxial layer 52 grown by μm, patterned by photolithography, and boron ions 3a for the deep p buried region 53b are ion-implanted [FIG. 5 (a)]. The acceleration voltage was 1.5 MeV and the dose was 1 × 10 ¹⁵ cm ⁻² .

Next, a silicon oxide film 8b is formed again on the n-epitaxial layer 52, patterned by photolithography, and boron ions 3a for the p-contact region 54 are implanted [FIG. ].
The accelerating voltage was 200, 500, and 800 keV, and the dose was 1 × 10 ¹⁵ cm ⁻² .

Next, patterning is again performed by photolithography, and boron ions 3a for the p buried region 53a of the surface layer are ion-implanted (FIG. 9C). The accelerating voltage is 50 keV and the dose is 1 × 1
It was set to 0 ¹⁵ cm ^-2 . With this method, a mask can be formed using the silicon oxide film 8b of FIG. 5B again.

Subsequently, a heat treatment is performed at 1700 ° C. for 30 minutes [FIG. The implanted impurities are activated, and p
The buried regions 53a and 53b and the p-contact region 54 are formed.

Thereafter, 0.1 μm of titanium and 1 μm of aluminum are sputter-deposited to form an anode electrode. Further, aluminum is deposited on the back surface of the n ⁺ substrate to complete the SBD as a cathode electrode.

This method utilizes the fact that the implantation depth can be adjusted by controlling the accelerating voltage at the time of ion implantation to, for example, 50 keV to 1.5 MeV, and utilizes two different depths of p buried regions 53a, 53b and p. The contact region 54 is formed by controlling with an acceleration voltage.

This manufacturing method is characterized in that mask formation and ion implantation can be performed without interposing epitaxial growth in the middle. The SBD according to this manufacturing method also shows almost the same characteristics as the SBD of the first embodiment.

[Embodiment 3] FIGS. 6 (a) to 6 (c)
FIG. 13 is a cross-sectional view illustrating a method of manufacturing an SBD according to a third embodiment having a structure similar to that of FIG. 1 according to still another manufacturing method in the order of manufacturing steps.

N not shown⁺10 on substrate
silicon oxide on the n-epitaxial layer 62
A film 8a is formed, and a pattern is formed by photolithography.
And boron ions for p-contact region 54
3a is ion-implanted [FIG. 6 (a)]. Acceleration voltage is 20
0, 500, and 800 keV, and the dose amount is 1 × 10 ¹⁵
cm^-2And

Next, the thickness of the silicon oxide film 8a is adjusted and patterned by photolithography, and boron ions 3a for the p buried regions 63a and 63b are implanted [FIG. Acceleration voltage is 1.5MeV
And the dose was 1 × 10 ¹⁵ cm ⁻² .

Subsequently, a heat treatment is performed at 1700 ° C. for 30 minutes [FIG. The implanted impurities are activated, and p
The buried regions 63a and 63b and the p-contact region 64 are formed.

Thereafter, titanium is sputter-deposited at 0.1 μm and aluminum is sputter-deposited at 1 μm to form an anode electrode. Further, aluminum is deposited on the back surface of the n ⁺ substrate to complete the SBD as a cathode electrode.

In this method, ion implantation is also used, but unlike the previous example, ion implantation for the p buried regions 63a and 63b is performed with a single accelerating voltage, and the difference in depth is determined by the mask. Is controlled by That is, the thickness of the mask is set so that the shallower p-embedded region 63a passes through the mask and reaches the semiconductor on the substrate. Therefore,
The difference between the depths of the p buried regions 63a and 63b is controlled by the thickness of the mask, and the
One time and one ion implantation can be manufactured in a shorter process compared to the above two methods.

The SBD according to this manufacturing method is the same as that of the first embodiment.
It shows almost the same characteristics as BD. [Embodiment 4] FIG. 7 is a partial sectional view of an SBD according to a fourth embodiment of the present invention.

The difference from the SBD of the first embodiment shown in FIG. 1 is that the n epitaxial layer 7 on the n ⁺ substrate 71
2 is that two stages of p-embedded regions 73a and 73b are embedded. The anode electrode 75 forming the Schottky junction is in contact with almost the entire surface of the n epitaxial layer 72.

The p buried portions 73a and 73b are alternately arranged, and the anode electrode 75 on the surface and the p contact region 7 are arranged alternately.
It is the same that they are connected via 4 so that sub-micron distances can be easily controlled and very narrow current paths can be set up.

In this structure, the S in the first embodiment shown in FIG.
Unlike the BD, the area of the Schottky junction does not decrease, and the entire surface of the epitaxial layer 72 is used. Therefore, the forward voltage can be reduced.

Further, since the current also flows in the upper part of the p buried region 73a, there is an effect of reducing the current concentration. As a result, heat generation at the Schottky junction is reduced, and the temperature rise is suppressed.

The method of Embodiments 1 to 3 can be appropriately applied to the method of manufacturing the SBD of Embodiment 4. [Embodiment 5] FIG. 8 is a partial sectional view of an SBD according to a fifth embodiment of the present invention.

The difference from the SBD of the fourth embodiment shown in FIG. 7 is that the n epitaxial layer 82 on the p buried region 83b
Is that a high concentration n ⁺ high concentration region 89 is formed in the surface layer, and an anode electrode 85 for forming a Schottky junction is provided on the surface.

In order to make such a structure, the S
In addition to the BD process, phosphorous ions are accelerated at an accelerating voltage of 20 keV.
1 × 10 ¹⁴ cm ⁻² may be implanted and annealed. If annealing is performed simultaneously with B and Al, only one heat treatment is required.
The n ⁺ high concentration region 89 can be formed by implanting nitrogen ions in SiC and arsenic ions in silicon instead of phosphorus ions.

In this way, the effect of reducing the barrier height of the Schottky junction can be obtained. For example, in the SiCSBD of this embodiment, the forward voltage at a current density of 100 A · cm ⁻² was reduced by 0.2V. Needless to say, since the anode electrode 85 is provided on the entire surface in the same manner as in the fourth embodiment, there is also an effect that the current density can be suppressed low. In addition, the effect of alleviating the current concentration is great, and the temperature rise is suppressed because the heat generated at the junction is small.

[0062]

As described above, according to the present invention, an anode electrode of a metal forming a Schottky junction is arranged on the surface of the first conductive type semiconductor layer, and the ohmic electrode is formed on the back side of the first conductive type semiconductor layer. In the Schottky barrier diode provided with a suitable cathode electrode, the second conductivity type is provided at two or more different depths of the first conductivity type semiconductor layer below the anode electrode at intervals such that the depletion layer is continuous at the time of reverse bias. A buried region is formed, the centers of adjacent upper and lower second conductivity type buried regions are shifted from each other on a plan view, and the second conductivity type buried region is set to the same potential as the anode electrode, so that a low on-voltage is achieved. And a low leakage current can be realized.

The present invention which can realize a Schottky barrier diode with low on-voltage and low leakage current has a high breakdown voltage,
This has great significance in expanding the applications of Schottky barrier diodes as high-speed switching devices.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of an SBD according to a first embodiment of the present invention.

FIG. 2 is an operation diagram for explaining an effect of the present invention.

FIG. 3A is a plan view of the SBD according to the first embodiment,
(B) is a sectional view taken along line AA.

FIGS. 4A to 4E are partial cross-sectional views in the order of manufacturing steps according to the method of manufacturing the SBD of the first embodiment.

FIGS. 5A to 5D are partial cross-sectional views in the order of manufacturing steps according to the method of manufacturing an SBD of the second embodiment.

FIGS. 6A to 6C are partial cross-sectional views in the order of manufacturing steps according to a method of manufacturing an SBD according to a third embodiment;

FIG. 7 is a partial sectional view of an SBD according to a fourth embodiment of the present invention.

FIG. 8 is a partial sectional view of an SBD according to a fifth embodiment of the present invention.

FIG. 9 is a partial cross-sectional view of a conventional low leakage current SBD.

FIG. 10 is a partial cross-sectional view of another conventional low leakage current SBD.

FIG. 11 is a partial cross-sectional view of a conventional improved SBD.

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 71 n ⁺ substrate layer 12, 22, 32, 42, 52, 62, 72 n epitaxial layer 13 p anode region 15, 35, 45, 65, 75 anode electrode 16 , 26, 36, 46, 56, 66, 76 cathode electrode 25a, 55a first barrier metal 25b, 55b second barrier metal 28 trench 33, 43, 53, 63, 73 p buried region 33a, 34a, 43a, 44a Elemental ions 34, 44, 54, 64, 74 p contact region 37 p guard ring 38, 48a, 48b silicon oxide film 42an n epitaxial layer 69, 79n ⁺ high concentration region

Claims (10)

[Claims] 1. A Schottky barrier diode in which a metal anode electrode forming a Schottky junction is arranged on the surface of a first conductivity type semiconductor layer and an ohmic cathode electrode is provided on the back side of the first conductivity type semiconductor layer. A second conductivity type buried region is formed at an interval such that a depletion layer is continuous at the time of reverse bias at two or more different depths of the first conductivity type semiconductor layer below the anode electrode. A Schottky barrier diode, wherein the two conductivity type buried regions are shifted from each other on a plan view, and the second conductivity type buried region is set to the same potential as an anode electrode. 2. The Schottky barrier diode according to claim 1, further comprising a first conductivity type semiconductor layer above the uppermost second conductivity type buried region. 3. The Schottky barrier diode according to claim 1, further comprising a first conductivity type high concentration region having a higher impurity concentration than the first conductivity type semiconductor layer above the uppermost second conductivity type buried region. . 4. The Schottky barrier diode according to claim 3, wherein an anode electrode is in contact with the surface of the first conductivity type high concentration region. 5. The method according to claim 5, further comprising:
The Schottky barrier diode according to any one of claims 1 to 4, further comprising a second conductivity type contact region that connects the second conductivity type buried region and the anode electrode. 6. The Schottky barrier diode according to claim 1, wherein the first conductivity type semiconductor layer is made of silicon carbide. 7. The Schottky barrier diode according to claim 1, wherein the first conductivity type semiconductor layer is made of silicon. 8. An anode electrode of a metal forming a Schottky junction provided on the surface of the first conductivity type semiconductor layer, an ohmic cathode electrode provided on the back surface side, and the first conductive layer below the anode electrode. In the type semiconductor layer, two or more second conductivity type buried regions having different depths, at least one having a depth not reaching the surface, formed at intervals such that the depletion layer is continuous at the time of reverse bias. In the method for manufacturing a Schottky barrier diode having a conductivity type buried region, after ion implantation of a second conductivity type impurity, a first conductivity type semiconductor layer is epitaxially grown, and a second layer is formed on a surface layer of the first conductivity type semiconductor layer. A method for manufacturing a Schottky barrier diode, characterized in that a conductive impurity is ion-implanted. 9. A metal anode electrode for forming a Schottky junction provided on the surface of the first conductivity type semiconductor layer, an ohmic cathode electrode provided on the back side, and the first conductive layer below the anode electrode. In the type semiconductor layer, two or more second conductivity type buried regions having different depths, at least one having a depth not reaching the surface, formed at intervals such that the depletion layer is continuous at the time of reverse bias. In the method of manufacturing a Schottky barrier diode having a conductive type buried region, two or more different depths from the surface of the first conductive type semiconductor layer by ion-implanting a second conductive type impurity by changing the acceleration voltage. A method of manufacturing a Schottky barrier diode, comprising forming a second conductivity type buried region. 10. A Schottky junction metal anode electrode provided on the front surface of the first conductivity type semiconductor layer, an ohmic cathode electrode provided on the back surface side, and the first conductive material below the anode electrode. In the type semiconductor layer, two or more second conductivity type buried regions having different depths, at least one having a depth not reaching the surface, formed at intervals such that the depletion layer is continuous at the time of reverse bias. In a method for manufacturing a Schottky barrier diode having a buried region of a conductivity type, a thin mask is selectively provided on the surface of a semiconductor layer of a first conductivity type and ions of a second conductivity type are ion-implanted to form two layers having different depths. A method of manufacturing a Schottky barrier diode, comprising forming the above-described second conductivity type buried region.