JPH11330498A - Schottky barrier diode and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Schottky barrier diode having low ON voltage in which leak current is suppressed in a reverse bias and a fabrication method therefor. SOLUTION: A p<+> buried region 33 is buried in an n-epitaxial layer 32 on an n<+> substrate 31. An anode electrode 35 forming a Schottky junction is provided on the surface of the n-epitaxial layer 32 and also connected with the surface of a p<+> contact region 34 formed on the surface of the n-epitaxial layer 32. More specifically, the p<+> buried region 33 is brought to same potential as the anode electrode 35 through the p<+> contact region 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a Schottky barrier diode (hereinafter abbreviated as SBD).

[0002]

2. Description of the Related Art An SBD has the following characteristics as compared with a pn diode having a pn junction. (1) Since the barrier height can be controlled by the metal, the ON voltage can be controlled. (2) Since it is a majority carrier element, there is no accumulation of minority carriers and high-speed switching is possible. (The pn diode is a bipolar element in which minority carriers are accumulated.) Until now, the SBD using silicon has been used in a relatively low withstand voltage region of around 100 V mainly for the purpose of lowering the on-resistance. Recently, S of silicon carbide (hereinafter referred to as SiC)
The BD is expected to be a device capable of high-voltage and high-speed switching by utilizing the feature of the above (2).

[0003] However, SBD has a major obstacle due to physical principles. That is, if the barrier height is reduced to reduce the on-resistance, the leakage current at the time of reverse bias increases. In order to solve this problem, several new structures have been proposed. Figure 8 shows F.
Dahlquist, CM. Zettering, M. Yo stling, K. Rottner announce SBD ["Junction Barrier Schottky dio
des in 4H-SiC and 6H-SiC "Abstracts of Int. Conf.
On silicon carbide, III-nitride, and Related Mater
ials 1997, pp. 134-135].

A p ⁺ anode region 13 is formed in a stripe shape on a surface layer of an n epitaxial layer 12 on an n ⁺ substrate 11, and an anode electrode 15 for forming a Schottky junction is brought into contact with the surface. 16 is an ohmic cathode electrode. The purpose of this is to utilize the depletion layer that extends from the p ⁺ n junction when a reverse bias is applied to the device. Anode electrode 1
The Schottky junction No. 5 is covered with the depletion layer to cut off the current, thereby reducing the reverse leakage current of the SBD.

FIG. 9 shows KJSchoen, JP Henning, JMWoo
dall, JACooper, Jr., and MRMelloch announce SBD ["A Dual-Metal-Trench (DM) Schottky Pinch-R
ectifier in 4H-SiC "Abstracts of Int. Conf. On sil
icon carbide, III-nitride, and Related Materials 19
97, pp. 419-420]. In this example, n
A trench 28 is provided in a surface layer of the epitaxial layer 22,
A metal having a high barrier height, for example, a second barrier metal 25b of Ni, and a first barrier metal 25a, for example, a metal having a low barrier height, such as Ti, are brought into contact with the bottom and side walls of the trench. Thus, when the SBD is biased in the forward direction, a main current flows through the Schottky junction of the first barrier metal 25a having a low barrier height. When reverse biased, the second barrier metal 2
Trench 2 in which Ni that is 5b is in Schottky junction
8, the depletion layer extends from the side wall of the first barrier metal 25a.
Large leakage current of the Schottky junction is suppressed. Thus, a low on-state voltage is realized while reducing the reverse leakage current.

[0006]

However, these structures have not completely solved the problem of SBD. First, an SB of the type using a pn junction shown in FIG.
In D, as is clear from the figure, the effective area of the Schottky junction is reduced by the amount of the p ⁺ anode region 13. In an actual device, an example was shown in which the area was reduced by 50% or 66%. However, when the utilization rate of the semiconductor substrate surface is low as described above, even if the on-voltage is reduced by using a metal having a low barrier height as a Schottky electrode, the effective area is reduced, and the current density is large. Therefore, the on-voltage rises. Also,
Since the current is concentrated on the Schottky junction, heat generation is remarkable in a high current region, which may cause deterioration of the junction.

On the other hand, in the trench type SBD shown in FIG. 9, a trench shape must be formed as shown in FIG. Usually, such a trench structure is formed by a dry etching technique such as reactive ion etching (hereinafter referred to as RIE). At this time, a phenomenon occurs such that damage is caused by ion bombardment at the time of RIE, and characteristics of the Schottky junction are deteriorated.

In a low-breakdown-voltage element, the width Wm of the convex portion is 2 to 3 in order to spread the depletion layer in the convex portion between the trenches 28.
μm. In particular, in a device in which the impurity concentration of the n-epitaxial layer 21 is high, the depletion layer does not widen so much. In order to make this structure work effectively, trenches must be formed at a very narrow pitch of submicron.

[0009] The formation of trenches with a very narrow pitch of submicron is not only a manufacturing problem that it is very difficult, but also the area of the Schottky junction with a low barrier height becomes narrower as the width Wm of the projection is reduced. This causes a problem that the on-state voltage increases. SUMMARY OF THE INVENTION It is an object of the present invention to provide an SB having a low leakage current at the time of reverse bias and a low ON voltage
D and its manufacturing method.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method in which a metal anode electrode for forming a Schottky junction is arranged on a surface of a first conductivity type semiconductor layer, and a back side of the first conductivity type semiconductor layer is provided. In a Schottky barrier diode provided with an ohmic cathode electrode, the second conductivity type buried region that does not reach the surface inside the first conductivity type semiconductor layer below the anode electrode is formed such that the depletion layer is continuous at the time of reverse bias. The buried region of the second conductivity type has the same potential as the anode electrode.

A second conductivity type buried region having the same potential as the anode electrode is provided, and an anode electrode for forming a Schottky junction is provided on the surface of the first conductivity type semiconductor layer thereon.
The area of the Schottky junction is not reduced, the utilization efficiency of the surface of the semiconductor substrate can be increased, and current concentration as in the related art can be prevented. At the time of reverse bias, a depletion layer extending from the buried region of the second conductivity type is made continuous, so that a leak current can be suppressed low.

An anode electrode comprising a first barrier metal having a small barrier height and a second barrier metal having a large barrier height, wherein the first barrier metal is disposed at least partially above the buried region of the second conductivity type. And In this case, at the time of forward bias, a current flows through the first barrier metal having a small barrier height, so that a low on-resistance can be obtained. At the time of reverse bias, the depletion layers extending from the buried region of the second conductivity type or the depletion layers extending from the second barrier metal are made continuous, so that the leak current can be suppressed.

A first conductivity type high concentration region having a higher impurity concentration than the first conductivity type semiconductor layer is provided above the second conductivity type buried region. By providing the first-conductivity-type high-concentration region, current distribution and uniformity can be achieved, and current concentration can be suppressed. It is assumed that the anode electrode contacts the surface of the first conductivity type high concentration region.

With this configuration, the barrier height can be reduced. A second conductivity type contact region that connects the second conductivity type buried region and the anode electrode is provided above a part of the second conductivity type buried region. By doing so, the second conductivity type buried region can be set to the same potential as the anode electrode.

The first conductivity type semiconductor layer may be either silicon or silicon carbide. As a method of manufacturing a Schottky barrier diode having a second conductivity type buried region that does not reach the surface inside the first conductivity type semiconductor layer below the anode electrode, a second conductive type semiconductor layer is formed from the surface of the first conductivity type semiconductor layer. After the type impurity is ion-implanted or the second conductivity-type impurity is ion-implanted, the second conductivity type buried region is formed by epitaxially growing the first conductivity type semiconductor layer.

In any of such methods, a Schottky barrier diode having a second conductivity type buried region at a predetermined interval can be manufactured.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. In the following, n or p
Means that electrons and holes are majority carriers, respectively. Embodiment 1 FIG. 1 shows a SiCSBD according to a first embodiment of the present invention.
FIG.

In the figure, ap ⁺ buried region 33 is buried in an n epitaxial layer 32 on an n ⁺ substrate 31 of SiC. On the surface of the n-epitaxial layer 32, an anode electrode 35 of titanium and aluminum for forming a Schottky junction is provided. This anode electrode 35 is also in contact with the surface of p ⁺ contact region 34 formed in the surface layer of n epitaxial layer 32. That, p ⁺ buried region 33, p ⁺
This means that the potential is the same as that of the anode electrode 35 via the contact region 34. On the lower surface of the n ⁺ substrate 31, a cathode electrode 36 is provided. The description of the p guard ring 1 for increasing the withstand voltage is omitted.

For example, in the case of a 1000 V class SiCSBD, examples of the dimensions of each part are as follows. The impurity concentration and the thickness of the n ⁺ substrate 31 are each 2 × 10 ¹⁸ c
m ⁻³ , 250 μm, that of the n epitaxial layer 32
It is 1 × 10 ¹⁶ cm ⁻³ and 10 μm. The width and thickness of p ⁺ buried region 33 are 6 μm and 0.7 μm, respectively, and the maximum impurity concentration is 1 × 10 ²⁰ cm ⁻³ . The interval between the p ⁺ buried regions 33 is 2 μm. The thickness of n epitaxial layer 32 on p ⁺ buried region 33 is 0.7 μm.
m. The width and thickness of p ⁺ contact region 34 are 6 μm and 0.7 μm, respectively, and the maximum impurity concentration is 1 ×
10 ²⁰ cm ^-3 . The anode electrode 35 is composed of a 0.1 μm titanium layer and a 1 μm aluminum layer.

The width of the p ⁺ buried region 33 is preferably as narrow as possible, but an appropriate size and impurity concentration are determined by the patterning accuracy and conductance, and are usually about 1 to 10 μm. Also, the p ⁺ buried region 33
Is determined by the width of the depletion layer, so it is necessary to individually design each withstand voltage structure. FIG. 2 (a)
FIG. 2 is a plan view seen through an anode electrode 35 of the SiCSBD chip of FIG. 1. The striped p ⁺ buried region 33 is shown by a dotted line. An annular p ⁺ contact region 34 is provided around the stripe-shaped p ⁺ buried region 33, and the anode electrode 35 is in contact with the surface of the p ⁺ contact region 34. The outer ring of the anode electrode 35 is a p ⁺ guard ring 37. FIG. 2B is a cross-sectional view taken along line AA.
The situation where p ⁺ buried region 33 is in contact with p ⁺ contact region 34 and the placement situation of p ⁺ guard ring 37 are seen. The p ⁺ contact region 34 does not necessarily have to be only in the peripheral portion. Also, the p ⁺ contact region 3
4 and the p ⁺ guard ring 37 may have the same surface concentration and the same junction depth.

Next, a method of manufacturing the SiCSBD of the first embodiment will be described. FIGS. 3A to 3D are cross-sectional views for respective main manufacturing steps shown in the order of the manufacturing steps. A silicon oxide film 38 is formed on the grown n epitaxial layer 32.
Is formed, and patterned by photolithography, and boron ions 34a for forming a shallow p ⁺ contact region 34 and a p ⁺ guard ring (not shown) are ion-implanted [FIG. 3 (a)]. The accelerating voltage is 30, 80,
The dose was 200 keV and the dose was 1 × 10 ¹⁵ cm ⁻² .

In the case of SiC, ion implantation may be performed at a high temperature of 500 to 1000 ° C. due to the problem of activation of the ion-implanted impurities. Since the ion implantation mask in this case needs to withstand high temperatures, a silicon oxide film, silicon, or a metal such as titanium or aluminum is used. Boron or aluminum is used as the p-type impurity ion. At the same acceleration voltage, boron is more deeply implanted, but aluminum is more easily activated in SiC. The acceleration voltage at the time of ion implantation is, for example, 200 keV or more.
By controlling the voltage to 3 MeV, the p ⁺ buried region 33 is formed.
The depth of the can be adjusted. Although the dose does not significantly affect the SBD characteristics, it is preferable that the dose be in the range of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² in order to reduce the conductance of the p ⁺ buried region 33.

Next, patterning is again performed by photolithography, and boron ions 33a for the p ⁺ buried region 33 are implanted [FIG. The ion implantation conditions were as follows: an acceleration voltage of 500 keV and a dose of 1 ×.
It is 10 ¹⁵ cm ^-2 . With this method, a mask can be formed using the silicon oxide film 38 of FIG. 3A again. If the silicon oxide film is formed again, p
⁺ Ion implantation for the buried region 33 may be performed first.

Subsequently, a heat treatment is performed at 1700 ° C. for 30 minutes [FIG. The implanted impurities are activated, and p
⁺ Buried region 33 and p ⁺ contact region 34 are formed. Titanium is sputter-deposited at a thickness of 0.1 μm, and aluminum is sputter-deposited at a thickness of 1 μm. Further, aluminum was vapor-deposited on the back surface of the n ⁺ substrate 31 to form a cathode electrode [FIG.

The feature of the SBD of this embodiment is that the anode potential
P⁺The buried region 33 is buried inside the semiconductor.
It is rare. In such a structure,
8, the area of the Schottky junction is greatly reduced.
There is nothing less. Therefore, the surface of the semiconductor substrate is effectively utilized.
And the ON voltage does not increase. Also, p ⁺
The upper part of the buried region 33 is shaded and current hardly flows.
And the current spreads and flows. That is, the current collector
It has the effect of relaxing inside. This allows Schottky bonding
The heat generated by the heating is reduced, and the temperature rise is suppressed.

Furthermore, at the time of reverse bias, the depletion layer spreads from the p ⁺ buried region 33 buried in the semiconductor, and is not affected by the surface or the like. Actual prototype SB
Also in D, it was confirmed that the leak current was reduced to about 1/4 of the conventional value.

The manufacturing method shown in FIGS. 3A to 3D is extremely simple, and can be easily manufactured without the need for expensive equipment and difficult steps as in conventional RIE. [Embodiment 2] FIGS. 4A to 4F show the SiC of FIG.
It is sectional drawing which showed the manufacturing process by another manufacturing method of SBD in order. The lower part of the SBD is omitted in a part of the space.

A silicon oxide film 48a is formed on the grown n epitaxial layer 42, patterned by photolithography, and boron ions 43a for the p ⁺ buried region 43 are implanted [FIG. 4 (a)]. . The ion implantation conditions may be the same as in the first embodiment. Then, 1
A heat treatment is performed at 700 ° C. for 30 minutes to activate [FIG. The implanted impurities are activated, and p ⁺ buried region 43 is formed.

An n-type epitaxial layer 42a having a thickness of about 1 μm is grown at 1500 ° C. by a monosilane-propane-hydrogen gas system (FIG. 3C). Further, a silicon oxide film 48b is formed on the grown n epitaxial layer 42a.
Is formed, and patterned by photolithography, and boron ions 44a for forming ap ⁺ contact region 44 are ion-implanted [FIG. Acceleration voltage is 3
0, 80, and 200 keV, and the dose amount is 1 × 10 ¹⁵
cm ^-2 .

Here, a heat treatment is performed at 1700 ° C. for 30 minutes [FIG. The implanted impurities are activated, and p
⁺ Contact region 44 is formed. 0.1μ titanium
m and aluminum are sputter-deposited at 1 μm to form an anode electrode 45. Further, aluminum was vapor-deposited on the rear surface of the n ⁺ substrate 41 to form a cathode electrode 46 [FIG.

In this manufacturing method, p ⁺ buried region 43
It is characterized in that boron ion implantation for GaAs can be performed at a low acceleration voltage. That is, since high-energy ion implantation equipment is very expensive, such expensive equipment is not required, and there is an advantage that an ordinary low-energy apparatus can be used. The SBD by this manufacturing method also shows the same characteristics as the SBD of the first embodiment.

[Embodiment 3] FIG. 5 is a partial sectional view of a SiCSBD according to a third embodiment of the present invention. The internal structure of the semiconductor of this embodiment is the same as that of the first embodiment, and the arrangement of the barrier metal is devised. An anode electrode of the first barrier metal 55a having a low barrier height is arranged on a part of the surface above the p ⁺ buried region 53, and the other uses a second barrier metal 55b having a higher barrier height. For example, hafnium is used as the first barrier metal 55a having a low barrier height, and the second barrier metal 5 having a high barrier height is used.
Nickel was used as 5b.

With such a structure, it is possible to alleviate that the upper portion of the p ⁺ buried region 53 becomes a shadow and that the current hardly flows, and the current spreads to the upper portion of the p ⁺ buried region 53 and flows more easily. That is, the effect of reducing the current concentration is great. Also, regarding the leakage current at the time of reverse bias, p
^{+ A} depletion layer extending from the buried region 53 and the second barrier metal 55b is connected, so that a leak current in a portion of the first barrier metal 55a having a low barrier height can be suppressed. Therefore, a low on-voltage and a low leakage current can be realized simultaneously.

The method of manufacturing the SiCSBD of this embodiment can be easily inferred from the manufacturing method of the first or second embodiment. For example, after the step of FIG. 3C, the first barrier metal 55a may be deposited and patterned, and then the second barrier metal 55b may be deposited. SiCS of this embodiment
The plan view of the BD is the same as that of FIG.

[Embodiment 4] FIG. 6 is a partial sectional view of a SiCSBD according to a fourth embodiment of the present invention. This structure is also based on the structure of the first invention. p ⁺ embedded region 63
High concentration of n ⁺
A high concentration region 69 is formed, and an anode electrode 65 for forming a Schottky junction is provided on the surface.

To achieve such a structure, for example, FIG.
After the step (b), phosphorus ions may be implanted at 1 × 10 ¹⁴ cm ⁻² at an acceleration voltage of 20 keV and annealing may be performed. If annealing is performed simultaneously with boron or aluminum, only one heat treatment is required. In SiC instead of phosphorus, nitrogen can also be used as an n-type impurity. Arsenic may be used for Si. With such a structure, the effect of reducing the barrier height of the Schottky junction can be obtained. For example, the SiCS of this embodiment
In the case of BD, the ON voltage at a current density of 100 A · cm ⁻² decreased by 0.2 V. Needless to say, since the anode electrode 65 is provided on the entire surface in the same manner as in the above embodiment, there is also an effect that the current density can be kept low. In addition, the effect of alleviating the current concentration is great, and the temperature rise is suppressed because the heat generated at the junction is small.

[Embodiment 5] FIG. 7 is a partial sectional view of a SiCSBD according to a fifth embodiment of the present invention, which can be said to be a modification of the fourth embodiment. Although p ⁺ buried point above the region 73 high concentration n ⁺ high concentration region 79 is formed is the same as in Example 4, it is limited to a portion above the p ⁺ buried region 73. The anode electrode 75 is provided on the entire surface.

To achieve such a structure, for example, FIG.
After the step (b), a mask is formed and the fourth embodiment is selectively performed.
A phosphorous ion implantation similar to that described above may be performed and annealing may be performed. Above p ⁺ buried region 73, n with a high impurity concentration
^{Since the +} high-concentration region 79 is added, a current easily flows also in the upper part of the p ⁺ buried region 73. n ⁺
Since the barrier height is reduced in the high-concentration region 79, an effect of reducing the on-voltage can be obtained. As for the leakage current at the time of reverse bias, the depletion layer extending from the p ⁺ buried region 73 or the depletion layer extending from the anode electrode 75 where the n ⁺ high-concentration region 79 is not provided is connected,
⁺ Leakage current from the portion where the high concentration region 79 is provided can be suppressed. Therefore, a low on-voltage and a low leakage current can be realized simultaneously.

It is also possible to combine the second embodiment with the third or fourth embodiment. Note that, in the above embodiment, Si
Although only the example of CSBD has been given, the present invention is not limited to silicon SBD.
There is no problem in applying it to.

[0040]

As described above, according to the present invention, an anode electrode of a metal forming a Schottky junction is arranged on the surface of the first conductive type semiconductor layer, and the ohmic electrode is formed on the back side of the first conductive type semiconductor layer. In the Schottky barrier diode provided with a suitable cathode electrode, the second conductivity type buried region that does not reach the surface inside the first conductivity type semiconductor layer below the anode electrode is spaced apart such that the depletion layer is continuous at the time of reverse bias. By making the buried region of the second conductivity type the same potential as the anode electrode, it is possible to realize a Schottky barrier diode having both low on-voltage and low leakage current.

The anode electrode may be composed of a first barrier metal having a large barrier height and a second barrier metal having a small barrier height, or may have an impurity concentration higher than that of the first conductive type semiconductor layer above the second conductive type buried region. By providing the high-concentration region of the first conductivity type having a high SBD, it is possible to obtain an SBD in which the relationship between the ON voltage and the leakage current is further improved.

The present invention which can realize a Schottky barrier diode having a low on-voltage and a low leakage current has a high breakdown voltage,
This has great significance in expanding the applications of Schottky barrier diodes as high-speed switching devices.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of a SiCSBD according to a first embodiment of the present invention.

FIG. 2A is a plan view of the SiCSBD of the first embodiment, and FIG. 2B is a cross-sectional view taken along line AA.

FIGS. 3A to 3D show SiCS of the first embodiment.
Sectional drawing in order of manufacturing process of BD manufacturing method

4 (a) to 4 (f) are cross-sectional views in the order of manufacturing steps by another manufacturing method of SiCSBD.

FIG. 5 is a partial sectional view of a SiCSBD according to a third embodiment of the present invention.

FIG. 6 is a partial cross-sectional view of a SiCSBD according to a fourth embodiment of the present invention.

FIG. 7 is a partial cross-sectional view of a SiCSBD according to a fifth embodiment of the present invention.

FIG. 8 is a partial cross-sectional view of a conventional low leakage current SiCSBD.

FIG. 9 is a partial cross-sectional view of a conventional low on-voltage SiCSBD.

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 71 n ⁺ substrate layer 12, 22, 32, 42, 52, 62, 72 n epitaxial layer 13 p ⁺ anode region 15, 35, 45, 65, 75 anode electrode 16, 26, 36, 46, 56, 66, 76 Cathode electrode 25a, 55a First barrier metal 25b, 55b Second barrier metal 28 Trench 33, 43, 53, 63, 73p ⁺ embedded region 33a, 34a, 43a, 44a Boron ions 34, 44, 54, 64, 74 p ⁺ contact region 37p ⁺ guard ring 38, 48a, 48b silicon oxide film 42an n epitaxial layer 69, 79n ⁺ high concentration region

Claims (9)

[Claims] 1. A Schottky barrier diode in which a metal anode electrode forming a Schottky junction is arranged on the surface of a first conductivity type semiconductor layer and an ohmic cathode electrode is provided on the back side of the first conductivity type semiconductor layer. In the first conductive type semiconductor layer below the anode electrode, a second conductive type buried region that does not reach the surface is formed at an interval such that the depletion layer is continuous at the time of reverse bias, and the second conductive type buried region is formed. A Schottky barrier diode, wherein a region has the same potential as an anode electrode. 2. An anode electrode comprising a first barrier metal having a small barrier height and a second barrier metal having a large barrier height, wherein the first barrier metal is arranged at least partially above the buried region of the second conductivity type. The Schottky barrier diode according to claim 1, wherein 3. The Schottky according to claim 1, further comprising a first conductivity type high concentration region having a higher impurity concentration than the first conductivity type semiconductor layer above the second conductivity type buried region. Barrier diode. 4. The Schottky barrier diode according to claim 3, wherein an anode electrode is in contact with the surface of the first conductivity type high concentration region. 5. The method according to claim 5, further comprising:
The Schottky barrier diode according to any one of claims 1 to 4, further comprising a second conductivity type contact region that connects the second conductivity type buried region and the anode electrode. 6. The Schottky barrier diode according to claim 1, wherein the first conductivity type semiconductor layer is made of silicon. 7. The Schottky barrier diode according to claim 1, wherein the first conductivity type semiconductor layer is made of silicon carbide. 8. An anode electrode of a metal forming a Schottky junction provided on the surface of the first conductivity type semiconductor layer, an ohmic cathode electrode provided on the back surface side, and the first conductive layer below the anode electrode. In the method for manufacturing a Schottky barrier diode having a second conductivity type buried region that does not reach the surface formed inside the type semiconductor layer, the second conductivity type impurity is ion-implanted from the surface of the first conductivity type semiconductor layer. Forming a second conductivity type buried region by the method. 9. A metal anode electrode for forming a Schottky junction provided on the surface of the first conductivity type semiconductor layer, an ohmic cathode electrode provided on the back side, and the first conductive layer below the anode electrode. In the method of manufacturing a Schottky barrier diode having a second conductivity type buried region that does not reach the surface formed inside the type semiconductor layer, the first conductivity type semiconductor layer is epitaxially grown after ion implantation of the second conductivity type impurity. Forming a buried region of the second conductivity type.