JPH0395826A - Semiconductor electron emitting element - Google Patents

Abstract

PURPOSE:To easily attain stable electron emission characteristics by providing a P<+> region and a plurality of N<+> regions formed with the P<+> region to prevent them from contacting the P<+> region in a P-type semiconductor layer and forming a Schottky barrier electrode on the P<+> region. CONSTITUTION:A P<+> region 5 and a plurality of N<+> regions 3 formed with the P<+> region interposed to prevent them from contacting the P<+> region 5 are provided in a P-type semiconductor layer 4, while a Schottky barrier electrode b is formed on the P<+> region 5. Electrons generated by avalanche amplification obtain energy higher than lattice temperature by an electric field in a depletion layer 2 and are injected into a Schottky electrode 6 made of a low work function material. The electrons which do not lose energy due to lattice scattering and have energy larger than the work function of the Schottky electrode 6 surface are emitted into vacuum from the surface of the Schottky electrode.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor electron-emitting device.

[Prior Art] Among conventional semiconductor electron-emitting devices, one that uses avalanche amplification is disclosed in, for example, U.S. Pat. No. 4,259,678.
and US Pat. No. 4,303,930.

This semiconductor electron-emitting device emits electrons by forming a P-type semiconductor layer and an N-type semiconductor layer on a semiconductor substrate, and depositing cesium or the like on the surface of the N-type semiconductor layer to lower the work function of the surface. A reverse bias voltage is applied to both ends of a diode formed by a P-type semiconductor layer and an N-type semiconductor layer to cause avalanche amplification, thereby making the electrons hotter and causing them to flow from the electron-emitting region to the semiconductor substrate. It emits electrons in a direction perpendicular to the surface.

[Problems to be Solved by the Invention] However, the conventional semiconductor electron-emitting device described above has the following drawbacks because cesium, which is used to form the electron-emitting portion, is a chemically extremely active element. was there.

■Ultra-high vacuum (IX 1 0-1
0 Torr or higher).

■Life span, efficiency, etc. strongly depend on the degree of vacuum.

■The device cannot be exposed to the atmosphere.

Furthermore, in conventional semiconductor electron-emitting devices, the structure is such that electrons that have gained high energy through avalanche amplification pass through the N-type semiconductor layer and reach the surface of the electron-emitting region. There was also the drawback that it was lost due to lattice scattering within the layer. In order to suppress this energy loss, it is necessary to form an extremely thin N-type semiconductor layer (less than 200 layers), but it is difficult to manufacture such an extremely thin N-type semiconductor layer with uniformity, high concentration, and low defects. Therefore, the problem was that it was difficult to stably fabricate the device. Furthermore, due to structural and manufacturing process problems, it has been difficult to form the electron-emitting region in the cross section of the semiconductor substrate (that is, in the direction of the side surface of the substrate). SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a substrate cross-sectional emission type electron-emitting device that can easily achieve stable electron-emitting characteristics.

[Means for Solving the Problems] The gist of the present invention is to have a P-type semiconductor layer formed on a semiconductor substrate, a P+ region and a plurality of P+ regions formed in the P-type semiconductor layer with the P+ region sandwiched therebetween. N3 regions, and the P1
A semiconductor electron-emitting device is characterized in that a Schottky barrier electrode is formed on a region.

[Function] The semiconductor electron-emitting device of the present invention uses a material for lowering the work function of the surface of the electron-emitting part (hereinafter referred to as a low-work function material).
Since the doped region is used as a Schottky electrode for the P-type semiconductor, an electron emitting region can also be formed in the cross-sectional direction of the semiconductor substrate, and multiple electron emitting regions can be formed in the same device. .

In addition, since we used an element that is extremely stable even in the atmosphere as a low work function material, we do not need an ultra-high vacuum to achieve stable operation, and the lifespan and efficiency do not strongly depend on the degree of vacuum. It is also possible to expose it to the atmosphere.

Conventionally invented semiconductor electron-emitting devices use a PN junction, so there is a lot of energy loss within the N-type layer.
Materials with extremely low work functions had to be used. Therefore, in practice, only cesium and the like have been used. On the other hand, in the present invention, since a Schottky junction is used, the energy loss is smaller than in the conventional example.
s,GdBa1//Si2,7i3i2,ZrSi
2, GfSi2, etc. can be used. Examples of low work function materials that can be used in the present invention include metals of groups IA, 2A, 3A and lanthanoids, silicides, borides, carbides and the like of groups 1A, 2A, 3A and lanthanides. Specifically, TfC, ZrC, H f C, La B
6 SmBs Gd BsWSL2, TiS
i2, ZrSi2, GfSi2, etc. can be used.

Furthermore, unlike conventional semiconductor electron-emitting devices, the structure is not such that electrons that have gained high energy through avalanche amplification pass through the N-type semiconductor layer and reach the surface of the electron-emitting region, so the N-type semiconductor layer is extremely thin. < (200 people or less) There are no manufacturing difficulties such as the need to conduct a production process, and therefore, semiconductor electron-emitting devices can be stably produced.

Hereinafter, the present invention will be explained in detail using FIG. 1 and FIG. 2.

FIG. 1 is a diagram for explaining the operating principle of the semiconductor electron-emitting device of the present invention, and is a conceptual diagram showing an example of the configuration of the semiconductor electron-emitting device of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a depletion layer region, 3 is an n+ region, 4 is a P-type semiconductor layer,
5 is a P'' region, 6 is a Schottky electrode, 8 is an n-type ohmic electrode, and 9 is a P-type ohmic electrode.

In addition, examples of semiconductor materials used in the electron-emitting device of the present invention include Si, Ge, GaAs, GaP, and AJZ.
As%GaAsP%AJ2GaAs, SiC, BP, etc. may be used, but any material may be used as long as it can form a P-type semiconductor, and indirect transition type materials with a large band gap are particularly suitable.

Furthermore, FIG. 2 is a conceptual diagram showing energy bands near the surface of the semiconductor electron-emitting device of the present invention.

First, the electron emission process in the semiconductor electron-emitting device of the present invention will be explained with reference to FIG.

By applying a reverse bias to a Schottky diode made of a P-type semiconductor and a low work function material, the bottom EC of the conduction band of the P-type semiconductor is brought to the vacuum level E of the Schottky electrode.
The energy level is higher than VAC. Electrons generated by avalanche amplification gain energy higher than the lattice temperature due to the electric field in the depletion layer generated at the semiconductor/body-metal electrode interface, and are injected into the Schottky electrode made of a low work function material. Electrons that do not lose energy due to lattice scattering or the like and have energy greater than the work function of the Schottky electrode surface are emitted into vacuum from the Schottky electrode surface (ie, the electron emitting portion).

In the semiconductor discharge device of the present invention, as shown in FIG.
N+ near the interface with the low work function material in the P-type semiconductor substrate
Since the region is provided, a depletion layer is created at the PN" interface. Therefore, the movement path of electrons injected from the P1 layer to the P layer is limited by the depletion layer created at the PN" interface, and the electrons are formed in the electron emitting region. Since the current is concentrated in the P+ region, it is easy to increase the current density.

In addition, in the semiconductor discharge device of the present invention, in the device fabrication process, the P0 region and the N+ region, which become electron emitting regions,
It can be formed from the semiconductor surface by ion implantation, etc.
A plurality of electron emitting parts can be formed at arbitrary positions on the same plane of the same substrate.

Furthermore, in the present invention, since the surface of the low work function material that will become the electron-emitting region and the P area immediately below it can be formed in the cross section of the semiconductor substrate that is the base material, the electron emission direction can be made perpendicular to the cross section. I can do it. In addition, in order to use the cross section of the substrate, for example, from one element to each horizontal direction, 9
It becomes possible to obtain electron beams that are emitted separately in four directions shifted by 0°.

Furthermore, since desired semiconductor layers can be sequentially deposited on the surface of the semiconductor substrate by, for example, the MBE (molecular beam epitaxial) method, it is easy to fabricate a device in which electron-emitting parts are stacked. Multiple electron-emitting regions can be formed in a direction perpendicular to the substrate surface. [Example] (Example 1) FIG. 3 is a schematic diagram showing a semiconductor electron-emitting device according to an example of the present invention, and FIG. 3(a) is a perspective view schematically showing a part of the device. Figure 3(b) is a cross-sectional view taken through the electron-emitting part and parallel to the substrate surface, and Figure 3(C) is a cross-sectional view taken through the electron-emitting part and perpendicular to the substrate surface. be. In each figure, 101 is an nGaAs substrate, 1
02 is a P-GaAs layer, 103 is a P0 region, 104 is a P0 region for ohmic electrode, 105 is an n0 region, 106 is an n layer, 107 is a Schottky electrode, 108 is an n-type ohmic IIE electrode, and 109 is a P-type ohmic electrode. It is a good electrode.

-Hereinafter, the manufacturing process of the semiconductor discharge device shown in FIG. 3 will be explained using FIG. 4.

■Si-doped N” with impurity concentration of 5X10”cm-’
- On the GaAs substrate 401, the impurity concentration is reduced to 1 x 10"a by MBE (molecular beam epitaxial) method or Mo-CVD (organic metal chemical vapor deposition).
A P--GaAS layer 402 doped with Be was epitaxially grown so that the p--GaAS layer 402 was doped with Be.

■Next, P' region 4 for defining avalanche amplification
In order to form 03, a Be" ion beam of 90 keV focused to a diameter of 0.1 μm or less is irradiated onto a predetermined position from the surface of the P--GaAs layer, and the Be" is 2xlO"cm-
'Injected. Further, in order to form a P" region 404 for an ohmic electrode, a focused Be+ ion beam of 40 keV was irradiated in the same manner, and Be" was implanted by 3xlO"am".

■Next, the N1 area 405 that can reach the N+ board 401
40 µm or less in diameter to form
A 0 keV Si” ion beam is irradiated to a predetermined position, and the I
Only X 10"Cm-" was injected.

■Then, by RTA (Rapid Thermal Annealing) method,
The injection part was activated at 900°C for 3 seconds (see Figure 4).
a)).

■ St-doped N''-GaAs layer 406 with impurity concentration of 5X10l6cm-' is formed by MBE method or MO-C
Evitaxial growth was performed using the VD method.

(2) For electrode wiring, the upper part of the P+ region 404 for the ohmic t-electrode was removed and exposed by ordinary tritho-etching.

■Processed the cross section of the sample to form a Schottky electrode. For processing, the resist was buttered by normal photolithography, and then etched by RIBE (reactive ion beam etching) using Ce- ions perpendicular to the sample surface and sufficiently reaching the N0 substrate 401 ( Figure 4(b)). Note that in this example, the RI BE method was used as the method for forming the sample cross section, but
Other etching methods or scribing methods may be used as long as the formed cross section is smooth and does not cause damage or contamination to the sample side.

■ Form a Schottky barrier against the P-type GaAs from a direction perpendicular to the previously formed sample cross section, and use a low work function material (LaB. was used in this example) to a thickness of 100 mm. A Schottky electrode 407 was formed by electron beam evaporation as described above.

[Phase] Finally, A as N type talented Mick%EVi408
A u-Ge alloy and an Au-Zn alloy as the P-type ohmic electrode 409 were formed by vacuum evaporation and photolithography etching, respectively, and alloying treatment was performed at 400° C. for 3 minutes.

An operation test was conducted on the semiconductor electron-emitting device manufactured by the above manufacturing process.

First, this semiconductor electron-emitting device is
The device was placed in a vacuum chamber that was evacuated to a temperature of 1×10 Torr, and then a phosphor substrate was placed opposite the Schottky electrode of the device, and the vacuum chamber was evacuated to 1×lO−′ Torr. ，
Next, a voltage was applied to the phosphor substrate so that the accelerating voltage for the element was +3KV, and a voltage was applied to the Ohmic electrodes 408 and 409 so as to create a reverse bias. Luminescence from the body substrate was observed. The amount of emitted current at this time was about 1 nA.

(Embodiment 2) FIG. 5 is a schematic perspective view showing a second embodiment of the present invention. In this embodiment, two sample cross sections for emitting electrons are formed on a semiconductor electron-emitting device, and a plurality of P regions for roughly defining avalanche amplification are formed on each sample cross section. Note that in FIG. 5, the Schottky electrode is omitted.

The manufacturing method was the same as that shown using FIG.

When we conducted an operation test of this device, we found that P0 of each sample cross section
Electron emission was confirmed from each location where region 503 was formed.

Although this example shows the case where two sample cross sections are formed, it is also possible to have three or more sample cross sections, and furthermore, the position or angle of the sample cross sections can be set arbitrarily. is also possible.

In addition, although this example shows the case where multiplication is performed only in the horizontal direction to the substrate surface, by repeating ion implantation into the FL layer of the semiconductor layer, multiplication is simultaneously performed in the vertical direction to the substrate surface. It is also possible to do so.

[Effects of the Invention] As explained above in detail, according to the electron-emitting device of the present invention, the electron-emitting portion can be arbitrarily limited, and furthermore, a plurality of electron-emitting portions can be formed on the same substrate at the same time. can be formed.

Further, according to the electron-emitting device of the present invention, it is possible to emit electrons in a direction perpendicular to the cross section of the sample, and furthermore, by providing the electron-emitting cross section in a plurality of different directions, it is possible to emit electrons in a direction perpendicular to the cross section of the sample. It is possible to emit electrons independently.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the operating principle of the semiconductor electron-emitting device of the present invention, FIG. 2 is a conceptual diagram showing the energy band near the surface of the semiconductor electron-emitting device of the present invention, and FIG.
Figure (a) is a perspective view schematically showing a part of this device, Figure 3 (b) is a cross-sectional view taken parallel to the substrate surface through the electron emission region, and Figure 3 (C) is a perspective view schematically showing a part of the device. FIG. 4 is a cross-sectional view taken perpendicularly to the substrate surface through the emission part, and FIG. 4 is a diagram for explaining the manufacturing process of the semiconductor discharge device shown in FIG. 3.
The figure is a schematic perspective view showing a second embodiment of the invention. 1... Semiconductor substrate, 2... Depletion layer region, 3... n
ゝRegion, 4... P-type semiconductor layer, 5... P3 region, 6
...Schottky electrode, 8...n-type ohmic electrode, 9...P-type ohmic electrode, 101...n"G
aAs substrate, 10:l...P-GaAs layer, 1 0 3
-P+ region, 104... P1 region for ohmic electrode,
105...n3 region, 106...n3 layer, 107.
...Schottky electrode, 108...n type ohmic electrode, 109...p type ohmic electrode, 401...N
-GaAs substrate, 402-P--GaAs layer, 40
3・P” area, 404...P for Saiichi Mic electrode
"Area, 4 0 5 ・N""Area,406...N"
-GaAs layer, 407... Schottky electrode, 40
8...N-type ohmic electrode, 409...P-type ohmic electrode, 501...-N''-GaAs substrate, 502-
P--GaAs layer, 503...P+ region, 504.
...P+ region for ohmic electrode, 505...N+ region, 506...N3-GaAs layer, 508...N type ohmic electrode, 509...P type ohmic electrode. Figure 1 Figure 2 Figure 3 (b) (C) Figure 5

Claims (5)

[Claims] (1) having a P-type semiconductor layer formed on a semiconductor substrate,
The P-type semiconductor layer has a P^+ region and a plurality of N^+ regions formed sandwiching the P^+ region so as not to be crowded with the P^+ region, and the P^+ A semiconductor electron-emitting device characterized in that a Schottky barrier electrode is formed on a region. (2) The semiconductor electron-emitting device according to claim 1, wherein the P^+ region, the N^+ region, and the Schottky barrier electrode are formed on a side surface of the P-type semiconductor layer. (3) Having a plurality of the above P^+ areas, each of the P^
3. The semiconductor electron-emitting device according to claim 1, wherein the + region has a plurality of N^+ regions sandwiching the P^+ region. (4) having a plurality of P-type semiconductor layers, having at least one Schottky barrier electrode on a side surface of a stack formed by the plurality of P-type semiconductor layers, and having a side surface of each of the P-type semiconductor layers; 4. The semiconductor electron-emitting device according to claim 1, wherein the P^+ region and the N^+ region are formed. (5) The semiconductor electron-emitting device according to any one of claims 1 to 4, wherein the P^+ region, the N^+ region, and the Schottky barrier electrode are formed on a side surface of the P-type semiconductor layer.