JPH0364078A - Semiconductor light emitting element - Google Patents
Semiconductor light emitting elementInfo
- Publication number
- JPH0364078A JPH0364078A JP1200481A JP20048189A JPH0364078A JP H0364078 A JPH0364078 A JP H0364078A JP 1200481 A JP1200481 A JP 1200481A JP 20048189 A JP20048189 A JP 20048189A JP H0364078 A JPH0364078 A JP H0364078A
- Authority
- JP
- Japan
- Prior art keywords
- region
- light emitting
- type semiconductor
- junction
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 230000015556 catabolic process Effects 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 8
- 230000005684 electric field Effects 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000003031 high energy carrier Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、プレ−ナー型ＰＮ接合を有し、このＰＮ接合
に逆バイアスを印加し、電子なだれ降伏を生じさせるこ
とによって光を発する半導体光放出素子に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a semiconductor that has a planar PN junction and that emits light by applying a reverse bias to the PN junction to cause electron avalanche breakdown. It relates to a light emitting device.
［従来の技術］
従来より、アバランシェ状態からの光放出は、学術論文
Ｐｈｙｓ、Ｒｅｖ、 、Ｖｏｌ、１０２．Ｐ２Ｓ５，１
９５６゜’Ｐｈｏｔｏ ｅｍｉｓｓｉｏｎ ｆｒｏｍ
ａｖａｌａｎｃｈｅ ｂｒｅａｋ ｄｏｗｎ」、Ａ、Ｇ
、Ｃｈｙｎｏｗｅｔｈ、ａｎｄ Ｈ，に、ｌ１ｌｃｋｅ
ｙ等において報告されている。一方、この光放出現象を
光放出半導体素子として応用した例として、（：ｏｎｆ
、Ｐｒｏｃ。[Prior Art] Conventionally, light emission from an avalanche state has been described in the academic paper Phys, Rev., Vol. 102. P2S5,1
956゜'Photo emission from
Avalanche break down”, A, G
, Chynoweth, and H., l1lcke
It has been reported in y et al. On the other hand, as an example of applying this light emission phenomenon to a light emission semiconductor device, (:onf
, Proc.
ＩＥＥＥ、ｓｏｕ ｔｈｅａｇｔｃｏｎ、Ｐ２Ｓ５，１
９８８ ’Ａｓｔｕｄｙ ｏｆｔｈｅ ｎａｔｕｒｅ
ａｎｄ ｃｈａｒａｃｔｅｒｉｓｔｉｃｓ ｏ
ｆ Ｌｉｇｈｔｒａｄｉａｔｉｏｎ ｉｎ ｒｅ
ｖｅｒｓｅ−ｂｉａｓｅｄ ５ｉｌｉｃｏｎｊｕｎｃ
ｔｉｏｎｓＪ Ｃ，Ｂ、Ｗｉｌｌｉａｍｓ ａｎｄ
Ｋ、Ｄａｎｅｓｈｖｅｒ が知られている。この論
文においては、ＳｉのＰＮ接合界面における光放出強度
は、０．０１Ｗ／ｃｍ”であると報告されている。そし
て、これらの文献の半導体素子は、 Ｓ、Ｍ、Ｓｚｅ著
ｒ Ｐｈｙｓｉｃｓ ｏｆｓｅｍｉｃｏｎｄｕｃｔｏｒ
ＤｅｖｉｃｅＪＪｏｈｎ ９１ｉ１ｅｙ＆５ｏｎｓ
Ｐ７３に記載されているようなプレ−ナー型のＰＮ接合
で構成されていた。IEEE, so theagtcon, P2S5,1
988 'Study of the nature
and characteristics o
f Lightradiation in re
verse-biased 5iliconjunc
tionsJ C, B, Williams and
K. Daneshver is known. In this paper, it is reported that the light emission intensity at the Si PN junction interface is 0.01 W/cm''.The semiconductor devices in these documents are
DeviceJJohn 91i1ey&5ons
It was composed of a planar type PN junction as described in P.73.
［発明が解決しようとしている問題点］しかしながら、
上記従来例は、その構成がプレ−ナー型ＰＮ接合である
ため、接合部の周囲に円筒状の曲率な持つ部分や球状の
曲率を持つ部分が存在していた。そして、接合部に作用
する電界は、平面状の接合部よりも球状の曲率なもつ部
分や円筒状の曲率を持つ部分の方が高いので、アバラン
シェ降伏現象による光放出はこの高い電界領域、即ち接
合部の周囲でのみ生じ、接合部を均一に光らせることは
出来なかった。また、このようなプレ−ナー接合では、
接合を形成する時のバターニング形状の不均一に伴なう
電界集中による発光や、欠陥等に伴なう電界集中による
発光があり、偶発的な要素による発光が素子発光の光強
度や光の発光場所を支配する。このため、制御性よく光
放出デバイスを形成することは出来なかった。[Problem that the invention seeks to solve] However,
Since the conventional example described above has a planar type PN junction, there are parts with cylindrical curvature and parts with spherical curvature around the joint. The electric field acting on a junction is higher in a part with spherical curvature or a part with cylindrical curvature than in a planar joint, so light emission due to avalanche breakdown occurs in this high electric field region, i.e. It occurred only around the joint, and it was not possible to make the joint glow uniformly. In addition, in such a planar joint,
There is light emission due to electric field concentration due to uneven patterning shape when forming a bond, and light emission due to electric field concentration due to defects, etc., and light emission due to accidental factors may affect the light intensity of device light emission or the light intensity. Control the luminous location. For this reason, it was not possible to form a light emitting device with good controllability.
本発明の目的は、上記従来技術の問題点を解決し、制御
性良く作製することが出来、均一な発光を行なう半導体
光放出素子を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above, to provide a semiconductor light emitting device that can be manufactured with good controllability and emits uniform light.
［問題点を解決するための手段］
本発明の上記目的は、ｎ型半導体の表面に、プレ−ナー
型ＰＮ接合を形成するようにｐ型半導体層を設けて成り
、前記ＰＮ接合に逆バイアスを印加し、電子なだれ降伏
を生じさせることによって光を発する半導体光放出素子
において、前記ＰＮ接合の平面部の一部に、他の部分よ
りも降伏電圧の低い領域を設けることによって達成され
る。[Means for Solving the Problems] The above object of the present invention is to provide a p-type semiconductor layer on the surface of an n-type semiconductor so as to form a planar PN junction, and to apply a reverse bias to the PN junction. In a semiconductor light-emitting device that emits light by applying a voltage to cause electron avalanche breakdown, this is achieved by providing a region in a part of the plane part of the PN junction with a lower breakdown voltage than the other part.
［実施例］
第１図（Ａ）及び第１図（Ｂ）は、夫々本発明の半導体
光放出素子の第１実施例を示す平面図及びＡ−Ａ’部に
おける断面図である。このような素子は、以下のような
プロセスで作製された。[Example] FIG. 1(A) and FIG. 1(B) are a plan view and a cross-sectional view taken along the line AA', respectively, showing a first example of a semiconductor light emitting device of the present invention. Such an element was manufactured by the following process.
まず、ｎ型半導体基体ｌ（本実施例ではＧａＡｓ（１０
０） ）上に、３ ｘ １０ ”ｃｍ−３の不純物濃度
を持つｎ型半導体層２を１分子線エピタキシー（ＭＢＥ
）！＆長によって形成した。そして、フォトリソグラフ
ィーのレジストプロセスを用いて、領域３の位置のフォ
トレジストを開口し、ここにＳｉイオンを８０ ＫｅＶ
の加速電圧で注入した。更に、同様なレジストプロセス
を用いて領域５の位置のフォトレジストを開口しここに
Ｚｎイオンを４０ ＫｅＶの加速電圧で注入した。First, an n-type semiconductor substrate l (in this example, GaAs (10
0) ), an n-type semiconductor layer 2 having an impurity concentration of 3 x 10"cm-3 is formed by single molecular beam epitaxy (MBE).
)! Formed by & long. Then, using a resist process of photolithography, the photoresist at the position of region 3 is opened, and Si ions are injected here at 80 KeV.
was injected at an accelerating voltage of Furthermore, using a similar resist process, the photoresist at the position of region 5 was opened, and Zn ions were implanted therein at an accelerating voltage of 40 KeV.
次に、これをアルシン雰囲気中で８５０℃−３０ｓｅｃ
のアニールな行ない、不純物原子を活性化した。そして
領域３を、不純物濃度のピーク値が約Ｉ Ｘ １０１ａ
ｃＩｌ−”の高濃度ｎ型領域に領域５を不純物濃度のピ
ーク値が約ｌｘ１０ ”ｃｍ−”以上のｐ型半導体層と
した。高濃度ｎ型領域３の大きさは直径５ｐｍ以下が望
ましく、これ以上の大きさでは均一な光放出が得られず
、また発熱が大きかった。また、ｐ型半導体層５の厚さ
は０．１μｍ以下とするのが望ましく、これ以上では光
の透過率が急激に低下した。Next, this was heated at 850°C for 30 seconds in an arsine atmosphere.
Annealing was performed to activate the impurity atoms. Then, in region 3, the peak value of impurity concentration is about I x 101a
The region 5 is formed into a p-type semiconductor layer with a peak impurity concentration of approximately lx10 cm- or more in the highly-concentrated n-type region of cIl-''.The size of the highly-concentrated n-type region 3 is preferably 5 pm or less in diameter; If the size is larger than this, uniform light emission cannot be obtained and a large amount of heat is generated.Also, it is desirable that the thickness of the p-type semiconductor layer 5 is 0.1 μm or less, and if it is larger than this, the light transmittance will decrease. It declined rapidly.
上述の半導体層上に、絶縁層９をＳｉＯ２のスパッタで
形成し、同様なレジストプロセスを用いて所定の位置の
フォトレジストを開口した。そして、この上にＣｒ ／
Ａ ｕを蒸着して。An insulating layer 9 was formed on the above semiconductor layer by sputtering SiO2, and a similar resist process was used to open the photoresist at a predetermined position. And on top of this Cr/
Deposit Au.
適当にエツチングで不要部分を取り除き、Ｐ型半導体へ
のオーくツクコンタクト電極６を形成した。そして、こ
の電極６に接続して、ＡｆＬのコンタクト電極１１を形
成した。また、基体ｌの底面にも、オーミックコンタク
ト電極８を形成した。このように作製された素子に、電
極６及び８を介して電源７より逆バイアスの電界を印加
すると、領域３の上方より光ｈアを放出した。Unnecessary portions were removed by appropriate etching to form an open contact electrode 6 to the P-type semiconductor. Then, connected to this electrode 6, an AfL contact electrode 11 was formed. Furthermore, an ohmic contact electrode 8 was also formed on the bottom surface of the base 1. When a reverse bias electric field was applied from the power supply 7 to the device thus manufactured through the electrodes 6 and 8, light ha was emitted from above the region 3.
次に、本発明の素子の動作について説明する。Next, the operation of the device of the present invention will be explained.
第３図は、本発明の半導体光放出素子のエネルギーバン
ド図である。第３図に示すように、ｎ型半導体層にｐ型
半導体層を接合し、逆バイアスを印加することにより、
アバランシェ降伏な生ぜしめると、空乏層内で電子とホ
ールが多数生成される。この生成された電子やホールは
、第４図に示される様に、（ａ）で示される通常のバン
ド間遷移だけでなく、（ｂ）に示される高いエネルギー
を持つキャリアの再結合、或は、（Ｃ）に示されるバン
ド内遷移により光が放出される。FIG. 3 is an energy band diagram of the semiconductor light emitting device of the present invention. As shown in FIG. 3, by joining a p-type semiconductor layer to an n-type semiconductor layer and applying a reverse bias,
When avalanche breakdown occurs, many electrons and holes are generated within the depletion layer. As shown in Figure 4, these generated electrons and holes not only undergo the normal interband transition shown in (a), but also the recombination of high-energy carriers shown in (b), or , (C), light is emitted by the intraband transition shown in FIG.
そこで本発明では、ｎ型半導体層に他領域と異なる高濃
度ｎ型領域３を設けることで、第１図（Ｂ）に破線４で
示されるような空乏層を形成した。そして、この高濃度
ｎ型領域３全体に均一かつ高電界領域を形威することに
よって、光放出がこの高濃度領域でのみ均一に生じるよ
うにしたものである。Therefore, in the present invention, a depletion layer as shown by the broken line 4 in FIG. 1(B) is formed by providing a high concentration n-type region 3 different from other regions in the n-type semiconductor layer. By forming a uniform high electric field region over the entire high-concentration n-type region 3, light emission occurs uniformly only in this high-concentration region.
また、本発明においては、前述のように高濃度領域を設
けることによって、高い電界を形成し、電子−ホール対
の生成効率を高めて光放出の確率を増加させて輝度制御
を行なうとともに、電子−ホールに大きなエネルギーを
与えることで、バンドギャップＥｇよりも大きなエネル
ギーを持つ光の放出が可能となった。In addition, in the present invention, by providing a high concentration region as described above, a high electric field is formed, the generation efficiency of electron-hole pairs is increased, the probability of light emission is increased, and the brightness is controlled. - By giving a large amount of energy to the hole, it became possible to emit light with an energy larger than the band gap Eg.
更に、本発明では、半導体基体としてｎ型半導体を用い
たことにより、表面のｐ型半導体直下に最も高い電界が
形成されるため、ｐ型半導体内の小数キャリアである電
子が最もアバランシェ増幅に作用する。このため、キャ
リアの種類により電子−ホールベアの生成効率が異なり
、電子により電子−ホールベアが生成される確率がホー
ルにより電子−ホールベアが生成される確率よりも大き
いような基板（例えばシリコン）を用いる場合１本発明
のような構成にすることで、電子の生成効率を高めるこ
とが出来る。Furthermore, in the present invention, by using an n-type semiconductor as the semiconductor substrate, the highest electric field is formed directly under the p-type semiconductor on the surface, so that electrons, which are minority carriers in the p-type semiconductor, have the greatest effect on avalanche amplification. do. For this reason, the generation efficiency of electron-hole bears varies depending on the type of carrier, and when using a substrate (e.g. silicon) in which the probability that electron-hole bears are generated by electrons is greater than the probability that electron-hole bears are generated by holes. 1. By adopting the configuration of the present invention, the electron generation efficiency can be increased.
本発明において、ｐ型半導体層の厚さは、ＰＮ接合界面
で生成した光を十分に透過し、光の透過損失を減少させ
るため、極めて薄く形成される必要がある。In the present invention, the p-type semiconductor layer needs to be formed extremely thin in order to sufficiently transmit light generated at the PN junction interface and reduce light transmission loss.
以上述べた構成により、第２図に示すような光エネルギ
ーと光強度との関係を持つ光放出素子を制御性良く作製
することが可能になった。With the configuration described above, it has become possible to fabricate a light emitting element having a relationship between light energy and light intensity as shown in FIG. 2 with good controllability.
第５図に１本発明の第２の実施例を示す、第５図は、第
１図（Ｂ）と同様に素子の断面図を示す、また、第５図
において、第１図（Ｂ）と同一の部材には同一の符号を
付した。このような素子は、以下のプロセスで作製され
た。FIG. 5 shows a second embodiment of the present invention. FIG. 5 shows a cross-sectional view of the element similarly to FIG. 1(B). The same members are given the same reference numerals. Such an element was manufactured by the following process.
まず、ｎ型半導体基体！（本実施例では５ｉ（１００）
）上に５ Ｘ ｌ Ｏ”Ｃｍ−”の不純物濃度を持つ
ｎ型半導体層２を気相成長（ＣＶＤ）法にてエピタキシ
ャル成長させて形成した０次にＳｉｎ。First, the n-type semiconductor substrate! (5i (100) in this example)
) is formed by epitaxially growing an n-type semiconductor layer 2 having an impurity concentration of 5XlO"Cm-" on it by a vapor phase growth (CVD) method.
を、熱拡散を用いて４０００人の厚さに形成し、レジス
トプロセスを用いて所定の位置のレジストを開口後、５
ｉｎｓをフッ酸系のエツチング液を用いて取り除き、領
域１０の上部にドーナツ状の開口部を形成した０次に熱
拡散を用いて適当なドーパントを用いてＢ（ボロン）を
拡散し、ｐ型のガードリング領域ｌＯを形成した０次に
光放出部上部のＳｉｎ、領域を前述のレジストプロセス
及びエツチング液を用いて除去し、第１実施例と同様な
手法を用いて、領域３にはＰ（リン）イオンを注入し、
領域５にはＧａ（ガリウム）イオンを注入し、領域３を
不純物濃度のピーク値が約８ Ｘ １０ ”ｃｓ−”の
ｎ型半導体に、領域５を不純物濃度のピーク値が約ｌＸ
１０１９以上のｐ型半導体になるようにした。また、領
域５の厚さが５００Å以下になるように低加速で注入し
、適当なエツチングも行なった０次にオーミックコンタ
クト電極６及び電極８を形成し、光放出素子を構成した
０本実施例のように、高濃度ｎ型領域３の周囲にガード
リング領域１０を構成することで破線４で示される空乏
層を形威し、より一層電界を領域３に集中し。was formed to a thickness of 4,000 mm using thermal diffusion, and after opening the resist at a predetermined position using a resist process,
Ins is removed using a hydrofluoric acid-based etching solution, and a donut-shaped opening is formed in the upper part of the region 10. B (boron) is diffused using an appropriate dopant using zero-order thermal diffusion to form a p-type The area above the 0-order light emitting part where the guard ring area IO was formed was removed using the resist process and etching solution described above, and P was etched in area 3 using the same method as in the first embodiment. (phosphorus) ions are implanted,
Ga (gallium) ions are implanted into region 5, and region 3 is made into an n-type semiconductor with a peak impurity concentration of about 8 x 10 "cs-", and region 5 is made into an n-type semiconductor with a peak impurity concentration of about 1X.
It was made to be a p-type semiconductor of 1019 or more. In addition, a zero-order ohmic contact electrode 6 and an electrode 8 were formed by implantation at low acceleration and appropriate etching so that the thickness of the region 5 was 500 Å or less, and a light emitting device was constructed. By configuring the guard ring region 10 around the heavily doped n-type region 3, a depletion layer shown by the broken line 4 is formed as shown in FIG.
発光効率を向上することが出来た。We were able to improve the luminous efficiency.
［発明の効果］
以上説明したように１本発明は、電子なだれ降伏を用い
る半導体光放出素子において、ＰＮ接合の平面部の一部
に他の部分よりも降伏電圧の低い領域を設けたことによ
って、均一な発光部を制御性良く作製出来る効果が得ら
れたものである。[Effects of the Invention] As explained above, one aspect of the present invention is that, in a semiconductor light emitting device using electron avalanche breakdown, a region having a lower breakdown voltage than other parts is provided in a part of the plane part of the PN junction. , it was possible to produce a uniform light emitting section with good controllability.
第１図（Ａ）及び第１図（Ｂ）は夫々本発明の半導体光
放出素子の第１実施例を示す平面図及び断面図、第２図
は本発明の素子の典型的な光エネルギーと光強度との関
係を示す図２第３図は本発明の素子のエネルギーバンド
を示す図、第４図は本発明の素子における光の発生過程
を説明する図、第５図は本発明の第２実施例を説明する
断面図である。
１−−− ｎ型半導体基体
２ ・・−ｎ型半導体層
３・・・高濃度ｎ型領域
４・・・空乏層
５・・・Ｐ型半導体層
６．８・・・オーミックコンタク
７・・・電源
９・・・絶縁層
１０・・・ガードリング領域
ト電極
富
３
図FIG. 1(A) and FIG. 1(B) are a plan view and a sectional view, respectively, showing a first embodiment of a semiconductor light emitting device of the present invention, and FIG. 2 is a typical light energy diagram of the device of the present invention. FIG. 2 shows the relationship with light intensity. FIG. 3 shows the energy band of the device of the invention. FIG. 4 shows the process of light generation in the device of the invention. FIG. 5 shows the energy band of the device of the invention. It is a sectional view explaining a second example. 1---- N-type semiconductor substrate 2...-N-type semiconductor layer 3...High concentration n-type region 4...Depletion layer 5...P-type semiconductor layer 6.8...Ohmic contact 7...・Power source 9...Insulating layer 10...Guard ring area To electrode wealth 3 Figure
Claims (5)
成するようにｐ型半導体層を設け て成り、前記ＰＮ接合に逆バイアスを印加 し、電子なだれ降伏を生じさせることに よって光を発する半導体光放出素子におい て、 前記ＰＮ接合の平面部の一部に、他の部 分よりも降伏電圧の低い領域を設けたこと を特徴とする半導体光放出素子。(1) A p-type semiconductor layer is provided on the surface of an n-type semiconductor to form a planar PN junction, and light is emitted by applying a reverse bias to the PN junction and causing electron avalanche breakdown. What is claimed is: 1. A semiconductor light emitting device for emitting light, characterized in that a region having a lower breakdown voltage than other portions is provided in a part of the plane portion of the PN junction.
りも不純物濃度の高い領域を設け て成る特許請求の範囲第１項記載の半導体 光放出素子。(2) The semiconductor light emitting device according to claim 1, wherein the region is formed by providing a region having a higher impurity concentration in a part of the n-type semiconductor than in other parts.
よりも厚くした特許請求の範囲第 １項記載の半導体光放出素子。(3) The semiconductor light emitting device according to claim 1, wherein the p-type semiconductor layer around the region is thicker than other parts.
範囲第１項記載の半導体光放出素 子。(4) The semiconductor light emitting device according to claim 1, wherein the size of the region is 5 μm or less.
である特許請求の範囲第１項記載 の半導体光放出素子。(5) The semiconductor light emitting device according to claim 1, wherein the p-type semiconductor layer in the region has a thickness of 0.1 μm or less.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20048189A JP2692971B2 (en) | 1989-08-02 | 1989-08-02 | Semiconductor light emitting device |
| US07/560,769 US5107311A (en) | 1989-08-02 | 1990-07-31 | Semiconductor light-emitting device |
| DE69017301T DE69017301T2 (en) | 1989-08-02 | 1990-08-01 | Semiconductor light emitting device. |
| EP90114775A EP0411612B1 (en) | 1989-08-02 | 1990-08-01 | Semiconductor light-emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20048189A JP2692971B2 (en) | 1989-08-02 | 1989-08-02 | Semiconductor light emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0364078A true JPH0364078A (en) | 1991-03-19 |
| JP2692971B2 JP2692971B2 (en) | 1997-12-17 |
Family
ID=16425033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20048189A Expired - Fee Related JP2692971B2 (en) | 1989-08-02 | 1989-08-02 | Semiconductor light emitting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2692971B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013518402A (en) * | 2010-01-22 | 2013-05-20 | インシアヴァ （ピーテーワイ） リミテッド | Silicon light emitting device and method of manufacturing the device |
-
1989
- 1989-08-02 JP JP20048189A patent/JP2692971B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013518402A (en) * | 2010-01-22 | 2013-05-20 | インシアヴァ （ピーテーワイ） リミテッド | Silicon light emitting device and method of manufacturing the device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2692971B2 (en) | 1997-12-17 |
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