JPH01212111A - Off-set fluctuation preventing circuit - Google Patents

Abstract

PURPOSE:To reduce energy consumption due to battery saving by closing an analog switch and short-circuiting the output terminal and inverting input terminal of an operational amplifier when it is detected by a clock detector that a driving clock is interrupted. CONSTITUTION:An analog switch 18 and a clock detector 19 are added. Namely, the presence and absence of a driving clock phi1 or phi2 of a switched capacitor is decided by the clock detector 19 and when there is no driving clock, the analog switch 18 is closed. Accordingly, for an operational amplifier 15, there is no difference in the bias of a differential pair transistor and the increase of an output off-set due to the unbalanced fluctuation of a transistor threshold VT is not generated. Thus, even when a power source is added to an LSI, the driving clock can be stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to a switched capacitor circuit configured with MOSLSI, in which fluctuations in operational amplifier output offset voltage caused by changes over time in the threshold voltage of a MOS transistor are suppressed. Regarding the circuit to prevent.

[Conventional technology]

In recent years, the miniaturization of LSI circuits has progressed rapidly, and MO
Even in S analog ICs, the size of transistors is becoming smaller and smaller. Therefore, changes in transistor characteristics over time tend to increase. In particular, it has been reported that when the channel length of a transistor is on the order of several micrometers, vT (threshold voltage) fluctuates significantly due to factors such as movement of impurity ions in the gate oxide film by the electric field. (Reference: “5ECONDARY
5LOWTRAPPING-A NEW MOIST
URE INDUCED INSTABILITIES
ENOMENON IN 5CALED ClO2DE
VICES″by M, Noyori et al. 1982 IE
fJ/PROC, IRPS).

A problem with analog LSIs is when the threshold value vT of the transistors constituting the differential pair of the operational amplifier fluctuates in an unbalanced manner between the left and right sides, which causes a noticeable fluctuation in the output offset voltage. ■? The amount of variation varies depending on the bias voltage applied to the transistor. If the inherent short state between the inverting and non-inverting input terminals of the operational amplifier breaks down, a large difference will occur in the bias voltages of the left and right transistors that make up the differential pair, and if this state continues for a long time, the VT Unbalanced fluctuations occur. As a result, the output offset voltage of the operational amplifier increases, which in turn greatly impairs the overall performance of the analog LSI. In order to prevent such problems, it is necessary to ensure that the inverting input terminal and the non-inverting input terminal of the operational amplifier are always short-circuited while power is being applied to the LSI.

[Problem to be solved by the invention]

However, in switched capacitor circuits, which are becoming mainstream in MOS analog LSIs, when a switch is driven or four circuits are interrupted, the inverting input terminal of the operational amplifier almost becomes a direct current oven, and the potential becomes unstable. In this case, while the non-inverting input terminal is always directly connected to the analog ground in a normal switched capacitor filter, the inverting input terminal becomes at a potential different from the analog ground over time due to junction leakage of the switch. fluctuate. From the above, in a switched capacitor circuit, while there is no drive clock, the bias of the differential section of the operational amplifier is greatly different between the left and right sides, and if this state continues for a long time, unbalanced fluctuations in VT will occur.
Output offset voltage increases.

The above phenomenon will be explained below using the drawings. Figure 4 shows
This is a typical example of a normal switched capacitor circuit. Clock φ1. φ2 are exclusive two-phase clocks whose phases are inverted to each other. Drive clock 7φ1. While there is φ2,
Since charge is supplied via a switch or a capacitor, the inverting input terminal 16 and the non-inverting input terminal 17 are in an immanent short state unless the operational amplifier is saturated.

In this state, bias imbalance of the differential pair hardly occurs. However, when the drive clock is interrupted, switches 7 and 8 and switches 8 and 9 are stopped so that when one is ON, the other is always OFF, so the inverting input terminal 16 is open in terms of DC in any case. Become. In this case, the potential of the inverting input terminal 16 converges to a value determined by the junction leak currents in the switches 7 and 8 in the long term, and becomes a potential different from that of the non-inverting input terminal 17. Therefore, a large difference occurs in the biases of the transistors constituting the differential pair, resulting in unbalanced fluctuations in %VT.

An object of the present invention is to prevent the above fluctuations.

[Means to solve the problem]

In the present invention, a means for detecting the presence or absence of a driving clock for the switched capacitor circuit is added to the conventional circuit, and an analog switch is used to short-circuit the inverting input terminal of the operational amplifier to the output terminal only when the driving clock is not detected. This eliminates the bias difference between the differential pair transistors of the operational amplifier, and ■? This prevents an increase in the output offset voltage due to unbalanced fluctuations in the output voltage.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The circuit is the same as the one shown in FIG. 4, except that an analog switch 18 and a clock detector 19 are added. In the present invention, the clock detector 19 determines whether there is a driving clock φ1 or φ2 for the switched capacitor circuit, and if there is no driving clock, the analog switch 18 is closed. As a result, in the operational amplifier 15, there is no difference in bias between the differential pair transistors, and an increase in output offset voltage due to unbalanced fluctuations in VT does not occur. A concrete example of the clock detector 19 is shown in FIG. In FIG. 3, drive clock φ1. When φ2 is operating, switch 2
3, 24 and the capacitor 25, so if the resistance value of the resistor 27 is sufficiently large, the input terminal of the inverter 28 will have a potential exceeding the threshold level of the inverter, and the output 20 will become " It becomes 0” level. On the other hand, when the driving clock is interrupted, the charge accumulated in the capacitor 26 is discharged through the resistor 27, so the input voltage of the inverter 280 decreases and the output terminal 20 becomes the "1" level.

Through the above steps, the presence or absence of the drive clock is determined.

FIG. 3 shows another specific example of the clock detector.

In FIG. 3, when clock φ1 is inputted via inverter 29, capacitor C1, transistor 30 .
31 rectifies the alternating current component, and charges are accumulated in the capacitor C8. If the resistance value of the resistor 27 is sufficiently large, the input voltage to the inverter 280 will exceed the threshold voltage of the inverter, and the output terminal 2.0 will be at the "0" level.

On the other hand, when the driving clock stops, the charge in the capacitor 27 is discharged through the resistor R, and the input voltage of the inverter 28 drops, so that the output terminal 20 becomes the "1" level. The presence or absence of the drive clock is determined through the above steps. The circuit of FIG. 3 differs from the circuit of FIG. 2 in that only one phase of input clock is required. In addition to the circuits shown in FIGS. 2 and 3, many other configurations are possible for the clock detector. However, it is clear that any circuit configuration used as the offset fluctuation prevention circuit is within the scope of the claims of the present invention.

〔Effect of the invention〕

As explained above, by using the present invention, even when there is no driving clock, the biases of the differential pair transistors of the operational amplifier can be kept equal, so that unbalanced power of % VT that changes over time does not occur. Therefore, an increase in the output offset of the operational amplifier can be prevented. Therefore, even when power is applied to the LSI, the driving Q-
), it is possible to reduce current consumption through battery saving.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a clock detector used in the embodiment of the invention, and Fig. 3 is a circuit diagram showing the clock detector used in the embodiment of the invention. Circuit diagram: FIG. 4 is a circuit diagram of a conventional example. 1...Input terminal, 2...Output terminal, 3
...Analog ground, 4, 5, 6, 7, 8,
9,10゜11...Analog switch, 12,
13, 14... Capacitor, 15...
Operational amplifier, 16... Inverting input terminal, 17...
...Non-inverting input terminal, 18...Analog switch, 19...Clock detection circuit, 20...
...Clock detection circuit output terminal, 21.22...
... Clock input terminal, 23, 24 ... Analog switch, 25.26 ... Capacitor, 2
7... Resistor [28, 29... Inverter, 30.31... N-channel transistor. Agent Patent Attorney Uchihara Oneki Now

Claims (1)

[Claims] The switched capacitor circuit includes a clock detector for detecting the presence or absence of a driving clock for the switched capacitor circuit, and an analog switch between an output terminal and an inverting input terminal of an operational amplifier constituting the switched capacitor circuit, and the clock detector The offset fluctuation prevention circuit is characterized in that when it detects that the driving clock is interrupted, the analog switch is closed to short-circuit the output terminal and the inverting input terminal of the operational amplifier.