JPH0512797B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor circuits, and particularly to peak hold circuits.

[Conventional technology]

Conventionally, this type of peak hold circuit connects an input terminal (hereinafter referred to as Vin) to the + input of a comparator 21 and one terminal of an analog switch element 22, respectively, as shown in FIG.
The other terminal of 2 is connected to the negative input of the comparator 21, and a capacitor 2 is connected between this connection point and the ground potential.
Connect 3 and set this as Vout. The output of the comparator 21 is subjected to logic with the control signal Φ inputted for sampling in the gate circuit 24 and is inputted to the gate of the analog switch element 21. Now consider the case where a voltage that changes from the ground potential in the + direction is applied to Vin. Initially, if Vout is OV, then Vin
If becomes even slightly + than OV, comparator 21
The output of becomes "high" level. If the control signal Φ is also "high" level at this time, the analog switch element 22 is made conductive and the capacitor 23 is charged to the level of Vin. This state is when Vin>Vout and It continues when the control signal Φ is at "high" level. Vin＞
When Vout is present, the comparator 21 outputs a "low" level, and the analog switch element 22 becomes non-conductive regardless of the state of the control signal, so that Vout maintains its previous value. Here, since Vout is a high impedance, it is received by an amplifier with a high input impedance.

[Problem that the invention seeks to solve]

The above-described conventional peak hold circuit conducts the analog switch element 22 during the precharging period, that is, when the control signal Φ is at the "high" level, and makes it non-conductive during the comparing period, that is, when the control signal Φ is at the "low" level. When this non-conduction occurs, the following problem occurs. As shown in Figure 4A, if the voltage V _G applied to the gate is higher than the threshold voltage V _T of the analog switch element Mm, the terminal voltage of the capacitor Ch will be applied via the interelectrode capacitance Cd when the gate voltage V _G changes.
Vd is affected, but when it is higher than V _T , the analog switch element Mm is conductive, so the terminal voltage Vd of the capacitor Ch immediately becomes equal to the analog input voltage Vs. However, as shown in Figure 4B, V _G becomes V _T
The analog switch element Mm changes up to
Because it becomes non-conductive, when V _G changes from "high" to "low" level, it pushes down Vd, that is, the peak value stored in capacitor 23, causing a malfunction as if the peak could not be found no matter how long it passed. There are drawbacks to doing so. The conventional peak hold circuit described above conducts the analog switch element during the precharge period, that is, when the control signal Φ is at a "high" level.
It is non-conductive during the comparison period, that is, when the control signal Φ is at a "low" level. This is because when there is no control signal and this circuit is fixed at "high", the following problem occurs. The switching speed of this circuit is determined mostly by the time constant determined by the product of the impedance of the analog switch element and the holding capacitance. In this peak hold circuit, when the +input>-input, that is, the input _V1o changes from low to high, the peak value will be held low unless it follows quickly. In other words, while accuracy deteriorates, if the tracking is too fast, + input < - input, that is, the input is high →
When changing to low, a potential difference sufficient to invert the output is not generated, and a phenomenon may occur in which the analog switch element cannot be made non-conductive for any length of time. To prevent this, the analog switch element was made non-conductive in a certain cycle and the hold value was fixed to make it easier for the comparator to compare. This is because if the input is changing, the input and the hold value will become further apart. However, when it becomes non-conductive in a certain cycle, the above-mentioned malfunction will occur.

By the way, as understood from the above explanation, this analog switch element does not need to be made non-conductive every other clock, so it is only necessary to make it non-conductive when the relationship of +input<-input is established. In the present invention, malfunctions can be avoided by making this analog switch element have a high resistance except when it is completely non-conductive.

[Means for solving problems]

The peak hold circuit of the present invention has a level control circuit having three output levels for controlling an analog switch element in order to prevent the above-mentioned malfunction.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Vin is connected to the + input of comparator 1 and one terminal of analog switch element 2, and the other terminal of analog switch element 2 is connected to the - input of comparator 1, and there is a capacitance between this connection point and the ground potential. Connect 3 and set this as Vout. The output of the comparator 1 is logically combined with the control signal Φ by a gate circuit 4 and a level control circuit 5, and is input to the gate of an analog switch element 2.

FIG. 5 shows an example of the level control circuit 5, which comprises an inverter with a PMOS transistor 31 and an NMOS transistor 32, and a bias source V that biases the source of the NMOS transistor 32 at a low voltage that does not cause the analog switch element 2 to become inactive. Connected to ₀ . The output signal of the gate circuit 4 is received at the input 1 of this inverter, and the output is sent to the gate terminal of the analog switch element 2. Furthermore, the input 2 is connected via an inverter 24 to the gate of a transistor 33 for short-circuiting the bias source V ₀ . This terminal is comparator 1
receives the output signal of

The operation is basically the same as the conventional one; when +input (Vin) > -input (Vout), the output of comparator 1 is "high" level, and when +input (Vin) < -input (Vout), comparator 1 output goes high. Output is “low”
level. The difference is that when the control signal Φ is at a "high" level and the output of the comparator 1 is also at a "high" level, the output of the level control circuit 5 becomes a "high" level, making the analog switch element 2 conductive and inputting the input voltage Vin to the capacitor 3. Charge. Next, when the control signal Φ is at a "low" level and the output of the comparator 1 is at a "high" level, the level control circuit 5 outputs an intermediate level, causing the analog switch element 2 to have a high resistance value. At this time, if the + input of comparator 1 is changing from low to high, the difference between the + input and - input will widen, but if the control signal Φ goes to the "high" level in the next cycle, the difference will shrink again. , during this time the comparator continues to output a "high" level. If the + input is changing from high to low, the difference will still be widened, so even if there is an offset in comparator 1 and it outputs a "high" level, it can become a "low" level. Furthermore, + of comparator 1
When the input changes from low to high to low, the -input does not change much, but the output of comparator 1 goes to the "low" level in the next cycle. Therefore, if the required accuracy is severe, it is necessary to speed up the cycle of the control signal Φ.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In place of the analog switch element 2 of FIG. 1, analog switch elements 12 and 16 connected in series are used. At this time, analog switch element 16
The output of the comparator 11 is directly input to the gate of the analog switch element 12, and the output of the level control circuit 15 is connected to the gate of the analog switch element 12. The level control circuit 15 applies a control signal Φ to an input 1 and a ground level to an input 2. A capacitor 13 is connected between the negative input of the comparator 11 and ground. The operation follows the same logic as in the first embodiment, so the gate circuit 4 is removed. For this reason, since two analog switch elements are connected in series, the on-resistance and switching speed when used as a switch are disadvantageous compared to when only one element is used, but the circuit becomes simpler.

〔Effect of the invention〕

As explained above, the present invention has two states when the output of the comparator is at the "high" level, that is, when the control signal Φ is at the "high" level, the analog switch element is in a state of conduction and low resistance, and the control signal is When the level is "low", the analog switch element is conductive but has a high resistance state.
As a result, the analog switch element does not become completely non-conductive, and the gate that occurs when it is non-conductive,
This eliminates the pressure required by the drain overlap capacitance, which has the effect of preventing malfunctions in which peaks cannot be detected, which occurred in the past.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention,
FIG. 2 is a circuit diagram showing a second embodiment of the present invention, FIG. 3 is a circuit diagram showing a conventional example, and FIGS. 4A and B are diagrams explaining malfunction due to capacitance between gate and drain.
FIG. 5 is a circuit diagram showing an example of the level control circuits 5 and 15. 1, 11, 21 are comparators,
2, 12, 22 are analog switch elements, 3, 1
3 and 23 are capacitors, 5 and 15 are level control circuits,
4, 24 are gate circuits, 31 are PMOS transistors, 32, 33 are NMOS transistors, 34
is the inverter and V ₀ is the bias power supply.

Claims (1)

[Claims] 1. It has a first analog switch element, a first comparator, and a first capacitor, and one of the first analog switch elements is connected to the + input side and the - input side of the first comparator, respectively. In a peak hold circuit in which the terminals are connected, the + input side is the input terminal, and the - input side is connected between the first capacitor and ground, which is used as the output terminal, for the output of the first comparator and the input sampling. When the control signal of the first comparator is at the "high" level, the first analog switch element is made conductive, and when the output of the first comparator is at the "high" level and the control signal is at the "low" level, the first analog switch element is turned on. a level control circuit in which the resistance is larger than when the control signal is at a "high" level, and when the output of the first comparator is at a "low" level, the first analog switch element is made non-conductive regardless of the state of the control signal; A peak hold circuit characterized by having. 2 It has a first analog switch element, a first comparator, and a first capacitor, and one terminal of the first analog switch element is connected to the + input side and the - input side of the first comparator, respectively, and the + input A second analog switch element is connected in series with the first analog switch element in a peak hold circuit in which the input side is the input terminal and the input side is connected between the first capacitor and the ground, and this is the output terminal. ,
The control input of one analog switch element inputs the output of the first comparator, and the control input of the other analog switch element is conductive when the input control signal for sampling is at a "high" level.
A peak hold circuit comprising a level control circuit connected thereto that makes the on-resistance larger when the control signal is at a "low" level than when the control signal is at a "high" level.