JPH09312561A - Noise suppressing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently suppress noise leaked to the outside by fully enlarging the bypass effect of noise though the capacitance of a capacitor incorporated in a semi-conductor integrated circuit is small. SOLUTION: One end of the capacitor 6 is connected to a power source line 1 which extends to a digital circuit 3, one end of the capacitor 9 is connected to a gounded line 2 which extends to the digital circuit 3, a charging transistor 5 is connected between the other side of the capacitor 6 and the grounded line 2, the charging transistor 8 is connected between the other end of the capacitor 9 and the power source line 1 and the discharging transistor 11 is connected between the other end of the capacitor 6 and the other end of the capacitor 9. Then, the charging transistors 5 and 8 are made conductive by a timing to prevent transitional and instantaneous current from flowing in the digital circuit 3 and also the discharging transistor 11 is made conductive by the timing to permit transitional and instantaneous current to flow in the digital circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided in a semiconductor integrated circuit device in association with the digital circuit in order to suppress noise generated from the semiconductor integrated circuit device having a digital circuit operating according to a basic clock. The present invention relates to a noise suppression device that is composed of a bypass capacitor.

[0002]

2. Description of the Related Art In recent years, EMI due to noise generated by a semiconductor integrated circuit device having a digital circuit operating according to a basic clock has become a problem, and low EMI of the semiconductor integrated circuit device itself is required. Low EM
2. Description of the Related Art Semiconductor integrated circuit devices having a built-in bypass capacitor, which is a means of realizing I (Electromagnetic Interference), have come to be used.

A conventional semiconductor integrated circuit device having a digital circuit which operates according to a basic clock will be described below with reference to FIG. FIG. 3 is a circuit diagram showing a configuration of a conventional semiconductor integrated circuit device. In FIG. 3, 1
Reference numeral 3 is a power supply, and 3 is a digital circuit which operates according to a basic clock and serves as a noise source. Reference numeral 1 is a power supply line from the power supply 13 to the digital circuit 3, and 2 is a ground line from the power supply 13 to the digital circuit 3. 12 is the power line 1
Is a capacitor for reducing noise that is fed back to the power supply 13 by connecting one end to the ground line 2 and connecting the other end to the ground line 2.

The operation of the semiconductor integrated circuit device configured as described above will be described below. First,
When power is supplied from the power supply 13 and the digital circuit 3 operates, the internal state of the digital circuit 3 changes in accordance with the basic clock, for example, at each rising edge of the basic clock, but power is consumed at that timing and a transient instantaneous current Flowing. Parasitic impedances are formed between the power supply line 1 and the digital circuit 3 and between the ground line 2 and the digital circuit 3. However, when the capacitor 12 is sufficiently close to the digital circuit 3, the instantaneous current flowing through the digital circuit 3 is generated. Is first supplied from the capacitor 12, and then from the power supply 13 through the power supply line 1 and the ground line 2. As a result, the capacitor 12 arranged near the digital circuit 3 serves as a supply source of the instantaneous current flowing into the digital circuit 3, and has an effect of reducing the supply amount of the instantaneous current from the power supply 13. That is, the power source 1
Since the instantaneous current flowing from the power source line 3 to the power source line 1 and the ground line 2 is reduced, the capacitor 12 has a role of bypassing the noise of the digital circuit 3 serving as a noise source and suppressing the leakage from the power source 13 to the outside. Effective as a measure.

Noise is observed between the power supply and ground due to the transient current due to the clock, and the magnitude of the noise allows the charge emitted by the capacitor 12 to be known.
Of the accumulated charges of 2, about 5% of charges are provided for noise suppression.

[0006]

However, in the above conventional structure, a large capacity capacitor cannot be built in the semiconductor integrated circuit device for noise bypass, and the built-in capacitor is limited to a small capacity. Therefore, the electric charge supplied from the capacitor 12 to the digital circuit 13 is small, and most of the electric charge is supplied from the power source 13.
The noise bypass effect was not sufficiently obtained, and the noise leaking from the power supply to the outside could not be sufficiently suppressed.

The present invention solves the above-mentioned conventional problems. Even if the capacity of a capacitor incorporated in a semiconductor integrated circuit device is small, the noise bypass effect is sufficiently increased to sufficiently prevent noise leaking to the outside. It is to provide a noise suppressing device that can suppress the noise.

[0008]

The noise suppressing device of the present invention is built in a semiconductor integrated circuit device having a digital circuit which operates according to a basic clock, and one end of which is connected to a power supply line from a power supply to the digital circuit. A first capacitor connected, a second capacitor having one end connected to a ground line extending from the power supply to the digital circuit, and a first charging switching connected between the other end of the first capacitor and the ground line. An element, a second charging switching element connected between the other end of the second capacitor and the power supply line, and a discharge connected between the other end of the first capacitor and the other end of the second capacitor Timing for preventing transient instantaneous current from flowing through the digital circuit by synchronizing the first and second charging switching elements with the basic clock. Together to conduct, and so as to conduct at the time it flows transient instantaneous current in the digital circuit the discharging switching element in synchronization with the basic clock.

The timing at which the transient instantaneous current flows is the period from the beginning of the instantaneous current flow to the end of the instantaneous current flow at the shortest, and the timing at which the instantaneous current does not flow is after the instantaneous current has finished flowing. Next is a period until immediately before the momentary current starts to flow. Further, the first charging switching element is, for example, an N-channel MOS transistor, the second charging switching element is, for example, a P-channel MOS transistor, and the discharging switching element is, for example, an N-channel MOS transistor. Composed.

According to this structure, at the timing when the transient instantaneous current does not flow in the digital circuit, the first and second capacitors are connected in parallel between the power supply line and the ground line, and the first and second capacitors are connected. The second capacitor will be charged in parallel by the power supply,
The voltage of the second capacitor is approximately the power supply voltage. Also, at the timing when a transient instantaneous current flows in the digital circuit, the first and second capacitors are connected in series between the power supply line and the ground line,
The voltage applied from the second capacitor to the digital circuit becomes higher than the power supply voltage, and in this state, the first and second capacitors are discharged in series to the digital circuit. The discharge continues to the digital circuit until the voltage of the series circuit of the second capacitor becomes approximately the power supply voltage, that is, until about half of the charges accumulated in the first and second capacitors are discharged. During that time, it does not flow through the power supply.

As described above, when the first and second capacitors are connected in series between the power supply line and the ground line at the timing when the transient instantaneous current flows through the digital circuit, the first and second capacitors are connected. About half of the electric charge charged to is discharged from the power supply line and the ground line and supplied to the digital circuit that becomes a noise source, so a larger amount of electric charge is discharged than before, and even with a capacitor with a small electrostatic capacity. The noise bypass effect can be increased, and thus noise leaking to the outside can be sufficiently suppressed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor integrated circuit device incorporating a noise suppression device according to an embodiment of the present invention. In FIG. 1, 13
Is a power supply, and 3 is a digital circuit which operates according to a basic clock and becomes a noise source. Reference numeral 1 is a power supply line from the power supply 13 to the digital circuit 3, and 2 is a ground line from the power supply 13 to the digital circuit 3. 6 is a first capacitor whose one end is connected to the power supply line 1, and 9 is a second capacitor whose one end is connected to the ground line 2. Reference numeral 5 is a first charging switching element composed of an N-channel type MOS transistor connected between the other end of the first capacitor 6 and the ground line 2. Reference numeral 8 is a second charging switching element composed of a P-channel MOS transistor connected between the other end of the second capacitor 9 and the power supply line 1. Reference numeral 11 is a discharging switching element composed of an N-channel MOS transistor connected between the other end of the first capacitor 6 and the other end of the second capacitor 9.

Reference numeral 4 denotes a charge timing control signal which becomes the "H" level at the charge period, that is, at the timing when the transient instantaneous current does not flow in the digital circuit 3 in synchronization with the basic clock, and the charge timing control signal is the first. Is input to the gate of the switching element 5 for charging, the first switching element 5 for charging is controlled, and the first switching element 5 for charging is controlled at a timing when a transient instantaneous current does not flow in the digital circuit 3. Conduct the first capacitor 6
Is charged. The charge timing control signal is at the “H” level during a period after the transient instantaneous current has finished flowing and immediately before the transient instantaneous current starts to flow next.

Reference numeral 7 is an inverter that inverts the logic of the charging timing control signal 4, and the output signal thereof is input to the gate of the second charging switching element 8 to control the second charging switching element 5. And the second transient is generated at the timing when no transient instantaneous current flows through the digital circuit 3.
The charging switching element 8 is turned on to charge the second capacitor 9.

Reference numeral 10 is a discharge timing control signal which becomes "H" level at a discharge period, that is, at the timing when a transient instantaneous current flows in the digital circuit 3 in synchronization with the basic clock, and is inputted to the gate of the discharge switching element 11. As a result, the switching element 11 for discharge is controlled,
At the timing when a transient instantaneous current flows in the digital circuit 3, the discharging switching element 11 becomes conductive and the first and second capacitors 6 and 9 are discharged in series. The discharge timing control signal becomes "H" level during the period from the beginning of the transient instantaneous current to the end of the instantaneous current at the shortest. It should be noted that both the charge timing control signal and the discharge timing control signal must not be "H" at the same time.

In this semiconductor integrated circuit device, the first and second capacitors 6 and 9 are connected in parallel between the power supply line 1 and the ground line 2 at the timing when no transient instantaneous current flows through the digital circuit 3. Has been
The first and second capacitors 6 and 9 are charged in parallel by the power supply 13, and the voltages of the first and second capacitors 6 and 9 are approximately the power supply voltage. Further, at the timing when a transient instantaneous current flows through the digital circuit 3, the first and second capacitors 6 and 9 are connected in series between the power supply line 1 and the ground line 2, and The voltage applied to the digital circuit 3 from the second capacitors 6 and 9 becomes higher than the power supply voltage, and in this state, discharging is performed in series from the first and second capacitors 6 and 9 to the digital circuit 3. Therefore, until the voltage of the series circuit of the first and second capacitors 6 and 9 becomes substantially the power supply voltage, that is, about half of the charges accumulated in the first and second capacitors 6 and 9 are discharged. Until then, the digital circuit 3 is continuously discharged, and during that time, the power does not flow through the power supply 13. When an instantaneous current flows through the digital circuit 3, the digital circuit 3 side has a low impedance,
The voltage when the second capacitors 6 and 9 are connected in series has a value lower than twice the power supply voltage. In the actual design, the transient current is estimated and the values of the first and second capacitors 6 and 9 are adjusted to be designed to be almost the same as the power supply voltage.

As described above, when the first and second capacitors 6 and 9 are connected in series between the power supply line 1 and the ground line 2 at the timing when the transient instantaneous current flows in the digital circuit 3, About half of the electric charges charged in the first and second capacitors 6 and 9 are discharged from the power supply line 1 and the ground line 2 and supplied to the digital circuit 3 which is a noise source, so that a larger amount of electric charges than the conventional one is discharged. As a result, the bypass effect of noise can be increased even with a capacitor having a small electrostatic capacity, and therefore noise leaking to the outside can be sufficiently suppressed.

Next, the operation of the semiconductor integrated circuit device of this embodiment will be described with reference to FIG. In FIG. 2, (a) is the basic clock of the digital circuit 3, (b) is
Shows the current consumption of the digital circuit 3, (c) shows the charge timing control signal 4, and (d) shows the discharge timing control signal 10. First, when power is supplied from the power source 13 and the digital circuit 3 operates, the internal state of the digital circuit 3 changes, but in the digital circuit 3 in which the internal state changes in synchronization with a constant basic clock,
As shown in (b), the power consumption timing is synchronized with the cycle of the basic clock. That is, for example, in FIG.
A current transiently flows and consumes power during a predetermined period immediately after the rise of the basic clock in (a), and almost no current flows during the subsequent period, and power is scarcely consumed.

Therefore, as shown in FIG. 2C, the charge timing control signal 4 is set to the "H" level at the timing when the digital circuit 3 does not consume the current, and the first charge switching element 5 and the second charge switching element 5 are connected. By making the charging switching element 8 conductive, the first capacitor 6 and the second capacitor 9 are respectively set to "H" in FIG. 2 (c).
It is charged during the level period. At this time, the discharge timing control signal 10 is at "L" level, and the discharge switching element 11 is cut off.

Next, as shown in FIG. 2 (d), the discharge timing control signal 10 is set to "L" level at the timing when the consumption current flows in the digital circuit 3 to make the discharge switching element 11 conductive and charge timing. By setting the control signal 4 to the “L” level to shut off the first charging switching element 5 and the second charging switching element 8, the charged first capacitor 6 and second capacitor 9 are connected in series. Connected. By this operation, the positive charges charged in the first capacitor 6 and the second capacitor 9 are discharged to the power supply line 1, and the negative charges are discharged to the ground line 2. Note that the timing of turning on the transistor 11 must be the same as the rising of the basic clock. If the timing is shifted earlier, the released charge will flow to the power supply side,
It becomes a source of noise, and if it is delayed, the noise is not sufficiently suppressed.

The electric charges emitted from the first and second capacitors 6 and 9 serve as a supply source of the instantaneous current flowing to the digital circuit 3 and have an effect of reducing the supply amount of the instantaneous current from the power source 13. That is, since the instantaneous current flowing from the power supply 13 to the power supply line 1 and the ground line 2 is reduced, the configuration of this embodiment serves to bypass the noise of the digital circuit 3 which is the noise source, and is effective as an EMI countermeasure. .

When the transient current flows in the digital circuit 3 side, when viewed from the capacitors 6 and 9 side,
Since the impedance is low, the voltage applied to the digital circuit 3 is lower than twice the power supply voltage as described above. In practical use, the transient current should be estimated and the capacitor should be designed to have the optimum capacity so that the breakdown voltage does not cause a problem.

Regarding the charging and discharging of the capacitors 6 and 9, the charging is performed gently, and the discharging is used to supply the transient current of the digital circuit 3. Therefore, the charging and discharging of the capacitors 6 and 9 itself is a noise. It cannot be the source. Further, the capacitors 6 and 9 are arranged close to the digital circuit 3 and separated from the power source, like the normal bypass capacitor, so that the capacitors 6 and 9 are parasitic impedances between the power source and the digital circuit 3, so that the capacitors 6 and 9 are not disposed. The supply of electric charges from 9 to the power supply side is small, and most of the electric charges are supplied to the digital circuit 3 side for noise suppression, and the noise suppression effect is not lost.

As described above, according to this embodiment,
The first capacitor 6 and the second capacitor 9 that have been charged at the timing when the transient instantaneous current flows in the digital circuit 3 are connected in series between the power supply line 1 and the ground line 2 so that the first capacitor Approximately half of the total amount of electric charges charged in 6 and the second capacitor 9 can be used as a source of the instantaneous current of the digital circuit 3, and the amount of electric charges to be emitted is several times to ten times that of the conventional example. Therefore, if compared with the same capacitance value, the instantaneous current flowing from the power supply 13 to the power supply line 1 and the ground line 2 can be further reduced.

Although the switching elements for charging and the switching elements for discharging are MOS transistors in the above embodiments, they may be bipolar transistors.

[0026]

According to the present invention, the first and second capacitors are charged in parallel at the timing when the instantaneous current does not flow, and the first capacitor is charged at the timing when the instantaneous current flows in the digital circuit which is the noise source. A capacitor charged by providing first and second charging switching elements and discharging switching element for connecting the first and second two charged capacitors in series between the power supply line and the ground line It is possible to realize an excellent noise suppression device capable of increasing the amount of electric charge emitted, reducing the supply amount of the instantaneous current from the power source, and sufficiently suppressing the noise leaking to the outside.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a timing chart of the semiconductor integrated circuit device device according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1 Power Line 2 Ground Line 3 Digital Circuit 4 Charging Timing Control Signal 5 First Charging Switching Element 6 First Capacitor 7 Inverter 8 Second Charging Switching Element 9 Second Capacitor 10 Discharge Timing Control Signal 11 For Discharging Switching element 12 Capacitor 13 Power supply

Claims (3)

[Claims] 1. A noise suppressor incorporated in a semiconductor integrated circuit device having a digital circuit operating according to a basic clock, the first capacitor having one end connected to a power supply line extending from a power supply to the digital circuit. A second capacitor having one end connected to a ground line extending from the power source to the digital circuit, and a first charging switching element connected between the other end of the first capacitor and the ground line,
A second charging switching element connected between the other end of the second capacitor and the power supply line, and a second charging switching element connected between the other end of the first capacitor and the other end of the second capacitor. A discharge switching element, wherein the first and second charge switching elements are brought into conduction at a timing at which a transient instantaneous current does not flow in the digital circuit in synchronization with the basic clock, and the discharge switching element The noise suppressing device is characterized in that the circuit is turned on at a timing at which a transient instantaneous current flows through the digital circuit in synchronization with the basic clock. 2. The timing at which the instantaneous current flows is a period from the beginning of the flow of the instantaneous current to the end of the flow of the instantaneous current at the shortest, and the timing at which the instantaneous current does not flow is after the instantaneous current has finished flowing. The noise suppression device according to claim 1, wherein the noise suppression device is a period immediately before the momentary current starts to flow. 3. The first charging switching element is an N-channel MOS transistor, and the second charging switching element is a P-channel MOS transistor.
The noise suppressing device according to claim 1 or 2, wherein the discharging switching element is an N-channel MOS transistor.