JP2001326535A - Bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure reliable starting with as small the number of elements as possible. SOLUTION: When the voltage of a standby terminal 23 is defined as Vss and a standby state by a 3rd NMOS 5 is released, a 3rd PMOS 7 made to be conductive, a 4th NMOS 6 is made to be nonconductive, a charging current is caused to flow to a capacitor 12 from the drain side of a 1st PMOS 1 to temporarily decrease the gate potential of 1st and 2nd PMOSs 1 and 2, the 2nd PMOS is therefore made conductive, a 1st NMSO 3 is also made conductive by the 2nd PMOS 2, and this circuit is started to be in a normal operation mode in which a bias current Ib is caused to flow so that reliable starting can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bias circuit in an analog circuit such as an operational amplifier, and more particularly to an improvement in a bias circuit having a function of switching between a normal operation state and an operation standby state by controlling an external signal.

[0002]

2. Description of the Related Art In an analog circuit such as an operational amplifier, a bias circuit using a constant current source is usually used to determine the operating point. In addition, depending on the application of the circuit, a bias circuit having a so-called standby function configured to temporarily stop operation while the power supply voltage is being supplied and to reduce current consumption in an operation standby state may be provided. There is also. FIG. 2 shows an example of the configuration of a conventional bias circuit having such a standby function. Hereinafter, this bias circuit will be described with reference to FIG. This bias circuit is composed of first and second P-channel MOSFETs (hereinafter referred to as “MP
1 "and" MP2 "), the first and second N-channel MOSFETs also forming a current mirror circuit.
(Hereinafter referred to as “MN1” and “MN2” respectively)
A third N-channel MOSFET for control (hereinafter referred to as “MN
3 ") as a main component.

The gates of MP1 and MP2 are connected to each other, and the gate and drain of MP1 are so-called diode-connected. The gates of MN1 and MN2 are also connected to each other, and the gate and drain of MN2 are connected to each other, so-called diode-connected. Further, the drain of MP1 is connected to the drain of MN1, while the drain of MP2 is connected to the drain of MN2.
Are connected to each other. The gate of the control MN3 is a standby control terminal STB. When the voltage Vdd is applied to the standby control terminal STB, the MN3 is turned on. As a result, MN1, MN2, MP1 and MP2 are all turned off (OFF), and MN is connected via the resistors R and MP2.
The bias current Ib supplied to the external circuit from the connection point between the drain of P2 and the drain of MN2 becomes zero, so that a so-called standby mode (operation standby state) is established. On the other hand, the voltage Vss is applied to the standby control terminal STB.
Is applied, MN3 is turned off, and the standby mode is released.

However, in this bias circuit, even if MN3 is turned off, there is no current flow path (so-called path), and there is no factor for forcibly starting the circuit, so that MN1, MN2, MP1, There is a disadvantage that the bias current does not flow while MP2 is in the OFF state, and the standby mode is not reliably released. In reality, due to the leakage current between the source and the drain in MP2 and MN1, electric charges are accumulated little by little in the gates of each other, and the gate potential fluctuates.
May be turned on to activate the circuit and release the standby mode. By the way, MP2 and MN1
The time until the transistor becomes conductive is determined by the time constant of the leakage current and the gate capacitance. However, since the leakage current is usually very small, it takes time to release the standby mode.
In particular, under low power supply voltage and low temperature conditions,
The leakage current between the drains is small, so that it may take several hundred milliseconds to several seconds to release the standby mode,
It can have a significant effect on the operation of the circuit.

As a circuit for solving such a problem, there is a bias circuit to which a so-called starting circuit is added. For example, a circuit having a configuration as shown in FIG. 3 is known. Hereinafter, this bias circuit will be described with reference to FIG. 10. This bias circuit is different from the bias circuit shown in FIG.
SFETs (hereinafter, “MP10”, “MP1”
1 "," MP12 ", and" MP13 ") and the tenth
And an eleventh N-channel MOSFET (hereinafter, referred to as “MN10” and “MN11”, respectively). That is, in this bias circuit, at the time when the voltage applied to the standby terminal STB is set to Vss to release the standby state and the MN3 is turned off, the MP1 is turned on, as in the bias circuit shown in FIG. , M
Since there is no trigger for changing the operation states of P2, MN1 and MN2, the potential at the Vn output terminal, which is the connection point between the drain of MP2 and the drain of MN2, remains at Vss even when MN3 is turned off. is there. Therefore, MN1
0, MP10 and MP11 are non-conductive and MP1
The gate potential of No. 3 is at the Vss level. On the other hand, MP12
Becomes conductive when Vss is applied to the standby terminal STB, so that the potential at the Vp output terminal, which is the connection point between the gates of MP1 and MP2, is reduced. As a result, MP2 and MN1 become conductive, the circuit is started, and the bias current Ib flows. After that, the potential of the Vn output terminal rises, whereby MN10, MP10 and MN11 are turned on, MP13 is turned off, and Vp
The start-up operation is completed by increasing the potential of the output terminal.

[0006]

However, the above-described bias circuit with a starting circuit has a large number of circuit elements.
When used in an IC circuit, there is a problem that the circuit area is increased and is not practical. The present invention has been made in view of the above circumstances, and has as few elements as possible.
An object of the present invention is to provide a bias circuit capable of ensuring reliable start-up. Another object of the present invention is to provide a bias circuit that can be started reliably and quickly when power is turned on or when the standby mode is released.

[0007]

In order to achieve the above object, a bias circuit according to the present invention comprises: a first current mirror circuit comprising two transistors between a power supply and a ground; A transistor and a second current mirror circuit composed of two transistors of opposite polarities are cascaded to form a basic bias circuit, and the second current mirror circuit has the same polarity as the two transistors of the second current mirror circuit, A standby control transistor connected in parallel to the diode-connected transistor in the current mirror circuit is provided, and in response to a control signal externally applied to the standby control transistor, the standby control transistor Bias circuit configured to be able to shift and release the basic bias circuit to a standby state A state in which the standby control transistor releases the standby state of the basic bias circuit by the control signal applied from the outside, between the gates of two transistors constituting the first current mirror circuit and the ground; When this happens, the potential of the gates of the two transistors constituting the first current mirror circuit is temporarily lowered, while the standby control transistor activates the basic bias circuit by the control signal applied from the outside. When a standby state is set, a startup control circuit is provided which is electrically disconnected from the gates of the two transistors constituting the first current mirror circuit.

In this configuration, when the standby control transistor is released from the standby state of the basic bias circuit, the start control circuit changes the gate potentials of the two transistors constituting the first current mirror circuit. This is forcibly changed, and this acts as a trigger, so that a current flow path is generated in the basic bias circuit, so that the basic bias circuit can reliably shift to a normal operation state.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. First, the configuration of the bias circuit according to the embodiment of the present invention will be described. This bias circuit is roughly divided into a basic bias circuit 101, a standby control circuit 102, and a start control circuit 103. It has become. The basic bias circuit 101 includes first and second P-channel MOSFETs (hereinafter referred to as “first PMO
S "," second PMOS ", 1, 2 and first and second N-channel MOSFETs (hereinafter," first NMOS "," second NMOS ", respectively) 3, 4
And a resistor 11. The standby control circuit 102 is configured using a third N-channel MOSFET (hereinafter, referred to as “third NMOS”) 5 as a standby control transistor. Further, the activation control circuit 103 uses a fourth N-channel MOSFET (hereinafter, referred to as “fourth NMOS”) 6, a third P-channel MOSFET (hereinafter, “third PMOS”) 7, and a capacitor 12. It is configured as follows.

The basic bias circuit 101 has basically the same configuration as a conventional bias circuit.
That is, the gates of the first and second PMOSs 1 and 2 are connected to each other, while the first PMOS 1 and the second PMOS 1 (FIG.
In this example, the gate and the drain are connected to each other, and are in a so-called diode connection state. Then, the source of the first PMOS 1
While the power supply voltage Vdd is applied directly,
Second PMOS 2 (in FIG. 1, denoted as “MP2”)
The power source voltage Vdd is applied to the source of the first and second PMOS transistors 1 and 2 through a resistor 11.
2, a so-called first current mirror circuit 51 is configured.

On the other hand, the first and second PMOSs 1, 2
The first and second NMOSs 3 and 4 (in FIG. 1, denoted as “MN1” and “MN2”, respectively) having opposite polarities have their gates connected to each other, while the second NMOS 4 has The gate and the drain are connected to each other to form a so-called diode connection state, and the first and the second are connected.
A so-called second current mirror circuit 52 is constituted by the NMOSs 3 and 4. And the first
The drain of the NMOS3 is connected to the drain of the first PMOS1, and the drain of the second NMOS4 is connected to the drain of the second PMOS2. On the other hand, a predetermined source potential Vss is applied to the sources of the first and second NMOSs 3 and 4, and in the embodiment of the present invention, Vss is a ground potential. As described above, the first current mirror circuit 51 and the second current mirror circuit 52 are configured to be connected in cascade between the power supply and the ground. In such a configuration, the drain of the first PMOS 1 and the first
A connection point between the drain of the NMOS 3 and the drain of the second NMOS 2 is connected to a first output terminal (denoted as “Vp” in FIG. 1) 21. Is a second output terminal 22 (denoted as “Vn” in FIG. 1). Further, the first output terminal 21 is connected to the P of a bias supply circuit (not shown).
The second output terminal 22 serves as a bias voltage supply terminal for an N-channel MOSFET of a bias supply circuit (not shown).

The standby control circuit 102 includes a third NMOS 5
The drain of FIG. 1 (referred to as “MN3”) is connected to the second output terminal 22, while the source is set to the ground potential. And the third NM
The gate of the OS5 is a standby terminal (indicated as "STB" in FIG. 1) 23. When the basic bias circuit 101 is set in a standby state (standby mode), the voltage Vdd is released from the standby state. Has the voltage Vss
Are respectively applied. In the activation control circuit 102, a third PMOS 7 (indicated as "MP3" in FIG. 1) as a first transistor for activation control and a fourth NMOS 6 (in FIG. 1 as a second transistor for activation control) "MN4" is connected to the respective gates and connected to the standby terminal 23, while the third P
The drain of the MOS 7 and the drain of the fourth NMOS 6 are connected. And the third PMOS
The source 7 is connected to the first output terminal 21, while the source of the fourth NMOS 6 is applied with a predetermined source voltage Vss. Vss is the ground potential. Further, a capacitor 12 is connected in parallel between the drain and the source of the fourth NMOS 6.

Next, the operation of the bias circuit having the above configuration will be described. First, the standby mode will be described. To shift from the so-called normal operation mode in which the bias circuit operates and the bias current Ib is output to the standby mode, the voltage applied to the standby terminal 23 is set to Vdd (the same as the power supply voltage). I do. As a result, the third NMOS 5 is turned on, and the second output terminal 22 is at the ground potential.
OSs 3 and 4 are turned off. Also, the third PMO
S7 becomes non-conductive, while the fourth NMOS 6 becomes conductive, so that the first output terminal 21 is disconnected from the capacitor 12 (in other words, the first and second terminals).
The gates of the PMOSs 1 and 2 and the capacitor 21 are turned off. On the other hand, the capacitor 12 is connected to the fourth NMO
In S6, a short-circuit state is set, and a discharge state is set. Then, since the potential of the first output terminal 21 rises to the power supply voltage Vdd, the first and second PMOSs 1 and 2 are also turned off, the bias current Ib does not flow, and the circuit enters the standby mode.

Next, in order to release the standby mode,
When the voltage applied to the standby terminal 23 is Vss, that is, the ground potential, the third NMOS 5 and the fourth NMOS 5
6 is turned off, the third PMOS 7 is turned on, and the capacitor 12 is connected to the first output terminal 21 via the third PMOS 7. Since the capacitor 12 is discharged during the standby mode, when the capacitor 12 is connected to the first output terminal 21 via the third PMOS 7, a charging current flows to the capacitor 12, so that the first The potential of the output terminal 21 is temporarily reduced from Vdd in the standby mode. Accordingly, the gate potentials of the first and second PMOSs 1 and 2 similarly decrease, and a potential difference is generated between the gate and the source of the second PMOS 2 and the second PMOS 2
Becomes conductive. Thereby, the second output terminal 22
, The first NMOS 3 also becomes conductive, the bias current Ib flows out, and the basic bias circuit 101 is activated. Then, when the charging of the capacitor 12 proceeds and the charging current becomes zero, the potentials of the first and second output terminals 21 and 22 are in a steady state, and the start-up operation is completed.

Next, the operation when the power is turned on will be described. Before turning on the power, the potential of the power supply line (the line to which the power supply voltage is applied) becomes Vss, and therefore, the charge stored in the capacitor 12 is zero. When the power is turned on while the potential of the standby terminal 23 is fixed at Vss, all the transistors are in a non-conductive state at the beginning of the power supply. However, as the power supply voltage rises, the first output terminal is connected via the first PMOS1. 21 increases, and the third PMO
When the threshold voltage of S7 is exceeded, the third PMOS 7 becomes conductive. Due to the conduction of the third PMOS 7, a charging current flows into the capacitor 12, and the first output terminal 2
The potential of 1 drops temporarily. Thereafter, as in the case of the release of the standby mode described above, the gate potential of the first and second PMOSs 1 and 2 also drops due to the temporary drop of the potential at the first output terminal 21. Therefore, a potential difference is generated between the gate and the source of the second PMOS 2, and the second PMOS 2 is turned on. As a result, the potential of the second output terminal 22 increases, and
The first NMOS 3 also becomes conductive, and the bias current I
b flows out, and the basic bias circuit 101 is activated.

When the power of the capacitor 12 may not be sufficiently discharged after the power of the capacitor 12 is turned off, for example, when the power is turned on immediately after the power is turned off, the power supply may be turned off before or after the power is turned on. At the same time, the standby terminal 23 is once set to the logical value High level (Vdd level) and then returned to the logical value Low level (Vss level), so that reliable start-up is ensured.

[0017]

As described above, according to the present invention,
A start control circuit is provided that generates a potential change that triggers a forced start of the bias circuit when a control signal for releasing the standby state of the bias circuit is externally applied. Is configured to use the charging / discharging described above, an effect is provided that a bias circuit that can ensure reliable start-up with as few elements as possible can be provided. In addition, the start-up control circuit is configured using a capacitor and a transistor, and is configured so that current flows into the capacitor when the power is turned on. This is effective in that the startup is performed and a highly reliable bias circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a circuit configuration example of a bias circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a circuit configuration of a conventional bias circuit.

FIG. 3 is a circuit diagram showing an example of a circuit configuration of a conventional bias circuit to which a circuit for starting control is added.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 ... Capacitor 51 ... 1st current mirror circuit 52 ... 2nd current mirror circuit 101 ... Basic bias circuit 102 ... Standby control circuit 103 ... Activation control circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5H420 BB12 CC02 DD02 EA14 EA18 EA24 EA42 EA43 EA47 EB15 EB37 FF03 FF23 KK01 NA28 NB02 NB12 NB13 NB16 NB36 NC02 NC23 NC26 NC38 NE03 5J069 AA03 CA02A FA18 HA10 HA17 HA25 HA29 HA39 KA09 KA12 KA25 KA47 KA49 MA21 5J092 AA03 AA43 AA54 AA59 CA81 CA85 CA92 FA05 FA10 FA18 FR15 HA10 HA17 HA25 HA29 HA39 KA09 KA12 KA25 KA47 KA49 MA21

Claims (2)

[Claims] 1. A first current mirror circuit comprising two transistors and a second current mirror circuit comprising two transistors having polarities opposite to those of the two transistors are connected in series between a power supply and a ground. And a standby control circuit which has the same polarity as the two transistors of the second current mirror circuit and is connected in parallel to the diode-connected transistor in the second current mirror circuit. Circuit, wherein the standby bias transistor is provided so as to be able to shift and release the basic bias circuit to a standby state in accordance with a control signal externally applied to the standby control transistor. And the gates and the gates of two transistors constituting the first current mirror circuit. When the standby control transistor is released from the standby state of the basic bias circuit by the control signal applied from the outside, the two currents constituting the first current mirror circuit While temporarily lowering the potential of the gate of the transistor, when the standby control transistor enters the standby state with the basic bias circuit in response to the control signal applied from the outside, the first current A bias circuit, comprising: a start-up control circuit that is electrically non-conductive to gates of two transistors forming a mirror circuit. 2. The start-up control circuit according to claim 1, wherein the start-up control circuit includes a start-up control first transistor having the same polarity as two transistors forming the first current mirror circuit, and two transistors forming the second current mirror circuit. And a second transistor for start control of the same polarity is connected in series between the gates of two transistors constituting the first current mirror circuit and ground, and the respective gates are connected to each other. Wherein a control signal externally applied to the standby control transistor is applied together with the standby control transistor, and a capacitor is connected in parallel to the second start control transistor. Item 2. The bias circuit according to Item 1.