JPH01211144A - Cache memory - Google Patents

Abstract

PURPOSE:To improve an information processing speed by outputting the data in a cache to a CPU when a continuous access signal from the CPU is detected and an access address and a tag address are coincident. CONSTITUTION:When a memory access signal 6 comes from a CPU 1, it is judged by a read/write signal 9 whether or not the access is written. When the signal 9 is a reading signal and the access of a CPU is a continuous access signal 6, a tag address corresponding to the entry designated by a bit 2b of an address bus 2 is read to a comparator 14 and it is judged whether or not a cache hit is obtained. When the address of data stored in data memories 12a-12d is continuous while it is a cache hit, coincident to the data of the same address of a main memory, the data of a memory 12a designated by a decoding signal 11a are outputted to the CPU 1. Continuously, the data of memories 12a-12d are all outputted to the CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cache memory, and in particular,
The present invention relates to a cache memory (hereinafter simply referred to as cache) that can shorten address comparison time and improve instruction processing speed when a CPU accesses the cache memory by sequentially accessing some blocks.

(Prior art) In order to improve the processing speed of instructions in a data processing device, a part of the storage contents of the main memory device is copied to a cache provided inside the CPU, and most memory references are directed to this cache. A method is used to do this.

FIG. 3 shows a block diagram of the above data processing system having a cache. In the figure, the CPUI uses an address bus 2 and a data bus 3 to access a main memory 4 and a cache 5 connected to the buses 2 and 3.

The CPU is connected to the main memory 4 via the buses 2 and 3.
When accessing the cache 5, a memory access signal 6 is output from the CPUI to the cache 5. When the address specified by the access signal and the tag address of the cache 5 match (hit), the cache 5 outputs the data to the data bus 2, activates the acknowledge signal 7, and notifies the CPUI of the completion of the access.

On the other hand, if the data requested by the access from the CPUI is not found in the cache 5 (miss), the cache 5 outputs an operation signal 8 to the main memory 4 to operate the main memory 4.

The main memory device 4 activates the acknowledge signal 7 upon completion of the operation for access from the CPUI, and notifies the CPUI and the cache 5 of the completion of the access. CPUI accesses to the main storage device 4 and cache 5 include reading and writing, and this distinction is
The main storage device 4 and cache 5 are informed by read/write signals 9 output from the PUI.

In a data processing system such as the above configuration, the access speed to the main storage device is generally several to several times slower than the internal processing speed of the CPU. Therefore, if most memory references are made to the cache, a processing speed equivalent to the machine cycle of the CPU can be obtained.

In conventional caches, when an access from the CPU misses, the CPU refers to the necessary data from the main memory as described above, and at the same time transfers several tens of bytes of data including the necessary data to the cache. The data within is now updated.

In the above data processing system, in order to improve the processing speed of instructions, the CPU has a briefetch mechanism that fetches an instruction at the next address from the main memory 4 or cache 5 while one instruction is being executed. You may have one. Furthermore, as a control to improve processing speed, it is possible to fetch instructions several times ahead, instruction fetch (instruction fetch) of consecutive addresses,
It may also have a brief fetch mechanism called pipeline control that allows decoding (instruction decoding) and execution to be performed simultaneously. In this data processing method, a certain block is successively accessed to the cache 5, and in this case, the memory access signal 6 from the CPU
A signal indicating that the access is a continuous access of a certain block is added and output.

(Problems to be Solved by the Invention) The above-described conventional technology had the following problems.

In a data processing system having the above-mentioned brifetch mechanism, especially the above-mentioned vibe line control mechanism, if there is a jump instruction during program execution, the processing of the briefetched instruction is interrupted, and a briefetch must be performed again at the jump destination. . Since instructions have not yet been pre-fetched at the jump destination, it is desirable that a constant number of consecutive instructions be pre-fetched as quickly as possible after the jump.

However, in conventional caches, addresses are compared every time the CPU accesses, so the response time of the cache is determined by the address comparison time.
There was a problem that the processing speed could not be increased.

The present invention has been made to solve the above-mentioned problems.

(Means and Operations for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides means for detecting continuous access signals of a certain block of a CPU, and means for detecting continuous access signals of a certain block of a CPU, The access address and tag address are compared in a memory cycle, and if the two addresses match, in the second and subsequent memory cycles of the continuous access, the data in the cache is output to the CPU without comparing the two addresses. It is characterized in that it is equipped with a controller configured to do so.

In the present invention with the above configuration, continuous data in the cache is determined to be valid by comparing addresses only once, even when a certain block is accessed continuously from the CPU, so that a high-speed response can be achieved. Can be done.

(Example) The present invention will be described in detail below with reference to the drawings. 1st
The figure is a process diagram showing one embodiment of the present invention. In this figure, the same reference numerals as in FIG. 3 represent the same or equivalent parts.

In FIG. 1, the memory section 5a of the carriage L5 is divided into entries of the number of stages, and each entry is as follows.
Four data memories 12a to 12d and a tag memory 1 holding addresses of the data memories 12a to 12d.
0, and a valid bit 25 indicating that the addresses of data stored in all of the data memories 12a to 12d are consecutive and the data is the same as the data stored at the same address in the main storage device 4. ing.

The address bus 2 from the CPUI is divided into three parts, and the data of the lower two bits 2a of the address bus 2 is input to the block decoder 13. The data memory 12 is decoded by decoding outputs 11a to lid from the block decoder 13.
One block from a to 12d is selected. The data of the next high-order bit 2b of the address bus 2 is stored in the memory section 5a.
The data of bit 2b is input to tag memory 10, valid bit 25 and data memories 12a to 12a.
Entry 12d is selected. The data on the upper bit 2C of the address bus 2 is inputted to the comparator 14 and the gate 15.

The input/output line 16 of the tag memory 10 is connected to a comparator 14 and a gate 15, and the comparator 14 compares the tag address held in the tag memory 10 of the entry selected by the bit 2b with the upper bit 2C. A comparison is made with the data. As a result of comparison, upper bit 2
When the data in C and the tag address match (hereinafter referred to as a cash hit), a hit signal 17 is output to the controller 18. Gate 15 is controller 18
It is controlled by a control signal 24 output from the tag memory 10 and is opened when data in the tag memory 10 is updated.

Input/output lines 20 of data memories 12a-12d are connected to data bus 3 via gates 21. When reading and writing data to the data memories 12a to 12d, the controller 18 outputs a control signal 22 to the gate 21 to control the direction of opening and closing of the gate 21, and designates either reading or writing to the data memories 12a to 12d. Data update signals 23 are output respectively.

Furthermore, the controller 18 receives a memory access signal 6 from the CPU 1 (a signal indicating continuous access to some blocks is also added), a read/write signal 9
and the output 11d from the block decoder 13 are input, while the controller 18 outputs an acknowledge signal 7 to the CPUI and an operation request signal 8 to the main storage device 4.

Next, the operation of this embodiment with the above configuration will be explained with reference to the drawings. FIG. 2 is a flowchart showing the operation of the controller 18.

In the figure, first, in step S1, it is determined whether or not a memory access signal 6 has been received from the CPUI. If there is no access, the determination is negative and the process of step S1 is repeated, but if there is access, the determination is positive and the process proceeds to step S2. In step S2, it is determined based on the read/write signal 9 whether the access is for writing or not. If it is a write cycle, the determination in step S2 is affirmative and the process moves to step S3.

In step S3, the tag address corresponding to the entry specified by bit 2b of address bus 2 is read out to comparator 14 through turnout line 16, and it is determined whether or not it is a cash hit. In the case of a hit, the process advances to step S4. In step S4, the valid bit 25 of the entry selected by the bus lower bit 2b is set to "0" (invalidated).

In the write cycle, data is only stored in the main storage device 4, and the data memories 12a to 12 of the cache 5 are
No data is stored in d. Therefore, if there is a cache hit in the write cycle, the stored contents of the main storage device 4 and the stored contents of the data memories 12a to 12d will no longer match, so the valid bit 25 is invalidated in step S4.

After invalidating the valid bit 25, in step S5, the operation signal 8 is output to issue an operation request to the main memory device 4. In the main storage device 4, in response to the operation request, the CPU
Stores data output from I.

If the address represented by bit 2C of the lower bit 2C of the bus does not match the tag address held in the tag memory 10 of the entry selected by the lower bit 2b of the bus (hereinafter referred to as a cache miss), , step S
The determination in step S4 is negative and step S4 is skipped.
Proceeding to step S5, the operation request signal 8 is output to the main storage device 4.

In response to the operation request, the main storage device 4 takes in the data output from the CPUI, as in the case of the cash hit.

In step S6, it is determined whether the access by the CPU 1 has ended or not, and if the determination in step S6 is affirmative, the process returns to step S1.

Further, in step S2, if the read/write signal 9 is a read signal, the determination in step S2 is as follows:
If the result is negative, the process moves to step S7. In step S7, it is determined whether the access by the CPU 1 is a continuous access. Whether or not it is a continuous access is determined by the signal 6, and if it is a continuous access, the step S
The determination in step 7 is affirmative and the process advances to step S8.

In step S8, similarly to step S3, the tag address corresponding to the entry specified by bit 2b of the address bus 2 is passed through the input/output line 16 to the comparator 1.
4, and it is determined whether or not it is a cash hit. Whether or not it is a cash hit is determined by the signal 17 output from the comparator 14. If it is a cash hit, the determination in step S8 is affirmative, and the process proceeds to step S9.

In step S9, it is determined whether the valid bit 25 is "1". Valid bit 25 is “1°,
That is, if the addresses of the data stored in the data memories 12a to 12d are consecutive and match the data at the same address in the main storage device 4, the determination in step S9 is affirmative and the process proceeds to step SlO. .

In step S10, the data in the data memory 12a specified by the decode signal 11a is output to the CPUI. When the data is output to the CPUI, an acknowledge signal 7 notifying completion of output is output to the CPUI (step 511).

In step S12, it is determined whether or not the CPUI access has ended, and if the CPUI access has ended, the determination in step S12 is affirmative, and step S
Proceed to step 13. In step 813, it is determined whether the most significant decode signal lid has been output.

That is, in step S13, the decode signals 11a to 11a to 11a to
The last signal lid of lid is output and the data memory 1
It is determined whether all data 2a to 12d have been output to the CPUI. If the determination in step S13 is affirmative, the process returns to step S1. Still the top decode signal lid
If not, the determination in step S13 is negative and the process proceeds to step S14.

In step 514, the process waits until there is a remaining access in the constant series of accesses, and if there is an access, the determination in step S14 becomes affirmative and the process returns to step SIO. When the data in the data memory 12d is output in response to the highest decode signal lid, the determination in step S13 becomes affirmative and the process returns to step S1 as described above.

In the case of a cache miss, the hit signal 17 is not output, so the determination in step S8 is negative and the process proceeds to step S.
Proceed to step 15. Even if the valid bit is not "1", the determination in step S9 is negative and the process proceeds to step S15. In step S15, the control signal 2 from the controller 18 is
4, the gate 15 is opened, the data on the upper bus 2c is taken into the tag memory 10, and the tag address is updated. After the tag address is updated, the operation request signal 8 is output to the main storage device 4 in step S16.

When the main storage device 4 receives the operation request signal 8 and finishes outputting data to the CPU 1, it outputs an acknowledge signal 7.

In step S17, it is determined whether the controller 18 has detected the acknowledge signal, and if the acknowledge signal is detected, the determination in step S17 is affirmative and the process proceeds to step S18.

In step S1g, the same data as the data output from the main storage device 4 to the CPU 1 is taken into the data memory 12a in the cache.

In step S19, it is determined whether or not the CPUI access has ended, and if the CPUI access has ended, the determination in step S19 is affirmative, and step S2
Go to 0. In step S20, it is determined whether the highest decoded signal lid has been output. That is, in step S20, decode signals 11a to 11a to l that are successively output in consecutive memory accesses are
The last signal lid of id is output, and all data is input from the main storage device 4 to the data memories 12a to 12d.
It is determined whether or not the Still the highest decoded signal li
If d has not been output, the determination at step S20 is negative and the process advances to step S21.

In step S21, the process waits until there is a remaining access in a certain number of continuous accesses, and if there is an access, the determination in step S21 becomes affirmative and the process returns to step 816. When the data in the data memory 12d is updated in response to the highest decode signal lid, the determination in step S20 becomes affirmative and the process moves to step S22.

In step S22, the valid bit 25 is set to "1" to enable it. In other words, the valid bit 25 is “1”
indicates that all of the data stored in the data memories 12a to 12d has been updated, the addresses of the data are consecutive, and the data matches the content stored at the same address in the main storage device 4. . Once the valid bit 25 has been validated, the process returns to step S1.

Note that if it is determined in step S7 that the memory accesses from the CPUI are not continuous, step S7
The determination in step S23 is negative and the process moves to step S23.

In step S23, it is determined whether or not there is a cash hit. If it is a catch hit, the corresponding step S2
3 is affirmative, and the process advances to step S24. In step S24, it is determined whether the valid bit 25 is "1" or not, and if the valid bit 25 is "1°", step S2
Proceed to step 5. In step S25, the data in the data memory 12a specified by the decode signal 11a is output to the CPUI. When the data is output to the CPUI, an acknowledge signal 7 notifying completion of output is output to the CPU 1 (step 526).

In step S27, it is determined whether or not the access by the CPU 1 has ended, and if the access by the CPU 1 has ended, the determination in step S27 is affirmative, and step S27 is determined to be positive.
Return to 1.

If there is a cache miss in step S23,
The judgment in step S23 is negative and the process proceeds to step 32g.
Then, the operation request signal 8 is outputted from the controller 18 to the main storage device 4 . In step S24, even if the valid bit 25 is not "11", step 5211t
to move to. The main memory device 4 outputs data to the CPUI in response to the operation request signal 8, but the data in the cache 5 is not updated in response to the discontinuous access.

In this embodiment, as described above, when a certain block (4 blocks in this embodiment) is accessed consecutively, a signal indicating continuous access is output from the CPUI and is detected (as described above). Flowchart step S7
), only at the first memory access of the consecutive accesses,
The upper 2c of the address bus 2 and the tag address held in the tag memory 10 are compared. In this comparison, there is a cache hit, and the data memories 12a to 1
If valid bit 25, which indicates that the data in 2d is a continuous address, is valid (steps S8 and S9 in the flowchart above), tag addresses are not compared in the remaining accesses of the continuous accesses. So, I am trying to output the data in the cache.

(Effect of the invention) As is clear from the above explanation, according to the present invention, the CP
Comparison of tag addresses in the case of continuous access from U can be simplified, and the cache can now respond to the CPU at high speed. In other words, since it is not necessary to perform address comparison every time the CPU accesses, the address comparison time can be shortened.

Therefore, the prefetching of consecutive instructions after a jump instruction can be quickly performed, the prefetch mechanism of the CPU can function effectively, and the information processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of a controller, and FIG. 3 is a block diagram of an information processing system having a cache. DESCRIPTION OF SYMBOLS 1...CPU, 2...Address bus, 3...Data bus, 4...Main storage device, 5...Cache memory, 6...Continuous access signal, 7...Acknowledge signal, 8... Operation request signal, 9... Read/write signal, 10... Tag memory, 12a to 12d... Data memory, 14... Comparator, 18... Controller agent Patent attorney Hiraki Figure 1 Figure 2 (Part 1) Figure 2 (Part 3) Figure 3

Claims (1)

[Claims] (1) In a cache memory having a plurality of data memories corresponding to one tag address, means for determining whether memory access output from a CPU is continuous access, and the first memory cycle of the continuous access. means for detecting a cache hit; and a valid indicator that indicates validity when the addresses of data stored in the plurality of data memories are consecutive and the same data as the contents of the same address in the main storage device is stored. After detecting the bit, the signal indicating continuous access, the signal indicating cache hit, and the valid signal of the valid bit detected by the respective means, the data memory is read without comparing the access address and the tag address. A cache memory characterized by comprising a controller that outputs data to a CPU.