JPH01191461A - Ic package - Google Patents

Ic package

Info

Publication number
JPH01191461A
JPH01191461A JP63014741A JP1474188A JPH01191461A JP H01191461 A JPH01191461 A JP H01191461A JP 63014741 A JP63014741 A JP 63014741A JP 1474188 A JP1474188 A JP 1474188A JP H01191461 A JPH01191461 A JP H01191461A
Authority
JP
Japan
Prior art keywords
package
capacitor
bus capacitor
pie
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63014741A
Other languages
Japanese (ja)
Inventor
Tomoyuki Kaneko
伴行 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63014741A priority Critical patent/JPH01191461A/en
Publication of JPH01191461A publication Critical patent/JPH01191461A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To omit connection to an external capacitor, to remove high frequency noises and to implement high density mounting, by incorporating a bypass capacitor as a unitary body in an IC package, and connecting the capacitor between the power source pins of an IC element. CONSTITUTION:An insulating film 7 comprising dielectric material is provided between metal films 6a and 6b which are connected to power source pins 5a and 5b. A parallel-plate capacitor is formed and made to be a bypass capacitor 8. The capacitor can be incorporated as a unitary body in a space 1a of a package 1. Connection can be performed at the closest position to an IC element 2. Frequency noises generated in the IC element 2 can be effectively removed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路（ＩＣ）に関し、特にそのＩＣ
パッケージの構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit (IC), and in particular to a semiconductor integrated circuit (IC).
Concerning the structure of the package.

〔従来の技術〕[Conventional technology]

従来のＩＣは、樹脂やセラミックで構成したパッケージ
内にＩＣ素子のみを内蔵した構成となっている。このた
め、パッケージ内のＩＣ素子が動作したときに発生する
高周波のノイズを除去するためには、第３図に示すよう
に、ＩＣパッケージＰＫＧの外部において電源ＶＣ，，
Ｖ。６間にパイバスコンデンサＣを接続している。Conventional ICs have a structure in which only an IC element is housed in a package made of resin or ceramic. Therefore, in order to remove the high frequency noise generated when the IC element inside the package operates, as shown in FIG.
V. A pie bus capacitor C is connected between 6 and 6.

〔発明が解決しようとする課題］ 上述した従来のＩＣパッケージでは、内蔵したＩＣ素子
が高集積化、高速化されている場合には、外部に接続し
たパイバスコンデンサとＩＣ素子との間の長さが相対的
に長くなり、この部分から高周波ノイズが発生され易い
という問題がある。また、半導体メモリのように高集積
化、高速化の著しいＩＣでは、各個のＩＣパッケージの
夫々にパイバスコンデンサを近接配置して接続する必要
があり、ＩＣパッケージを基板上へ実装したときには、
これらパイバスコンデンサによって実装面積が大きくな
り、高密度実装が困難になるという問題もある。[Problems to be Solved by the Invention] In the conventional IC package described above, when the built-in IC element is highly integrated and high-speed, the length between the externally connected pie bus capacitor and the IC element is shortened. There is a problem in that the length is relatively long, and high frequency noise is likely to be generated from this portion. In addition, in ICs such as semiconductor memories that are becoming highly integrated and fast, it is necessary to connect pie bus capacitors to each IC package in close proximity to each other.
There is also the problem that these pie bus capacitors increase the mounting area, making high-density mounting difficult.

本発明は高周波ノイズを有効に除去するとともに、ＩＣ
パッケージの実装面積の低減を図ったＩＣパッケージを
提供することを目的としている。The present invention effectively removes high frequency noise and
The purpose is to provide an IC package with a reduced package mounting area.

［課題を解決するための手段］ 本発明のＩＣパッケージは、ＩＣ素子を収納するＩＣパ
ッケージ内にパイバスコンデンサを一体的に内装し、か
つこのパイバスコンデンサを前記ＩＣ素子に接続される
電源ピン間に接続している。[Means for Solving the Problems] The IC package of the present invention has a pie bus capacitor integrally housed within an IC package housing an IC element, and the pie bus capacitor is connected to a power supply pin connected to the IC element. connected between.

〔作用〕[Effect]

上述した構成のＩＣパッケージでは、ＩＣ素子とパイバ
スコンデンサとの間の長さを短くして高周波ノイズを有
効に除去し、かつＩＣパッケージへのパイバスコンデン
サの外付けを不要にして実装の高密度化を可能とする。In the IC package configured as described above, the length between the IC element and the pie bus capacitor is shortened to effectively remove high frequency noise, and it is not necessary to externally attach the pie bus capacitor to the IC package, thereby increasing the mounting efficiency. Enables densification.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention.

図において、セラミックパッケージ１の内部にはＩＣ素
子２を収納し、これをボンディングワイヤ３により金属
配線４を介して外部導出用のピンに電気接続している。In the figure, an IC element 2 is housed inside a ceramic package 1, and is electrically connected to a pin for external extraction via a bonding wire 3 and a metal wiring 4.

そして、これらピンの内、ここでは電源ピン（Ｖｃｃ）
５ａに接続された金属膜６ａと、他の電源ピン（ＶＥＥ
）　５　ｂに接続された金属膜６ｂとを夫々パッケージ
１のベースｌａ内に上下方向に対向して形成している。Among these pins, here is the power supply pin (Vcc)
5a and other power supply pins (VEE
) and metal films 6b connected to the metal films 5b and 6b are respectively formed in the base la of the package 1 so as to face each other in the vertical direction.

そして、これら金属膜６ａ、６ｂ間には誘電体からなる
絶縁膜７を介挿し、これら金属膜６ａ、金属膜６ｂ及び
絶縁膜７で平行平板コンデンサを形成し、これをパイバ
スコンデンサ８として構成している。Then, an insulating film 7 made of a dielectric material is inserted between these metal films 6a and 6b, and a parallel plate capacitor is formed by these metal films 6a, 6b, and insulating film 7, and this is configured as a pibus capacitor 8. are doing.

したがって、このＩＣパッケージでは、電源ピン５ａ、
５ｂ間に接続するパイバスコンデンサ８をパッケージ１
のベースｌａ内に一体的に内装しているので、ＩＣ素子
２に最も近接した位置において接続を行うことができ、
ＩＣ素子２で発生する高周波ノイズを有効に除去するこ
とができる。Therefore, in this IC package, power pin 5a,
The pie bus capacitor 8 connected between 5b and 5b is connected to package 1.
Since it is integrated inside the base la of the IC element 2, connection can be made at the position closest to the IC element 2.
High frequency noise generated in the IC element 2 can be effectively removed.

また、ＩＣパッケージに外部パイバスコンデンサを接続
する必要がないので、ＩＣパッケージの実装を高密度に
行うことが可能となる。Furthermore, since there is no need to connect an external pie bus capacitor to the IC package, the IC package can be mounted with high density.

なお、絶縁膜７の材料を変えることにより、内蔵のパイ
バスコンデンサの容量及び特性を変化できることは言う
までもない。It goes without saying that by changing the material of the insulating film 7, the capacitance and characteristics of the built-in pie bus capacitor can be changed.

第２図は本発明の第２実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.

図において、ここではＩＣ素子（図示せず）を樹脂封止
して外部導出用のピン１２を突出しているモールドパッ
ケージ１１の内部の一部に、パイバスコンデンサ１３を
封入し、このパイバスコンデンサの電極１４を電源ピン
１２ａと接続し、他方の電極（図示せず）を電源ピン１
２ｂに接続している。In the figure, a piebus capacitor 13 is sealed in a part of the inside of a molded package 11 in which an IC element (not shown) is sealed with resin and a pin 12 for leading out to the outside is protruded. electrode 14 is connected to power pin 12a, and the other electrode (not shown) is connected to power pin 1
Connected to 2b.

この実施例においても、モールドパッケージ１１内にパ
イバスコンデンサ１３を内蔵することにより、外部コン
デンサの接続を不要にして、高周波ノイズの除去及び高
密度実装を実現できる。In this embodiment as well, by incorporating the pibus capacitor 13 in the molded package 11, it becomes unnecessary to connect an external capacitor, and high-frequency noise can be eliminated and high-density packaging can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＩＣパッケージ内にパイ
バスコンデンサを一体的に内装し、かつこのパイバスコ
ンデンサをＩＣ素子の電源ピン間に接続することにより
、ＩＣ素子に近接してパイバスコンデンサを接続でき、
ＩＣ素子とパイバスコンデンサとの間の長さを短くして
高周波ノイズを有効に除去できる。また、ＩＣパッケー
ジへのパイバスコンデンサの外付けを不要にし、部品点
数の低減及び実装の高密度化を実現できる効果がある。As explained above, the present invention provides a pie bus capacitor in close proximity to the IC element by integrally incorporating a pie bus capacitor in an IC package and connecting the pie bus capacitor between the power supply pins of the IC element. can be connected,
High frequency noise can be effectively removed by shortening the length between the IC element and the bypass capacitor. Further, it is not necessary to externally attach a pibus capacitor to the IC package, which has the effect of reducing the number of parts and increasing the packaging density.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１実施例の縦断面図、第２図は本発
明の第２実施例の一部破断斜視図、第３図は従来構成の
模式的な回路図である。 １・・・パッケージ、１ａ・・・パッケージベース、２
・・・半導体集積回路、３・・・ボンディングワイヤ、
４・・・金属配線、５ａ、５ｂ・・・電源ピン、６ａ、
６ｂ・・・金属膜、７・・・絶縁膜、８・・・パイバス
コンデンサ、１１・・・モールドパッケージ、１２・・
・ピン、１２ａ。 １２ｂ・・・電源ピン、１３・・・パイバスコンデンサ
、１４・・・電極、ＰＫＧ・・・パッケージ、Ｃ・・・
パイバスコンデンサ。 第１図 第２図 １１　モ、Ｉレドバ７１−ン′ ２ａ 第３図FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a partially cutaway perspective view of a second embodiment of the present invention, and FIG. 3 is a schematic circuit diagram of a conventional configuration. 1...Package, 1a...Package base, 2
... Semiconductor integrated circuit, 3... Bonding wire,
4... Metal wiring, 5a, 5b... Power pin, 6a,
6b...Metal film, 7...Insulating film, 8...Pibus capacitor, 11...Mold package, 12...
・Pin, 12a. 12b... Power supply pin, 13... Pibus capacitor, 14... Electrode, PKG... Package, C...
Pibus capacitor. Figure 1 Figure 2 11 Figure 3

Claims (1)

【特許請求の範囲】[Claims] １、半導体集積回路を収納するＩＣパッケージにおいて
、ＩＣパッケージ内にパイバスコンデンサを一体的に内
装し、かつこのパイバスコンデンサを前記半導体集積回
路に接続される電源ピン間に接続したことを特徴とする
ＩＣパッケージ。1. An IC package for housing a semiconductor integrated circuit, characterized in that a pie bus capacitor is integrally housed within the IC package, and the pie bus capacitor is connected between power supply pins connected to the semiconductor integrated circuit. IC package.
JP63014741A 1988-01-27 1988-01-27 Ic package Pending JPH01191461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63014741A JPH01191461A (en) 1988-01-27 1988-01-27 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63014741A JPH01191461A (en) 1988-01-27 1988-01-27 Ic package

Publications (1)

Publication Number Publication Date
JPH01191461A true JPH01191461A (en) 1989-08-01

Family

ID=11869544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63014741A Pending JPH01191461A (en) 1988-01-27 1988-01-27 Ic package

Country Status (1)

Country Link
JP (1) JPH01191461A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475264A (en) * 1992-07-30 1995-12-12 Kabushiki Kaisha Toshiba Arrangement having multilevel wiring structure used for electronic component module
US5523622A (en) * 1992-11-24 1996-06-04 Hitachi, Ltd. Semiconductor integrated device having parallel signal lines

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475264A (en) * 1992-07-30 1995-12-12 Kabushiki Kaisha Toshiba Arrangement having multilevel wiring structure used for electronic component module
US5523622A (en) * 1992-11-24 1996-06-04 Hitachi, Ltd. Semiconductor integrated device having parallel signal lines

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