JP2917629B2 - Bypass circuit - Google Patents

Bypass circuit

Info

Publication number
JP2917629B2
JP2917629B2 JP30865891A JP30865891A JP2917629B2 JP 2917629 B2 JP2917629 B2 JP 2917629B2 JP 30865891 A JP30865891 A JP 30865891A JP 30865891 A JP30865891 A JP 30865891A JP 2917629 B2 JP2917629 B2 JP 2917629B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit board
circuit
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP30865891A
Other languages
Japanese (ja)
Other versions
JPH05211278A (en
Inventor
健一 国藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP30865891A priority Critical patent/JP2917629B2/en
Publication of JPH05211278A publication Critical patent/JPH05211278A/en
Application granted granted Critical
Publication of JP2917629B2 publication Critical patent/JP2917629B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はバイパス回路に関し、特
に混成集積回路を高密度で実装した場合の高周波信号の
バイパス回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bypass circuit, and more particularly to a bypass circuit for a high frequency signal when a hybrid integrated circuit is mounted at high density.

【0002】[0002]

【従来の技術】従来、混成集積回路の電源系端子に使用
されるバイパス回路としては、図3に示す金属ケース1
1内にバイパス用のチップコンデンサ14を設けた場合
と、図4に示す金属ケースの外側にバイパス用のコンデ
ンサ15を設ける場合がある。図4,図5において、1
1は金属ケース、12は入出力端子、13は電源系端
子、14は内部のバイパス用のチップコンデンサ、15
はバイパス用のコンデンサである。
2. Description of the Related Art Conventionally, as a bypass circuit used for a power supply system terminal of a hybrid integrated circuit, a metal case 1 shown in FIG.
There is a case where a bypass chip capacitor 14 is provided in 1 and a case where a bypass capacitor 15 is provided outside the metal case shown in FIG. 4 and 5, 1
1 is a metal case, 12 is an input / output terminal, 13 is a power supply terminal, 14 is an internal bypass chip capacitor, 15
Is a bypass capacitor.

【0003】[0003]

【発明が解決しようとする課題】上述した従来の混成集
積回路のバイパス回路は金属ケースの内側にバイパス用
チップコンデンサを実装する場合には、通常混成集積回
路の主要回路が金属ケース11の大部分を占有するの
で、チップコンデンサに大容量の物を使用できず、低周
波領域でのバイパス効果が著しく低下するという欠点が
ある。また主要回路が大きくなると、金属ケース11内
にチップコンデンサを実装できない場合も生じた。一方
金属ケース11の外側にバイパス用コンデンサを実装す
る場合には、個別コンデンサの一方のリード線を金属ケ
ースの端子部に取り付け、他の一方をアースラグ等に取
り付ける構造である。この様な構造だとコンデンサのリ
ード線が長くなり、リードインダクタンスによりバイパ
スは外形形状も大きく、実装のために場所を占有するの
で、混成集積回路を高密度に実装できないという欠点も
あった。
In the above-described conventional bypass circuit of a hybrid integrated circuit, when a bypass chip capacitor is mounted inside a metal case, the main circuit of the hybrid integrated circuit is usually a large part of the metal case 11. Therefore, a large-capacity chip capacitor cannot be used, and the bypass effect in a low frequency region is significantly reduced. In addition, when the size of the main circuit is large, a chip capacitor cannot be mounted in the metal case 11 in some cases. On the other hand, when a bypass capacitor is mounted outside the metal case 11, one lead wire of the individual capacitor is attached to a terminal portion of the metal case, and the other is attached to a ground lug or the like. With such a structure, the lead wire of the capacitor becomes long, and the bypass has a large external shape due to the lead inductance and occupies a space for mounting. Therefore, there is a disadvantage that the hybrid integrated circuit cannot be mounted at a high density.

【0004】[0004]

【課題を解決するための手段】本発明のバイパス回路は
金属ケース内にモノリシック回路又はチップ状の個別半
導体と内部のバイパス回路部を実装した混成集積回路本
体と、積層回路基板の一端に前記混成集積回路本体の端
子配列に対応した取付穴と電源系端子とを設け、他端に
接地用導体を設け前記電源系端子と接地用導体間に積層
チップコンデンサを搭載しこの積層回路基板の取付穴を
介して前記電源系端子と前記混成集積回路の端子とを接
続し、この積層回路基板の接地用導体部と前記混成集積
回路本体の底面の該混成集積回路本体を取り付ける金属
ケース間の接触を良くするために挿入したばね性の金属
片の片端又は両端を延長して半田等で接地している。
SUMMARY OF THE INVENTION A bypass circuit according to the present invention comprises a hybrid integrated circuit body in which a monolithic circuit or a chip-shaped individual semiconductor and an internal bypass circuit portion are mounted in a metal case, and the hybrid circuit is provided at one end of a laminated circuit board. A mounting hole corresponding to the terminal arrangement of the integrated circuit body and a power supply terminal are provided, a grounding conductor is provided at the other end, and a multilayer chip capacitor is mounted between the power supply terminal and the grounding conductor. The power supply system terminal and the terminal of the hybrid integrated circuit are connected through a contact between the grounding conductor of the multilayer circuit board and the metal case for mounting the hybrid integrated circuit body on the bottom surface of the hybrid integrated circuit body. One or both ends of a resilient metal piece inserted for extension are extended and grounded by solder or the like.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例である混成集積回路とバイ
パス回路の回路図である。図2は本実施例の構造図であ
り、図2(a)は平面図、図2(b)は側面図である。
図1,図2において、1は金属ケース、1Aは混成集積
回路本体、2は混成集積回路内に実装した内部のバイパ
ス回路部、3は混成集積回路本体の電源系端子の両端側
に設けた積層回路基板、4は積層回路基板上に搭載した
積層チップコンデンサ、5はばね性金属片、6は入出力
端子、7は主として電源系端子,8は固定ねじ、9は積
層回路基板に設けた取付穴である。図2(a),(b)
からわかるように、積層回路基板3の一方の端に混成集
積回路本体1Aの電源系端子7の配列に対応した取付穴
9と、取付穴9を含めた導体を設け、他の端に接地用導
体5Aを設け、この導体間に積層チップコンデンサ4を
搭載する。この時接地用導体5Aは導通穴又はサイドコ
ンタクト等により積層回路基板の裏側に拡大してもよ
い。この積層回路基板の取付穴9に、混成集積回路本体
1Aの電源系端子7を通して半田等で固定する。一方、
混成集積回路本体1Aを金属ケース1に固定ねじ8で取
り付ける場合に、混成集積回路の底面部が金属ケース1
に良く接触するようにバネ性金属5を挿入する。この
時、このばね性金属片5の片方又は両方を混成集積回路
の入出力端子6の方向に延長し、この先端を積層回路基
板3の接地用導体部5Aに半田付け等により固定し接地
する。この様な構造になっているので、電源系端子7に
現われる不要波成分は積層チップコンデンサ4を介して
最短で接地される。電源系端子7から接地場所までの距
離が短いためにリードインダクタンスによるバイパス効
果の低下を防止できる。またバイパスする周波数成分で
積層チップコンデンサの最適容量を決めることにより周
波数の高低に応じ良いバイパス効果を得ることができ
る。また本バイパス回路は混成集積回路本体1Aの電源
系端子7の部分にチップコンデンサを取り付けることが
できるので、混成集積回路を高密度で実装できる。
Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a hybrid integrated circuit and a bypass circuit according to an embodiment of the present invention. 2A and 2B are structural views of the present embodiment. FIG. 2A is a plan view, and FIG. 2B is a side view.
1 and 2, 1 is a metal case, 1A is a hybrid integrated circuit main body, 2 is an internal bypass circuit portion mounted in the hybrid integrated circuit, and 3 is provided on both ends of a power supply system terminal of the hybrid integrated circuit main body. The laminated circuit board, 4 is a laminated chip capacitor mounted on the laminated circuit board, 5 is a resilient metal piece, 6 is an input / output terminal, 7 is a power supply terminal, 8 is a fixing screw, and 9 is provided on the laminated circuit board. Mounting hole. FIG. 2 (a), (b)
As can be seen from the figure, a mounting hole 9 corresponding to the arrangement of the power supply terminals 7 of the hybrid integrated circuit main body 1A and a conductor including the mounting hole 9 are provided at one end of the laminated circuit board 3, and the other end for grounding is provided. The conductors 5A are provided, and the multilayer chip capacitor 4 is mounted between the conductors. At this time, the grounding conductor 5A may be expanded to the back side of the laminated circuit board by a conduction hole or a side contact. The power supply system terminal 7 of the hybrid integrated circuit body 1A is fixed to the mounting hole 9 of the laminated circuit board by soldering or the like. on the other hand,
When the hybrid integrated circuit body 1A is attached to the metal case 1 with the fixing screw 8, the bottom of the hybrid integrated circuit is
The spring metal 5 is inserted so as to make good contact. At this time, one or both of the spring metal pieces 5 are extended in the direction of the input / output terminal 6 of the hybrid integrated circuit, and the tip is fixed to the grounding conductor 5A of the laminated circuit board 3 by soldering or the like and grounded. . With such a structure, unnecessary wave components appearing at the power supply system terminal 7 are grounded via the multilayer chip capacitor 4 at the shortest. Since the distance from the power supply system terminal 7 to the grounding location is short, it is possible to prevent a reduction in the bypass effect due to the lead inductance. By determining the optimum capacitance of the multilayer chip capacitor by the frequency component to be bypassed, a good bypass effect can be obtained according to the level of the frequency. Further, in this bypass circuit, a chip capacitor can be attached to the power supply system terminal 7 of the hybrid integrated circuit body 1A, so that the hybrid integrated circuit can be mounted at a high density.

【0006】[0006]

【発明の効果】以上説明したように本発明は、一方の端
に混成集積回路の端子配列に対応した取付穴と導体とを
設け、他端に接地用導体を設けた積層回路基板と積層チ
ップコンデンサとを取り付け、ばね性金属片の片端又は
両端を延長して積層回路基板の接地用導体に接続するこ
とにより、高い周波数に対してもリードインダクタンス
の少ないバイパス回路が可能となり、かつ高密度実装も
できるという効果がある。
As described above, the present invention provides a laminated circuit board and a laminated chip having a mounting hole and a conductor corresponding to the terminal arrangement of a hybrid integrated circuit at one end and a grounding conductor at the other end. By attaching a capacitor and extending one or both ends of the springy metal piece and connecting it to the grounding conductor of the laminated circuit board, a bypass circuit with low lead inductance is possible even at high frequencies and high-density mounting There is also an effect that can be.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

【図2】本実施例の構造を示す平面図(a),側面図
(b)である。
FIGS. 2A and 2B are a plan view and a side view, respectively, showing the structure of this embodiment.

【図3】従来のバイパス回路である。FIG. 3 is a conventional bypass circuit.

【図4】従来のほかのタイプのバイパス回路である。FIG. 4 is another type of conventional bypass circuit.

【符号の説明】[Explanation of symbols]

1,11 金属ケース 1A 混成集積回路本体 2 内部のバイパス回路部 3 積層回路基板 4 積層チップコンデンサ 5 ばね性金属片 5A 接地用導体 6,12 入出力端子 7,13 電源系端子 8 固定ねじ 9 取付穴 11 金属ケース 11A 混成集積回路 14 チップコンデサ 15 コンデンサ DESCRIPTION OF SYMBOLS 1, 11 Metal case 1A Hybrid integrated circuit main body 2 Internal bypass circuit part 3 Multilayer circuit board 4 Multilayer chip capacitor 5 Spring metal piece 5A Grounding conductor 6, 12 Input / output terminal 7, 13 Power supply terminal 8 Fixing screw 9 Mounting Hole 11 Metal case 11A Hybrid integrated circuit 14 Chip capacitor 15 Capacitor

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 金属ケース内にモノリシック回路又はチ
ップ状の個別半導体と内部のバイパス回路部を実装した
混成集積回路本体と、積層回路基板の一端に前記混成集
積回路本体の端子配列に対応した取付穴と電源系端子と
を設け、他端に接地用導体を設け前記電源系端子と接地
用導体間に積層チップコンデンサを搭載しこの積層回路
基板の取付穴を介して前記電源系端子と前記混成集積回
路の端子とを接続し、この積層回路基板の接地用導体部
と前記混成集積回路本体の底面の該混成集積回路本体を
取り付ける金属ケース間の接触を良くするために挿入し
たばね性の金属片の片端又は両端を延長して半田等で接
地していることを特徴とするバイパス回路。
1. A hybrid integrated circuit body in which a monolithic circuit or a chip-shaped individual semiconductor and an internal bypass circuit section are mounted in a metal case, and mounting corresponding to a terminal arrangement of the hybrid integrated circuit body on one end of a laminated circuit board. A hole and a power supply terminal are provided, a grounding conductor is provided at the other end, a multilayer chip capacitor is mounted between the power supply terminal and the grounding conductor, and the power supply terminal is mixed with the power supply terminal through a mounting hole of the multilayer circuit board. A resilient metal which is connected to a terminal of an integrated circuit and which is inserted to improve the contact between a grounding conductor of the laminated circuit board and a metal case for mounting the hybrid integrated circuit body on the bottom surface of the hybrid integrated circuit body. A bypass circuit characterized in that one end or both ends of a piece are extended and grounded by solder or the like.
【請求項2】 前記積層回路基板の前記チップコンデン
サ取付表面に設けられた接地用導体が導通穴又はサイド
コンタクトにより前記積層回路基板の裏面にも拡大され
ていることを特徴とする請求項1記載のバイパス回路。
2. The multi-layer circuit board according to claim 1, wherein a grounding conductor provided on the chip capacitor mounting surface of the multi-layer circuit board is also enlarged on the back surface of the multi-layer circuit board by a conduction hole or a side contact. Bypass circuit.
JP30865891A 1991-11-25 1991-11-25 Bypass circuit Expired - Lifetime JP2917629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30865891A JP2917629B2 (en) 1991-11-25 1991-11-25 Bypass circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30865891A JP2917629B2 (en) 1991-11-25 1991-11-25 Bypass circuit

Publications (2)

Publication Number Publication Date
JPH05211278A JPH05211278A (en) 1993-08-20
JP2917629B2 true JP2917629B2 (en) 1999-07-12

Family

ID=17983732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30865891A Expired - Lifetime JP2917629B2 (en) 1991-11-25 1991-11-25 Bypass circuit

Country Status (1)

Country Link
JP (1) JP2917629B2 (en)

Also Published As

Publication number Publication date
JPH05211278A (en) 1993-08-20

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Legal Events

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A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990323