JP3116782B2 - Circuit board with inductive cancellation capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention provides a capacitor having a reduced effective inductance component and a mounting structure thereof.
In particular, in connection with technology for reducing power supply noise on circuit boards and LSIs on which electronic components are mounted, the effective impedance of power supply noise reduction capacitors (hereinafter referred to as decaps) mounted on circuit boards and LSIs is reduced, thereby reducing The present invention relates to a device equipped with an induction canceling capacitor for improving frequency characteristics.

[0002]

2. Description of the Related Art As the prior art related to the present invention, focusing on the technology of decaps, an insertion type with leads or a leadless surface mount type is used for decaps. The decap is mounted on a board for the purpose of absorbing power supply noise. FIG. 9 shows a diagram in which a decap is mounted on a substrate, and FIG. 10 shows an equivalent circuit of the decap. In the conventional mounting method, a “practical noise reduction technique” (Henry W.O.
As described on pages 311 to 313 of J.T.
It is shown by an equivalent circuit in which the inductance 11 exists in series with the capacitor 12 as shown in FIG.

Accordingly, the impedance characteristic of a decap is higher at a high frequency as shown in FIG. 12 than the frequency characteristic of a pure capacitor shown in FIG. FIG.
It can be said that the capacitance 12 in the equivalent circuit diagram 10 is dominant in the low frequency region A of 2 and the inductance 11 is dominant in the high frequency region B. Assuming that the value of the inductance 11 is L and the value of the capacitance 12 is C, the frequency at the boundary between the region A and the region B is as follows.
Series resonance frequency fr = 1 / 2π√LC in equivalent circuit diagram 10
Becomes From this equation, there are two ways to improve the frequency characteristics of the decap by reducing C or L.

When C is reduced, C must be reduced to 1/4 in order to double fr. For this reason, when C is reduced, the frequency characteristics of the individual capacitors are improved, but the total capacitance of the capacitors with respect to the current to be supplied is reduced. For this reason, when C of the decap is reduced, it is necessary to increase the number of decaps or separately connect decaps having a large capacity in parallel, which increases the number of components of the entire board.

On the other hand, when L is reduced, the frequency characteristics of the decap can be improved without reducing the total capacity of the decap. That is, in order to improve the frequency characteristics of the bypass capacitor without increasing the number of components, it is advantageous to reduce L of the bypass capacitor.

There are two ways to reduce L. One is a method of shortening the distance between a component requiring a current and a decap, and the length of a path through which a current flows, and the other is a method of canceling a magnetic flux generated by the current. In the former case, it is common to reduce the shape of each component or to reduce the interval between components.

In particular, since L in decaps is mostly composed of component leads and lead lines of mounting pads, a leadless surface mount type is used, the mounting pads are shortened, and through holes are formed in the mounting pads. A method of providing it has been devised. In addition, as disclosed in Japanese Patent Application Laid-Open No. 2-202049, there is a type in which a bypass capacitor is mounted inside an LSI package.

[0008]

The operating frequency of recent digital equipment and communication equipment has been increasing, and the frequency of current flowing during the operation of components such as ICs and LSIs has been increasing. In order to shorten the wiring length between them, a multilayer board (Mnlti-layer PCB (Printed Circuit B
oard), Multi-layer PWC (Printed Wired Board) etc., power supply layer and ground layer
(ground layer) and parts are often connected by through holes. However, even if the leadless lead of the leadless component or mounting pad is made as short as possible and the inductance is reduced in this way, the impedance of the decap does not become sufficiently small, and the power supply noise increases, and furthermore, the power supply noise is reduced. As a result, electromagnetic interference emitted from the substrate has increased. In order to reduce the power supply noise, the individual capacitors were reduced to improve the frequency characteristics of the decaps, and the number had to be increased. For this reason, the area of the bypass capacitor occupying the circuit board has increased, and the mounting efficiency of the circuit board has been reduced.

An object of the present invention is to provide a capacitor and a mounting structure of the capacitor in which the effective inductance component is reduced by solving such a problem. It is still another object of the present invention to provide a circuit board or an LSI package using a mounting method that improves the frequency characteristics of the decap by reducing the effective inductance of the decap by reducing the effective inductance of the decap by mounting such a capacitor or the capacitor. .

[0010]

In order to achieve the above object, an apparatus equipped with a capacitor according to the present invention comprises a capacitor, a conductor for supplying a current flowing through the capacitor, and at least one of the capacitor and the conductor. And a current path provided in close proximity to the portion, wherein the current flowing in the current path flows in the opposite phase to the current flowing in the capacitor and the conductor.

In the case of a circuit board on which a power supply noise reducing capacitor is mounted, a means is provided near the power supply noise reducing capacitor for flowing a current having a phase opposite to that of the power supply noise reducing capacitor.

A system for realizing a means for flowing a current of opposite phase syst
As em, a method in which a conductor is placed close to a capacitor to generate an induced current in a nearby conductor by the current flowing in the capacitor, a method in which the forward and return paths of the current are adjacent, and a method in which the same capacitor is mounted in the opposite direction And the like.

[0013]

With such a configuration, the present invention has the following functions and functions.

The present invention employs a method of reducing inductance by canceling out magnetic flux. 13 and 14 illustrate the principle of the present invention. As shown in FIG.
, A magnetic flux Φ is generated around it. When i changes with time, d changes with the time change di / dt of i.
Φ / dt occurs. This dΦ / dt generates an electromotive force V in the opposite direction to cancel i. At this time, the inductance L is defined by V = Ldi / dt.

On the other hand, when a current i2 = -i1 flows close to the current i1 as shown in FIG. 14, Φ1 + Φ2 = 0 near i1 and i2 due to Φ2 generated by i2, so that dΦ / dt = d (Φ1 + Φ2) / dt = 0, and no back electromotive force V is generated.

Actually, since Φ is not canceled between i1 and i2, V does not become zero, but the back electromotive force V becomes smaller than when only i1 flows. Therefore, by flowing a reverse current close to the capacitor, the apparent L and effective inductance of the capacitor can be reduced.

According to the present invention, power supply noise of the circuit board can be reduced without increasing the number of decaps.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment applied to a capacitor for reducing power supply noise and its mounting structure.

FIG. 1 is a view showing a first embodiment of the present invention, and FIG. 2 is a cross sectional view thereof.

In FIGS. 1 and 2, reference numeral 1 denotes a power supply noise reduction capacitor mounted on the substrate 6, 2 denotes a mounting pad for mounting the capacitor 1 provided on the substrate 6, and 3 denotes a conductive pad provided on the substrate 6. 4 are through holes provided in the substrate 6.

In this embodiment, the capacitor 1 is a leadless surface mount type capacitor, but there is no problem even if it is an insertion type capacitor with leads.

The surface mount type capacitor 1 is connected to the mounting pad 2 by soldering. One electrode of the capacitor 1 is connected to the power supply layer 7 through the mounting pad 2, the lead 3, and the through hole 4a as shown in FIGS. 1 and 2 (a).
Similarly, the other electrode is connected to the ground layer 8 via the mounting pad 2, the lead 3, and the through hole 4b. For convenience of description, the capacitor 1, the mounting pad 2, the lead wire 3, and the through hole 4 will be referred to as a decap component.

The wiring 5 is wired immediately next to the decap component and in parallel with the decap component. 1 and 2 (b)
As shown in FIG. 7, both ends of the wiring 5 are connected to the ground layer 7 through the through holes 4b. At this time, it is desirable that the length of the wiring 5 be the same as the distance d between the through hole 4a and the through hole 4b of the decap unit, or that the length be extremely small. The distance d determines the self-inductance of the decap component. If the distance d is too large, the inductance becomes too large, so the maximum should be about 5 mm. The current flowing through the decoupling component is induced in the wiring 5 in a direction opposite to the current flowing through the decoupling component.

The thickness of the wiring 5 is determined by the length of the lead 3
It is desirable that the thickness is approximately the same as
It is necessary to have a thickness of about 2 to 4 times. It is important to match the impedance of the wiring 5 with the impedance of the decap component, and the impedance of the decap component is determined by the lead 3. The reason why the thickness of the wiring 5 is limited is that if the wiring 5 is too thick, the coupling between the wiring and the ground layer becomes too strong, and the effect of improving the frequency characteristics of the decap cannot be obtained.

The wiring 5 is desirably provided as close as possible to the decoupling component. Since the minimum conductor spacing is defined by the wiring standard of the board, it is desirable that the distance be defined by the minimum conductor spacing. It is often about 0.15 mm. Even if the distance is longer than that, the effect is obtained. However, in the case of a frequency of about 100 MHz (megahertz), it is desirable to be about 0.3 mm from the calculation result of the crosstalk coefficient. If higher frequencies have to be considered, this value must be reduced in inverse proportion to the frequency.

According to this embodiment, it is not necessary to add a new component to flow a current in the opposite phase to the current flowing through the decap, and the frequency characteristic of the decap can be improved only by designing the pattern of the substrate. . Note that the same effect can be obtained by connecting both ends of the wiring 5 to the power supply layer 8 instead of the ground layer 7.

Next, a second embodiment of the present invention will be described with reference to FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals. Through-hole 4a of through-hole 4
Indicates a through hole connected to the power supply layer 7 and a through hole 4
b indicates a through hole connected to the ground layer 8 (the same applies to FIG. 4 and subsequent figures).

As shown in FIG. 3, in this embodiment, one of the lead-out lines 3 of the decap capacitor structure is wired to the side of the capacitor 1 so as to be parallel to the capacitor 1, and the lead-out line 3 is placed immediately next to the other through hole 4a. A through hole 4b is provided and connected to the inner layer. In the present embodiment, the lead wire 3 on the through hole 4b side connected to the ground layer 8 has the above-described configuration. However, the lead wire 3 on the through hole 4a side connected to the power supply layer 7 may have the above configuration. According to the present embodiment, it is not necessary to add a new component to flow a current having the opposite phase to the current flowing through the capacitor 1, and the frequency characteristic of the decap can be improved only by the pattern design of the substrate. Compared with the first embodiment shown in FIG. 1, there is an effect that the number of through holes is small and the wiring efficiency is not reduced.

FIG. 4 is a diagram showing a third embodiment of the present invention. In this example, the lead wire 3 is drawn out of the mounting pad 2 in the lateral direction with respect to the capacitor 1, two lead wires 3 are arranged close to each other, and connected to the through holes 4a and 4b, respectively. According to the present example, the current flowing through the lead wire 3 is a current pair 9 of opposite phase (indicated by an arrow in FIG. 4). According to this embodiment, it is not necessary to add a new component to flow a current having a phase opposite to that of the current flowing through the decap, and the frequency characteristic of the decap can be improved only by designing the pattern of the substrate. Since there is no current to cancel the current flowing through the capacitor part,
Although the effect of improving the frequency characteristics is inferior to those of the first and second embodiments, the mounting area can be reduced, and the mounting efficiency of the substrate can be improved.

FIG. 5 shows a fourth embodiment of the present invention. In this embodiment, the same decaps are mounted in parallel instead of the wiring 5 of the first embodiment shown in FIG. The through holes 4a at diagonal positions are connected to the power supply layer, and the remaining two through holes 4b are connected to the ground layer. As a result, the two capacitors 1 are mounted in parallel and electrically opposite directions. If the size of the capacitor is several mm or less, the current flowing through the two capacitors will have the same phase and the direction of the current will be reversed because the frequency is sufficiently small compared to the wavelength of the power supply noise of 1 GHz or less. This produces a canceling effect.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a diagram showing a capacitor used in the present embodiment, FIG. 8 is a diagram showing a substrate on which the capacitor shown in FIG. 6 is mounted, and FIG. 7 is a diagram showing another example of the capacitor used in the present embodiment. The capacitors shown in FIGS. 6 and 7 are called composite capacitors.

First, the composite capacitor shown in FIG. 6 will be described. Ordinary capacitors have a structure in which electrodes are connected to both ends of an insulator (dielectric). The composite capacitor is formed by attaching electrodes 10a to both ends of an insulator (dielectric) 10b to form a capacitor.
0c is bonded. As the insulator 10b, a material having a high dielectric constant such as ceramic is used. The dielectric constant of the insulator 10c is set to a value sufficiently lower than that of the insulator 10b so that a high-frequency current does not flow through the insulator 10c.

When three or more composite capacitors are joined, the insulator 10c is sandwiched between the capacitors as in the case of two. When an insulator having a polarity such as tantalum is used for the insulator 10b, the insulator 1
It is arranged and joined so that the polarity of 0b is alternately inverted.
With this composite capacitor, even when two or more capacitors are joined into one component and a high-frequency voltage is applied between the electrodes 10a of each capacitor, the path of current flow can be limited within the insulator 10b. It does not flow to the other capacitor.

Next, an example of another composite capacitor shown in FIG. 7 will be described. While the composite capacitor shown in FIG. 6 has two capacitors arranged side by side and joined, the present embodiment is characterized in that the capacitors are overlapped and joined up and down.
In this example, the electrode 1 is provided on an insulator 10b having a crank shape.
0a to form one capacitor. A capacitor having a shape opposite to that of this capacitor is formed, and the capacitors are joined together with an insulator 10c interposed therebetween to form a composite capacitor as one component. In this composite capacitor, the main current flowing through the capacitor flows through the central portion of the capacitor. Therefore, according to this example, the distance between the currents flowing through the respective capacitors can be made shorter than in the composite capacitor shown in FIG. Further, the distance of the current flowing in the opposite phase to each capacitor can be made longer than the mounting area. On the other hand, the composite capacitor shown in FIG. 6 has a simple shape and is easy to form.

In the case of a composite capacitor, the effect is obtained that the distance between the capacitors can be made narrower and the current overlapping in opposite phase becomes longer (coupling becomes stronger) as compared with individual capacitors.

FIG. 8 is a view showing a state where the composite capacitor shown in FIG. 6 is mounted on a substrate. 10 is a composite capacitor, 2 is a connection pad, 3 is a lead wire, and 4a and 4b are through holes. The two connection pads 2 at the diagonal positions are connected to the power supply layer 7 in the substrate via the lead 3 and the through hole 4a, and the two connection pads 2 at the remaining diagonal positions are connected to the lead 3 and the through-hole. It is connected to the ground layer 8 in the substrate through the hole 4b. The composite capacitor 10 is mounted such that a power supply and a ground are connected to both ends of each capacitor constituting the composite capacitor. Thus, voltages are alternately applied to the individual capacitors forming the composite capacitor 10 in opposite directions.

FIGS. 16 and 17 show diagrams in which a bypass capacitor is mounted on a substrate together with other components.

As shown in FIG. 17 , the power supply pin and the GND pin (ground pin) of the IC 14 and the current loop 16 formed by the decap component 13a according to the present invention are minimized so that the area of the current loop 16 is minimized. It is desirable to realize the decap unit 13b according to the present invention. Power supply pin and GND pin of LSI 15 and decapsulation unit 1 according to the present invention
3b so that the area of the current loop formed by 3b is minimized.
The decapsulation unit 13 according to the present invention is located very close to the LSI 15.
b is realized. When mounting components on both sides of the board, use I
It is mounted directly behind the C14 or the LSI 15 so as to minimize the loop area of the power supply current.

Further, as shown in FIG. 1 6, IC 14 and L
Even if it is far from the mounting position of the SI 15, the decoupling component 13 according to the present invention is provided in a place where the board is widely vacant or at an end of the board.
c of the present invention near the cable / connector for realizing the interface c and interfacing with an external board.
By realizing 3d, power supply noise generated on the entire board can be reduced, power supply noise can be suppressed from being transmitted to the cable, and electromagnetic interference can be reduced.

FIG. 18 is a perspective view in the case where the mounting structure of the present invention is used for an LSI package, and is similar to the case of the circuit board.

The LSi chip 22 is mounted on the substrate 19 and connected to the wiring on the substrate 19 by wire bonding 21. The wiring is drawn out to the end of the substrate and connected to the external connection lead 20. The power supply noise reduction capacitor is mounted on the substrate 19 as close to the LSi chip 22 as possible. FIG. 18 shows a hybrid IC as an example, but a power supply noise reduction capacitor is similarly mounted inside an LSi package such as a PGA (Pin Grid Array) or BGA (Pin Ball Array) having a multilayer structure to reduce power supply noise. Can be reduced.

[0042]

As described above, the case where the power supply noise is reduced has been described in detail. However, the present invention can be applied to any capacitor mounting apparatus which needs to reduce the effective inductance component of the capacitor as described above. Needless to say, there is.

Also in the case of the above-mentioned decap, the frequency characteristics of the power-supply-noise reducing capacitor (pass-con) can be improved and the power-supply noise can be reduced, so that a circuit malfunction or electromagnetic interference caused by the power-supply noise can be achieved. and the effect of such can be reduced without increasing the number of paths <br/> Con.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first embodiment of the present invention.

FIG. 3 is a diagram showing a second embodiment.

FIG. 4 is a diagram showing a third embodiment.

FIG. 5 is a diagram showing a fourth embodiment.

FIG. 6 is a diagram showing an example of a composite bypass capacitor.

FIG. 7 is a diagram showing another example of a composite decapacitor.

FIG. 8 is a diagram showing a fifth embodiment.

FIG. 9 is a diagram showing a conventional decap.

FIG. 10 is a diagram showing an equivalent circuit of a bypass capacitor.

FIG. 11 is a diagram showing frequency characteristics of a pure capacitor.

FIG. 12 is a diagram illustrating frequency characteristics of decaps.

FIG. 13 is a diagram showing a magnetic flux generated around a current.

FIG. 14 is a diagram showing a magnetic flux generated around a reverse current.

FIG. 15 is a diagram showing a current flow in the first embodiment.

FIG. 16 is a diagram showing a relationship with other components mounted on a substrate.

FIG. 17 is another view showing the relationship with other components mounted on the board.

FIG. 18 is an enlarged plan view of an LSI package to which the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Capacitor, 2 ... Connection pad, 3 ... Lead wire, 4
a, 4b: through hole, 5: wiring, 6: substrate, 7: power layer, 8: ground layer, 9: current pair of opposite phase, 10: composite capacitor, 10a: electrode, 10b: insulator (forming capacitor) , High dielectric constant), 10c ... insulator (for separating capacitors, low dielectric constant), 11 ... inductance, 12 ... capacitance, 13a-d ... decaps according to the present invention, 14 ... IC,
15 LSI, 16 current loop, 17 connector, 1
8. Cable.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-61610 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H05K 9/00

Claims (2)

(57) [Claims] (1) In a circuit board on which an integrated circuit is mounted, A capacitor mounted on the circuit board to reduce power supply noise
And It is provided in the vicinity of the condenser, and flows to the condenser.
And the capacitor for flowing a current having a phase opposite to that of the
Conductors connected to the ground or power layer at both ends
A circuit board comprising a body. (2) The length of the conductor is mounted by the capacitor
At a distance approximately equal to the distance between the two through holes
2. The circuit board according to claim 1, wherein the circuit board is connected to a ground or a power supply layer.
Board.