JP3680673B2 - Multilayer capacitors, wiring boards, decoupling circuits, and high-frequency circuits - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer capacitor, a wiring board, a decoupling circuit, and a high-frequency circuit, and in particular, a multilayer capacitor that can be advantageously applied in a high-frequency circuit, and a wiring board and a decoupling that are configured using the multilayer capacitor. The present invention relates to a circuit and a high frequency circuit.
[0002]
[Prior art]
Conventionally, the most typical multilayer capacitor is made of, for example, a ceramic dielectric, and a plurality of dielectric layers to be laminated as well as a dielectric while facing each other through a specific dielectric layer to form a plurality of capacitor units. A capacitor body having a plurality of pairs of first and second internal electrodes arranged alternately in the stacking direction of the body layers is provided. First and second external terminal electrodes are formed on the first and second end faces of the capacitor body, respectively. The first internal electrode extends to the first end surface of the capacitor body, and is electrically connected to the first external terminal electrode, and the second internal electrode extends to the second end surface. Extending and here electrically connected to the second external terminal electrode.
[0003]
In this multilayer capacitor, for example, a current flowing from the second external terminal electrode to the first external terminal electrode flows from the second external terminal electrode to the second internal electrode, and from the second internal electrode to the dielectric The first internal electrode passes through the layer, and then passes through the first internal electrode to the first external terminal electrode.
[0004]
An equivalent circuit of a capacitor is represented by a circuit in which CLR is connected in series, where the capacitance of the capacitor is C, the equivalent series inductance (ESL) is L, and the resistance of the electrode is mainly called the equivalent series resistance (ESR). It is.
[0005]
In this equivalent circuit, the resonance frequency (f₀) Is f₀= 1 / [2π × (L × C)^1/2Thus, it does not function as a capacitor at a frequency higher than the resonance frequency. In other words, if L, that is, the ESL value is small, the resonance frequency (f₀) Becomes higher and can be used at higher frequencies. Although it has been considered to use copper for the internal electrode to reduce the ESR, a capacitor with a low ESL is required for use in the microwave region.
[0006]
Also, a capacitor used as a decoupling capacitor connected to a power supply circuit that supplies power to an MPU chip (bare chip) of a microprocessing unit (MPU) such as a workstation or a personal computer is required to have low ESL. .
[0007]
FIG. 5 is a block diagram schematically illustrating an example of a connection configuration related to the MPU 1 and the power supply unit 2 described above.
[0008]
Referring to FIG. 5, MPU 1 includes MPU chip 3 and memory 4. The power supply unit 2 supplies power to the MPU chip 3, and a decoupling capacitor 5 is connected to a power supply circuit from the power supply unit 2 to the MPU chip 3. A signal circuit is configured from the MPU chip 3 to the memory 4 side.
[0009]
Even in the case of the decoupling capacitor 5 used in connection with the MPU 1 as described above, like the normal decoupling capacitor, it is used for noise absorption and smoothing against fluctuations in the power source. 3, the operating frequency of which exceeds 500 MHz and reaches 1 GHz is planned, and in applications where high-speed operation is required in connection with such MPU chip 3, the function as a quick power supply (A function for supplying electric power within a few nanoseconds from the amount of electricity charged in the capacitor when electric power at the time of rising or the like is suddenly required).
[0010]
More specifically, a certain MPU chip (operation clock frequency about 500 MHz) 3 is designed to supply about 2.0 V DC and consume about 24 W, that is, a current of about 12 A flows. In order to reduce the power consumption, a specification is adopted in which the power consumption is reduced to 1 W or less as a sleep mode when the MPU 1 is not operating. At the time of conversion from the sleep mode to the active mode, the MPU chip 3 needs to be supplied with power necessary for the active mode within the operation number of clocks. At an operating frequency of 500 MHz, it is necessary to supply power during a time period of 4 to 7 nanoseconds when converting from the sleep mode to the active mode.
[0011]
However, since it is not possible to supply the above-mentioned power from the power supply unit 2, the electric charge charged in the decoupling capacitor 5 placed in the vicinity of the MPU chip 3 is discharged until the power supply from the power supply unit 2 is supplied. By doing so, power is supplied to the MPU chip 3.
[0012]
For this reason, even in the decoupling capacitor 5 in the MPU 1, it is necessary that the inductance component be as low as possible. Thus, it is desired to realize a capacitor having a low inductance value.
[0013]
Under the background described above, a multilayer capacitor structure capable of reducing the ESL is proposed in, for example, Japanese Patent Application Laid-Open No. 11-204372.
[0014]
The above-mentioned low ESL is mainly due to cancellation of the magnetic field induced by the current flowing in the multilayer capacitor, and in order to cause such cancellation of the magnetic field, the direction of the current flowing in the multilayer capacitor is diversified. Has been done. And in order to diversify the direction of this current, by increasing the number of external terminal electrodes formed on the outer surface of the capacitor body, the lead portion of the internal electrode that is drawn out so as to be electrically connected to this is increased. In addition to increasing the number, the current length of the current flowing through the internal electrode is shortened.
[0015]
FIG. 6 schematically shows the multilayer capacitor 11 described in the above-mentioned Japanese Patent Application Laid-Open No. 11-204372, and shows a sectional structure of an MPU 12 using such a multilayer capacitor 11 as a decoupling capacitor. It is shown schematically.
[0016]
Referring to FIG. 6, the multilayer capacitor 11 includes a capacitor body 14 including a plurality of dielectric layers 13 to be stacked. In the capacitor body 14, at least a pair of first and second internal electrodes 15 and 16 that are opposed to each other with a specific dielectric layer 13 interposed therebetween are provided.
[0017]
Further, both the first and second external terminal electrodes 18 and 19 are provided on the first main surface 17 of the capacitor body 14 extending in parallel with the internal electrodes 15 and 16. No external terminal electrode is provided on the second main surface 20 facing the first main surface 17.
[0018]
The capacitor body 14 is further electrically connected to the first internal electrode 15 and the first external terminal electrode 18 while being electrically insulated from the second internal electrode 16. The second internal electrode 16 and the second external terminal electrode 19 are electrically insulated from the first through conductor 21 that penetrates the specific dielectric layer 13 and the first internal electrode 15. Second through conductors 22 that penetrate through the specific dielectric layer 13 are provided so as to be electrically connected.
[0019]
A plurality of the first and second through conductors 21 and 22 described above are provided, and the first and second external terminal electrodes respectively correspond to the first and second through conductors 21 and 22, respectively. A plurality of 18 and 19 are also provided.
[0020]
According to such a multilayer capacitor 11, the current flowing through the internal electrodes 15 and 16 can be shortened and directed in various directions, so that the magnetic field induced by the current flowing through the internal electrodes 15 and 16 can be reduced. As a result, and as a result, low ESL can be achieved.
[0021]
On the other hand, the MPU 12 includes a multilayer wiring board 24 in which a cavity 23 is provided on the lower surface side. An MPU chip 25 is surface-mounted on the upper surface of the wiring board 24. In addition, the above-described multilayer capacitor 11 that functions as a decoupling capacitor is accommodated in the cavity 23 of the wiring board 24. Further, the wiring board 24 is surface-mounted on the mother board 26.
[0022]
As schematically illustrated, wiring conductors necessary for the MPU 12 are formed on the surface and the inside of the wiring board 24, and the connection shown in FIG. 5 is achieved by these wiring conductors.
[0023]
A typical one will be described. Inside the wiring substrate 24, a hot-side electrode 27 for power supply and a ground electrode 28 are formed.
[0024]
The power hot electrode 27 is electrically connected to the first external terminal electrode 18 of the multilayer capacitor 11 via the power hot via hole conductor 29, and is connected to the MPU chip via the power hot via hole conductor 30. It is electrically connected to 25 specific terminals 31 and further electrically connected to a hot-side conductive land 33 to be connected to the mother board 26 via a hot-side via-hole conductor 32 for power supply.
[0025]
The ground electrode 28 is electrically connected to the second external terminal electrode 19 of the multilayer capacitor 11 via the ground via-hole conductor 34, and a specific terminal of the MPU chip 25 is connected via the ground via-hole conductor 35. 36 and is further electrically connected to a ground-side conductive land 38 to be connected to the mother board 26 via a ground via-hole conductor 37.
[0026]
In FIG. 6, a memory corresponding to the memory 4 shown in FIG. 5 is not shown.
[0027]
[Problems to be solved by the invention]
In the multilayer capacitor 11, both the first and second external terminal electrodes 18 and 19 are positioned on the first main surface 17 of the capacitor body 14 as shown in FIG. 6. Therefore, for example, when paying attention to the wiring conductor having the ground potential, the second external terminal electrode 19 of the multilayer capacitor 11 passes through the ground via-hole conductor 34, the ground electrode 28, and the ground via-hole conductor 37 in the wiring substrate 24. After that, it is connected to the ground conductive land 38.
[0028]
Therefore, the ground lines provided by the ground via-hole conductors 34 and 37 and the ground electrode 28 are relatively long, the inductance component generated in association with such a ground line is increased, and the ESL is reduced. The effect using the capacitor 11 will be reduced. A relatively long ground line also causes an increase in impedance.
[0029]
Further, the routing of the ground line as described above has a problem that the wiring in the wiring board 24 becomes complicated.
[0030]
Accordingly, an object of the present invention is to provide a multilayer capacitor and a wiring board, a decoupling circuit, and a high-frequency circuit configured using such a multilayer capacitor, which can solve the above-described problems. is there.
[0031]
[Means for Solving the Problems]
  The multilayer capacitor according to the present invention isAn MPU chip provided in the microprocessing unit is mounted, and is mounted on a wiring board including a hot-side wiring conductor for power supply and a ground wiring conductor for supplying power for the MPU chip, and is used as a power circuit for the MPU chip. A multilayer capacitor used as a decoupling capacitor to be connected,A capacitor body including a plurality of laminated dielectric layers is provided.
[0032]
In the capacitor body, at least a pair of first and second internal electrodes facing each other through a specific dielectric layer is provided.
[0033]
Further, the capacitor main body includes a plurality of first electrodes penetrating the specific dielectric layer in a state of being electrically insulated from the second internal electrode and electrically connected to the first internal electrode. And a plurality of second through conductors that penetrate the specific dielectric layer while being electrically insulated from the first internal electrode and electrically connected to the second internal electrode Are provided respectively. These first and second through conductors are arranged to cancel each other out of the magnetic field induced by the current flowing through the internal electrode.
[0034]
  Also, DoubleA plurality of first external terminal electrodes respectively corresponding to the individual first through conductors are electrically connected to the number of first through conductors.Only on the first main surface of the capacitor body extending parallel to the internal electrodesProvided. The first external terminal electrode is used so as to be electrically connected to the hot-side wiring conductor for power supply of the wiring board.
[0035]
  The plurality of second external terminal electrodes respectively corresponding to the respective second through conductors are electrically connected to the plurality of second through conductors, respectively, on the first main surface of the capacitor body. Is provided only on the second main surface opposite to. The second external terminal electrode is used so as to be directly connected to the ground side conductive land on the mother board on which the wiring board is mounted.
  The first through conductor extends so as to reach the first main surface of the capacitor main body but does not reach the second main surface, and the second through conductor extends to the second main surface of the capacitor main body. However, it extends so as not to reach the first main surface.
[0036]
As described above, the multilayer capacitor according to the present invention can be simply described. The plurality of first external terminals provided corresponding to each of the plurality of first through conductors connected to the first internal electrode. And a plurality of second external terminal electrodes provided corresponding to each of the plurality of second through conductors connected to the second internal electrode, wherein the first external terminal electrode is a capacitor body. The second external terminal electrode is provided on the first main surface, and the second external terminal electrode is provided on the second main surface.
[0037]
It is preferable that solder bumps are formed on the first and second external terminal electrodes described above.
[0039]
The present invention is also directed to a wiring board on which the multilayer capacitor as described above is mounted.
[0040]
As described above, when the present invention is directed to a wiring board, in one specific embodiment thereof, the MPU chip provided in the MPU is mounted on the wiring board, and the wiring board is used for the MPU chip. A power supply hot-side wiring conductor for supplying power and a ground wiring conductor are provided, and the first main surface of the capacitor body is directed to the wiring board side and the second main surface is directed outward. The multilayer capacitor is mounted, and in this mounted state, the first external terminal electrode is electrically connected to the hot-side wiring conductor for power supply. At this time, the second external terminal electrode faces outward and is provided for ground connection. When this wiring board is mounted on a motherboard, for example, it is electrically connected to the ground side conductive land on the motherboard. It is in a state that can be done.
[0041]
The first external terminal electrode and the hot-side wiring conductor for power supply described above are preferably connected via bumps.
[0042]
Preferably, the MPU chip is mounted on the first board surface of the wiring board, and an opening is positioned on the wiring board along the second board surface opposite to the first board surface. A cavity is provided. The multilayer capacitor is accommodated in the cavity with its second main surface facing the opening side of the cavity, and the second main surface and the second substrate surface are located on the same plane, A ground side conductive land electrically connected to the ground wiring conductor is formed on the substrate surface. By adopting such a configuration, the second external terminal electrode provided in the multilayer capacitor and the ground-side conductive land provided in the wiring board are located on the same side and on the same plane. .
[0043]
In the configuration described above, it is preferable that solder bumps are formed on the second external terminal electrode and the ground-side conductive land.
[0044]
The present invention is further directed to a decoupling circuit including the multilayer capacitor as described above.
[0045]
Furthermore, the present invention is also directed to a high frequency circuit including the multilayer capacitor as described above.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
1 to 3 show a multilayer capacitor 41 according to an embodiment of the present invention. Here, FIGS. 1 and 2 are plan views showing the internal structure of the multilayer capacitor 41, and FIGS. 1 and 2 show different cross sections. FIG. 3 is a cross-sectional view taken along line III-III shown in FIGS. 1 and 2.
[0047]
The multilayer capacitor 41 includes a capacitor body 43 including a plurality of dielectric layers 42 to be stacked. The dielectric layer 42 is made of, for example, a ceramic dielectric.
[0048]
Inside the capacitor main body 43, at least one pair of first and second internal electrodes 44 and 45 facing each other via a specific dielectric layer 42 are provided. In this embodiment, a plurality of pairs of first and second internal electrodes 44 and 45 are provided.
[0049]
The capacitor main body 43 further penetrates the specific dielectric layer 42 in a state of being electrically insulated from the second internal electrode 45 and electrically connected to the first internal electrode 44. A plurality of first through conductors 46 are provided. In addition, a plurality of second through conductors 47 penetrating the specific dielectric layer 42 in a state of being electrically insulated from the first internal electrode 44 and electrically connected to the second internal electrode 45. Is provided.
[0050]
  In addition, on the first main surface 48 of the capacitor main body 43 extending in parallel with the internal electrodes 44 and 45, each of the first main conductors 48 is electrically connected to the plurality of first through conductors 46. A plurality of first external terminal electrodes 49 respectively corresponding to the through conductors 46 are provided.Here, the first through conductor 46 reaches the first main surface 48 of the capacitor body 43, but extends so as not to reach the second main surface 50 facing the first main surface 48. The capacitor body 43 is in a non-penetrating state.
[0051]
  In addition, on the second main surface 50 of the capacitor main body 43 that faces the first main surface 48, each of the second main surfaces 50 is electrically connected to the plurality of second through conductors 47. A plurality of second external terminal electrodes 51 respectively corresponding to the through conductors 47 are provided.Here, the second through conductor 47 reaches the second main surface 50 of the capacitor main body 43 but extends so as not to reach the first main surface 48. is there.
[0052]
In this embodiment, a plurality of first and second internal electrodes 44 and 45 are provided, and the capacitance formed between each of the first and second internal electrodes 44 and 45 is the first and second internal electrodes 44 and 45. The two through conductors 46 and 47 are connected in parallel, and the capacitance thus connected in parallel is taken out between the first and second external terminal electrodes 49 and 51.
[0053]
The first through conductor 46 and the second through conductor 47 described above are arranged so as to cancel each other out of the magnetic fields induced by the currents flowing through the internal electrodes 44 and 45. That is, in this embodiment, the first and second through conductors 46 and 47 are arranged so as to be adjacent to each other, and the directions of the currents flowing through the internal electrodes 44 and 45 are diversified and the current length To shorten the ESL.
[0054]
In this embodiment, the first and second external terminal electrodes 49 and 51 include conductive pads 52 and 53 and solder bumps 54 and 55 formed thereon, respectively.
[0055]
The conductive pads 52 and 53 are made of, for example, a Cr / Ni / Cu deposited film, and the internal electrodes 44 and 45 and the through conductors 46 and 47 are formed by baking of a conductive paste containing Ni, for example. The
[0056]
FIG. 4 is a diagram corresponding to FIG. 6 and shows an MPU 61 using the multilayer capacitor 41 according to the embodiment as described above as a decoupling capacitor.
[0057]
Referring to FIG. 4, MPU 61 includes a wiring board 62, and an MPU chip (bare chip) 64 is surface-mounted on first board surface 63 that is the upper surface side of wiring board 62.
[0058]
A cavity 66 is provided on the second substrate surface 65 side which is the lower surface side of the wiring substrate 62. The cavity 66 has an opening located along the second substrate surface 65.
[0059]
The multilayer capacitor 41 described above is accommodated in the cavity 66 with the second main surface 50 of the capacitor main body 43 facing the opening side of the cavity 66. At this time, the second main surface 50 of the capacitor body 43 and the second substrate surface 65 of the wiring substrate 62 are located on the same plane.
[0060]
Such a wiring board 62 is surface-mounted on a mother board 67.
[0061]
As schematically illustrated, wiring conductors necessary for the MPU 61 are formed on the surface and inside of the wiring board 62, and the connection shown in FIG. 5 is achieved by these wiring conductors.
[0062]
A typical one will be described. Inside the wiring conductor 62, a hot-side electrode 68 for power supply and a ground electrode 69 are formed.
[0063]
The power hot electrode 68 is electrically connected to the first external terminal electrode 49 of the multilayer capacitor 41 via the power hot via hole conductor 70, and is connected to the MPU chip via the power hot via hole conductor 71. The hot-side conductive lands 74 to be connected to the mother board 67 are electrically connected to the specific terminals 72 of the 64 via the hot-side via-hole conductors 73 for power supply.
[0064]
Although not shown in detail in FIG. 4, the hot-side connection portion described above is connected to the hot-side via-hole conductor 70 for power supply and the first external terminal electrode 49, and the hot-side via-hole conductor 71 for power supply and the terminal 72. In this connection, a connection via a bump is applied, and a solder bump is formed on the hot-side conductive land 74.
[0065]
On the other hand, the ground electrode 69 is electrically connected to a specific terminal 76 of the MPU chip 64 through the ground via-hole conductor 75 and further connected to the mother board 67 through the ground via-hole conductor 77. The side conductive land 78 is electrically connected.
[0066]
Although not shown in detail in FIG. 4, the connection portion on the ground side described above is connected to the ground via-hole conductor 75 and the terminal 76 through a bump, and the ground-side conductive land 78 is connected. A solder bump is formed.
[0067]
As a characteristic configuration in this embodiment, the second external terminal electrode 51 of the multilayer capacitor 41 is not connected to the ground electrode 69 in the wiring board 62 but directly connected to the mother board 67. As described above, the solder bump 55 (see FIG. 3) is formed on the second external terminal electrode 51, and is connected to the mother board 67 via the solder bump 55.
[0068]
Thus, according to this embodiment, since the second external terminal electrode 51 on the ground side in the multilayer capacitor 41 is directly connected to the motherboard 67, the ground line related to the multilayer capacitor 41 is made relatively short. Therefore, the inductance component and the impedance component can be reduced, and it is possible to sufficiently cope with the high frequency. Also, the wiring on the wiring board 62 can be simplified.
[0069]
In FIG. 4, a memory corresponding to the memory 4 shown in FIG. 5 is not shown.
[0070]
【The invention's effect】
  As described above, according to the multilayer capacitor in accordance with the present invention, the first and second internal electrodes facing each other are connected by the plurality of first and second through conductors on the outer surface of the capacitor body. Is provided with a plurality of first external terminal electrodes respectively corresponding to the respective first through conductors in a state of being electrically connected to the plurality of first through conductors, and a plurality of second through conductors A plurality of second external terminal electrodes respectively corresponding to the respective second through conductors are provided in a state of being electrically connected to the conductors, thereby reducing the ESL of the multilayer capacitor. ,Both the first and second through conductors are non-penetrating in the capacitor body,The first external terminal electrode is on the first main surface of the capacitor body.onlyIn addition, the second external terminal electrode is on the second main surface of the capacitor body.onlyIn addition, since the first and second external terminal electrodes are provided on different main surfaces, the following effects are exhibited when this multilayer capacitor is mounted on a wiring board. .
[0071]
  That is, when the multilayer capacitor is mounted with the first main surface facing the wiring board side, the first external terminal electrode is on the wiring board side.Hot side for power supplyAlthough electrically connected to the wiring conductor, the second external terminal electrodes on the second main surface can be directed outward. Therefore, the second main surface of the capacitor body, MaWhen the wiring board on which the multilayer capacitor is mounted is mounted on the mother board in the state facing the board side, it is possible to obtain a state in which the second external terminal electrode is directly connected to the ground side conductive land on the mother board. Therefore, the ground line related to the multilayer capacitor can be shortened, and accordingly, the increase of the inductance component and the impedance component can be prevented, and it becomes possible to sufficiently cope with the high frequency, and the multilayer capacitor itself as described above. It is possible to prevent the effects of lowering ESL from being diminished. In addition, since the wiring board does not require a wiring conductor for ground connection to the multilayer capacitor, wiring in the wiring board can be further simplified.
[0072]
For this reason, the multilayer capacitor according to the present invention can be advantageously used as, for example, a bypass capacitor or a decoupling capacitor in a high frequency circuit. In addition, in a decoupling capacitor used in combination with an MPU chip or the like provided in an MPU, a function as a quick power supply is required, but the multilayer capacitor according to the present invention itself has a low ESL, In addition, since it can be mounted on a wiring board in a state where an inductance component is not generated so much, it can sufficiently cope with a high-speed operation even if it is used for such a decoupling capacitor.
[0073]
  As described above, when the multilayer capacitor according to the present invention is used as the decoupling capacitor connected to the power supply circuit for the MPU chip included in the MPU, the first main circuit is provided on the wiring board side on which the MPU chip is mounted. The multilayer capacitor is mounted in such a posture that the surface is directed and the second main surface is directed outward. At this time, the MPU chip is mounted on the first substrate surface of the wiring substrate. The substrate is provided with a cavity in which an opening is positioned along a second substrate surface opposite to the first substrate surface, and the multilayer capacitor is in a state where the second main surface faces the opening side of the cavity. The second main surface and the second substrate surface are located on the same surface, and are electrically connected to the ground wiring conductor in the wiring substrate on the second substrate surface. Form ground side conductive land If in so that, MaThe second external terminal electrode and ground side conductive land for achieving ground connection to the board can be connected to the ground side conductive land on the motherboard side at once and efficiently.
[0074]
Further, in the multilayer capacitor according to the present invention, when solder bumps are formed on the first and second external terminal electrodes, or when solder bumps are formed on the ground side conductive land in the wiring board according to the present invention, high density is obtained. In addition to enabling mounting, it is possible to suppress the occurrence of parasitic inductance in the connection.
[Brief description of the drawings]
FIG. 1 is a plan view showing an internal structure of a multilayer capacitor 41 according to an embodiment of the present invention, with a cross section through which a first internal electrode 44 passes.
2 is a plan view showing the internal structure of the multilayer capacitor 41 shown in FIG. 1 with a cross section through which a second internal electrode 45 passes.
3 is a cross-sectional view of the multilayer capacitor 41, taken along line III-III shown in FIGS. 1 and 2. FIG.
4 is a cross-sectional view schematically showing a structure example of an MPU 61 using the multilayer capacitor 41 shown in FIGS. 1 to 3 as a decoupling capacitor. FIG.
FIG. 5 is a block diagram schematically showing a connection configuration related to the MPU 1 and the power supply unit 2 that are of interest to the present invention.
6 is a view corresponding to FIG. 4 and is a cross-sectional view schematically showing an example of the structure of an MPU 12 using a conventional multilayer capacitor 11 as a decoupling capacitor. FIG.
[Explanation of symbols]
1,61 MPU
2 Power supply
3,64 MPU chip
5 Decoupling capacitor
41 multilayer capacitors
42 Dielectric layer
43 Capacitor body
44 first internal electrode
45 Second internal electrode
46 First through conductor
47 Second through conductor
48 First main surface
49 First external terminal electrode
50 Second main surface
51 Second external terminal electrode
54,55 Solder bump
62 Wiring board
63 First substrate surface
65 Second substrate surface
66 cavity
67 Motherboard
68 Hot-side electrode for power supply
69 Ground electrode
70, 71, 73 Hot side via hole conductor for power supply
75,77 Ground via-hole conductor
78 Ground side conductive land

Claims (9)

A power supply for the MPU chip mounted on a wiring board, mounted with a power hot-side wiring conductor for supplying power for the MPU chip and a ground wiring conductor, mounted with an MPU chip for the microprocessing unit A multilayer capacitor used as a decoupling capacitor connected to a circuit,
A capacitor body including a plurality of dielectric layers to be laminated,
Inside the capacitor body, at least one pair of first and second internal electrodes facing each other through the specific dielectric layer is provided,
The capacitor body further penetrates the specific dielectric layer while being electrically insulated from the second internal electrode and electrically connected to the first internal electrode. A plurality of first through conductors and a specific dielectric layer are penetrated while being electrically insulated from the first internal electrode and electrically connected to the second internal electrode A plurality of second through conductors are respectively provided;
The first and second through conductors are arranged to cancel each other out of a magnetic field induced by a current flowing through the internal electrode;
A plurality of first external terminal electrodes respectively corresponding to each of the first through conductors in a state of being electrically connected to the plurality of first through conductors, and the internal electrodes of the capacitor body Provided only on the first main surface extending in parallel, the first external terminal electrode is used to be electrically connected to the power supply hot side wiring conductor of the wiring board,
A plurality of second external terminal electrodes respectively corresponding to each of the second through conductors are electrically connected to the plurality of second through conductors, respectively. Provided only on the second main surface opposite to the main surface, the second external terminal electrode is used so as to be directly connected to a ground side conductive land on a mother board on which the wiring board is mounted ,
The first through conductor extends so as to reach the first main surface of the capacitor body but does not reach the second main surface, and the second through conductor extends to the capacitor body. It reaches the second main surface but extends so as not to reach the first main surface.
Multilayer capacitor.   The multilayer capacitor according to claim 1, wherein solder bumps are formed on the first and second external terminal electrodes.   A wiring board on which the multilayer capacitor according to claim 1 is mounted. An MPU chip provided in a microprocessing unit is mounted, and includes a power supply hot-side wiring conductor and a ground wiring conductor for supplying power for the MPU chip,
The multilayer capacitor is mounted in a posture in which the first main surface is directed to the wiring board side and the second main surface is directed outward. In this mounted state, the first external terminal electrode The wiring board according to claim 3, wherein the wiring board is electrically connected to the hot-side wiring conductor for power supply.   The wiring board according to claim 4, wherein the first external terminal electrode and the hot-side wiring conductor for power supply are connected via a bump.   The MPU chip is mounted on a first substrate surface of the wiring board, and the wiring board has a cavity in which an opening is positioned along a second substrate surface opposite to the first substrate surface. The multilayer capacitor is housed in the cavity with the second main surface facing the opening side of the cavity, and the second main surface and the second substrate surface are the same. 6. The wiring board according to claim 4, wherein a ground side conductive land that is located on a surface and is electrically connected to the ground wiring conductor is formed on the second substrate surface. 7.   The wiring board according to claim 6, wherein solder bumps are formed on the second external terminal electrodes and the ground-side conductive lands.   A decoupling circuit comprising the multilayer capacitor according to claim 1.   A high frequency circuit comprising the multilayer capacitor according to claim 1.

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