JPH0117618B2 - - Google Patents

Info

Publication number
JPH0117618B2
JPH0117618B2 JP20798381A JP20798381A JPH0117618B2 JP H0117618 B2 JPH0117618 B2 JP H0117618B2 JP 20798381 A JP20798381 A JP 20798381A JP 20798381 A JP20798381 A JP 20798381A JP H0117618 B2 JPH0117618 B2 JP H0117618B2
Authority
JP
Japan
Prior art keywords
circuit
data
input
output
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20798381A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58111450A (ja
Inventor
Kiichi Matsuda
Takeshi Okazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20798381A priority Critical patent/JPS58111450A/ja
Publication of JPS58111450A publication Critical patent/JPS58111450A/ja
Publication of JPH0117618B2 publication Critical patent/JPH0117618B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
JP20798381A 1981-12-24 1981-12-24 デ−タの標本化速度変換回路 Granted JPS58111450A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20798381A JPS58111450A (ja) 1981-12-24 1981-12-24 デ−タの標本化速度変換回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20798381A JPS58111450A (ja) 1981-12-24 1981-12-24 デ−タの標本化速度変換回路

Publications (2)

Publication Number Publication Date
JPS58111450A JPS58111450A (ja) 1983-07-02
JPH0117618B2 true JPH0117618B2 (en:Method) 1989-03-31

Family

ID=16548731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20798381A Granted JPS58111450A (ja) 1981-12-24 1981-12-24 デ−タの標本化速度変換回路

Country Status (1)

Country Link
JP (1) JPS58111450A (en:Method)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783234B2 (ja) * 1984-05-30 1995-09-06 株式会社日立製作所 デイジタルフイルタ
JPH0828695B2 (ja) * 1989-04-17 1996-03-21 富士通株式会社 チャンネルアクセス方式

Also Published As

Publication number Publication date
JPS58111450A (ja) 1983-07-02

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