JPH01175753A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the degree of freedom of layout and raising the wiring efficiency of a chip as well and further, improve the degree of integration by selecting the size of cells, by causing a gate layer to be left even at a part other than a channel region in a master process and performing a metallization wiring after removing the gate layer at a needless connection part in a custom metallization process. CONSTITUTION:A master process where MOS transistors that are arranged systematically in a semiconductor wafer is formed and a custom metallization process where desired electronic circuits are formed are provided. In the master process, four pieces or more PMOS transistors as well as NMOS transistors are formed respectively as basic cells and gate layers 1 are patterned so that gate electrodes of the MOS transistors and the gate layers 1 having the same layers as those of the above gate electrodes are left even at regions other than channel regions and then, a plurality of the MOS transistors are connected one another by the gate layers 1. After that, in the custom metallization process, after a needless connection part between the MOS transistors, for example, the gate layers 1 of 1a and 1b are removed, metallization wiring, for example, 5 is applied and then, electronic circuits are made up by connection by the gate layers 1 and metallization wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor integrated circuit device using a method similar to a gate array method.

(Prior art) The gate array method is a method in which chips in which basic cells made of transistors are regularly and fixedly arranged in rows and columns are used in many types of random logic semiconductor integrated circuit devices. .

In other words, the board process (
Using the wafers that have completed the master process, and using different wiring masters for each product type, semiconductor integrated circuit devices with different functions are realized in a custom process.

A conventional gate array system will be explained with reference to FIG. 1(B). Here, we will explain a gate array based on CMOS transistors with polysilicon gates! The wiring is a two-layer metal wiring.

After forming a well in a silicon substrate (a), field oxidation is performed to form a diffusion region (b).

After forming the gate oxide film, a polysilicon layer that will become the gate layer is formed and patterned to form the gate electrode (
C), Forming source/drain regions in a self-aligned manner by ion implantation or diffusion using the gate electrode as a master (d) The steps up to this point are master steps and are common to all types.

After that, in order to form wiring for each type, one interlayer insulating film is formed and contact holes are formed (e), a first metal layer is formed and patterned, and f) one interlayer insulating film is formed and peer holes are formed. g), form a second metal layer thereon and pattern it to form the second layer wiring (e
),after that.

Apply passivation using the usual method.

In the conventional gate array method, in step (c) of forming a gate electrode in the master step, unnecessary portions of the gate layer are all removed so that each transistor constitutes a basic circuit. Therefore, the gate layer of the transistor cannot be changed in a custom process, and the logic gate can only be configured under limited conditions.As described above, there is a problem that the degree of freedom in layout is low.

Further, all connections between transistors are made by metal wiring (f, h, etc.) in a custom process.

Therefore, in order to increase wiring efficiency, metal wiring must be stacked in multiple layers.

Furthermore, since the size of the diffusion layer of the transistor is constant, there are only two possible cell sizes. Therefore, even if a small-sized transistor is sufficient in the circuit configuration, only a certain size of transistor is prepared, so only large-sized cells can be configured.
There may also be cases where it is necessary to use transistors with an unnecessarily large size. As a result, in terms of circuit configuration, it is suitable for configuring parts that require a large size, but is not suitable for configuring parts that require a small size.

(Purpose) The present invention allows the shape of the gate layer of a transistor to be changed even in a custom process, increasing the degree of freedom in layout, and also increases the metal wiring layer by allowing the gate layer to be used for wiring inside logic gate cells. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device using a method similar to a gate array method, which enables the wiring efficiency of a chip to be increased without any problem, and also allows the degree of integration to be improved by selecting the cell size. This is the purpose.

(Configuration) In the present invention, four or more PMOs are installed in the basic cell in the master process.
An S transistor and four or more NMOS transistors are formed, and the gate layer is patterned so that a gate layer of the same layer as the gate electrode of the IMOS transistor remains outside the channel region, and a plurality of MOS transistors are connected to each other by the gate layer. After removing unnecessary connection portions of the gate layer between MOS transistors in a custom process, metal wiring is applied, and an electronic circuit is constructed by the connection by the gate layer and the metal wiring.

Examples will be specifically described below.

In order to compare with the conventional gate array method shown in FIG. A Lee example will be explained with reference to FIG.

A well is formed in the silicon substrate, and a diffusion region is formed by field oxidation (b). This diffusion region consists of four PMOS transistors and four NMOS transistors in the basic cell.
It is formed to form a transistor.

Next, a gate oxide film is formed, a polysilicon layer that becomes a gate layer is formed on it, and the gate layer is patterned to form a gate electrode (c+).
As shown in Figure (A), in addition to the gate electrode, a connecting portion remains in the gate layer l so as to connect the gate electrodes of all the MOS transistors in the basic cell. Then, using the gate electrode as a master, impurities are introduced in a self-aligned manner by ion implantation or diffusion to form source/drain regions (d).

FIG. 2(A) shows the state after the source and drain have been formed. This is the master process, and the number of diffusion regions and the pattern of the gate layer are different from the conventional gate array method.

Referring back to FIG. 1A, next, in the customization process, circuits for each type are constructed.

First, unnecessary portions of the gate layer 2 are removed by etching (e2).

After that, as in the custom process of the conventional gate array method, after passing through contact formation (e), first metal process (f), peer hole formation (g), second metal process (h), etc., passivation is performed.

Figure 1 shows a comparison with the conventional gate array method.

Both of them use two-layer wiring, but the example (same figure (A)
)), the gate layer can also be used as wiring, so it is possible to achieve wiring efficiency equivalent to three-layer wiring.

Furthermore, in this embodiment, it is possible to configure a MOS transistor whose size is half that of the conventional gate array method.

FIG. 2(A) shows an example of a basic cell formed in the master process of the present invention.

After well formation, regions PL, Nl, N2 . . . for diffusion regions are formed by field oxidation. After forming P2, a polysilicon layer is formed and patterned by photolithography and etching to form a gate layer l. Gate layer 1 has each area PI
, Nl, N2. Connection portions 1a and 1b are provided not only in the region where the channel of P2 is formed, but also in areas other than the channel region for connecting the MOS transistors.

Thereafter, P-type impurities are introduced into the regions PL and P2 by ion implantation or diffusion, and N-type impurities are introduced into the regions Nl and N2 by ion implantation or diffusion. In this way, four PMOS transistors and four NMOS transistors are formed in the basic cell in the master process, and a circuit is obtained in which the gates of all the MOS transistors in the basic cell are interconnected.

A power supply Vcc line 2-1.2-2 is formed on the upper end of the P-type diffusion region P1 and on the lower end of the P-type diffusion region P2 by a first metal layer in a custom process.

An insulating film exists between the P-type diffusion regions Pi, P2 and the power supply lines 2-1, 2-2, and contact holes are formed as necessary to connect the P-type diffusion regions PI.

P2 and power line 2-1.2-2 are connected.

A ground GND line 3 is formed by a first metal layer in a custom process over the lower end of the N-type diffusion region N1 and the upper end of the N-type diffusion region N2. N-type diffusion regions Nl, N2
There is also an insulating film between the N-type diffusion region N and the ground line 3, and a contact hole is formed as necessary to
1, N2 and ground 3 are connected.

FIG. 2(B) shows an equivalent circuit of the basic cell shown in FIG. 2(A).

For comparison with the basic cell of this embodiment, FIG. 3A shows a basic cell of a conventional gate array.

For comparison, both basic cells have the same height and width.

In the basic cell of FIG. 3(A), two PMO8 transistors are formed in the P-type diffusion region P, and two PMO8 transistors are formed in the N-type diffusion region N.
NMo5 transistors are formed. 1 P
A MOS transistor and one NMOS transistor are connected through a gate layer 4, and another PMO8hMO
S transistors NMOS transistors are also connected through another gate layer 4. The respective gate layers 4, 4 are not connected to each other.

The power supply line 2 is formed on the P-type diffusion region P side, and the ground line 3 is formed on the N-type diffusion region N side by a first metal layer in a custom process. Connections between the diffusion region P and the power supply line 2 and between the diffusion region N and the ground line 3 are made by metal layers.

An equivalent circuit of the basic cell shown in FIG. 3(A) is shown in FIG. 3(B).

The basic cell in FIG. 2(A) and the basic cell in FIG. 3(A) are equivalent in terms of playing card ability.

FIG. 4(A) shows a small-sized inverter constructed using the basic cell of one embodiment, and its equivalent circuit is shown in FIG. 4(B).

A is an input terminal, and B is an output terminal. In this example, the area P
A CMOS inverter is constructed using the MOS transistors I and Nl on the left side.

FIGS. 5 and 6 each show an example in which a large-sized inverter is constructed of two PMOS transistors and two NMOS transistors.

In the example of FIG. 5, two PMOS transistors in region P1 and two NMOS transistors in region N1 are used. In this example, two sets of inverter cells shown in FIG. 4 are formed, and the gate electrodes of both inverters are connected by leaving the gate layer 1a.

Drain regions of two PMOS transistors and two N
The drain region of the MOS transistor is covered with the first metal layer 5 (
(thick solid line). The first metal layer 5 serves as the output B.

In the example of FIG. 6, areas Pl, Nl, N2. The MOS transistors on the left side of each P2 are used. Each gate electrode is connected by a gate layer including gate layer 1b. The drain regions of adjacent PMOS transistors and the drain regions of NMo5 transistors are connected via contact holes by first metal layer 5 (thick solid lines), and the drain regions of both NMO5 transistors are connected via peer holes to second metal layer 6 (thick solid lines). (dashed line),
The second metal layer 6 serves as the output B.

FIG. 7 shows a case where the inverter shown in FIG. 5 or 6 is constructed using conventional basic cells.

In FIG. 7, the left side portions of regions P and N are used.

FIG. 8(A) shows an example in which a flip-flop is constructed using the basic cell of one embodiment. The thick solid line represents the first metal layer, and the thick dashed line represents the second metal layer.One equivalent circuit is shown in FIG. 3B.

Output inverter 10.1 connected to output terminal 6t, 02
1 is configured to have a larger size than each transistor in the previous stage flip-flop. Those inverters 10.11
is the same as the inverter shown in FIG.
MO8) - contains a transistor and two NMo5 transistors. On the other hand, the transistors in the previous stage are composed of one PMO8 transistor and one NMo5 transistor.

When a flip-flop corresponding to the flip-flop in FIG. 8(B) is constructed using conventional basic cells, the result is as shown in FIG. 9. In FIG. 9, each transistor in the flip-flop must also be constructed with the same size as the transistors in the output inverter. Therefore, the cell size increases accordingly.

Although the transistors of the output inverter need to be large in size, the transistors in other logic circuits do not need to be as large in size as the output transistors. Therefore, while the flip-flop shown in FIG. 8(A) can be configured with three basic cells, the conventional flip-flop shown in FIG. 9 requires five basic cells, which reduces the proportion of the chip area. growing.

In this example, the number of transistors formed in one basic cell is 4 for both PMOS transistors and NMo5 transistors.
However, the present invention can also be applied to a case including a larger number of MOS transistors.

(Effects) In the present invention, the size of the diffusion region is made smaller than that of the conventional one, and four or more PMO5)-transistors and four
Since more than 2 NMo5 transistors are formed, it is possible to select a desired cell size. Since the size of the unit transistor is smaller than that of a conventional basic cell, a small-sized cell can be easily constructed.

Furthermore, by leaving the gate layer in areas other than the channel region, the gate electrodes of small-sized transistors remain connected, and by arranging the transistors horizontally or vertically, large-sized transistors can be easily constructed.

If the entire basic cell of a conventional gate array were to be made smaller, the source, drain, and gate would have to be connected using metal layers when constructing a large-sized transistor. In contrast, in the present invention, since transistors can be connected using gate layers, there is an effect that one metal layer can be omitted.

In this way, in the present invention, when a circuit is constructed using transistors of the required size, unnecessary large transistors are not used, which is advantageous in terms of area.

[Brief explanation of the drawing]

FIG. 1(A) is a flowchart showing the steps of one embodiment;
Figure 2 (B) is a flowchart showing the conventional gate array system, Figure 2 (A) is a plan view showing the basic cell of one embodiment, Figure 3 (B) is a circuit diagram showing its equivalent circuit, and Figure 3. (A
4(B) is a circuit diagram showing its equivalent circuit; FIG. 4(A) is a plan view showing a small inverter constructed using one embodiment; B) is its equivalent circuit diagram, FIGS. 5 and 6 are plan views each showing a large-sized inverter constructed using one embodiment, and FIG. 7 shows an inverter constructed using conventional basic cells. 8(A) is a plan view showing a flip-flop constructed using one embodiment, FIG. 8(B) is its equivalent circuit diagram, and FIG. 9 is a plan view showing a flip-flop constructed using a conventional basic cell. FIG. ■...Gate layer-1a, Ib...Gate layer connection part. 5.6...Metal layer, PL, P2. Nl, N2... Area for diffusion.

Claims (1)

[Claims] (1) It includes a master process in which regularly arranged MOS transistors are formed on a semiconductor wafer and a custom process in which a desired electronic circuit is formed.In the master process, a basic cell has four or more PMOS transistors and four or more NMOS of
A transistor is formed, and the gate layer is patterned so that the gate layer, which is the same layer as the gate electrode of the MOS transistor, remains outside the channel region and multiple MOS transistors are connected to each other by the gate layer, and in the custom process, the MOS transistor is A method of manufacturing a semiconductor integrated circuit device, in which an electronic circuit is constructed by removing unnecessary connection portions of a gate layer between the gate layers, and then applying metal wiring, thereby forming an electronic circuit by the connection by the gate layer and the metal wiring.