JPH01174962U - - Google Patents
Info
- Publication number
- JPH01174962U JPH01174962U JP7221388U JP7221388U JPH01174962U JP H01174962 U JPH01174962 U JP H01174962U JP 7221388 U JP7221388 U JP 7221388U JP 7221388 U JP7221388 U JP 7221388U JP H01174962 U JPH01174962 U JP H01174962U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- circuit board
- multilayer printed
- uniform
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
Description
第１図は、本考案の一実施例を示す平面図およ
び正面図である。第２図は、従来の多層プリント
基板例を示す平面図および正面図である。
１，１１……プリント基板、２，１２……外部
接続回路、３……レジスト塗布部、４……電子部
品、５，１５……プリント基板の端部、６……プ
リント基板実装方向を示す矢印、７……ソケツト
、８……装置本体。
FIG. 1 is a plan view and a front view showing an embodiment of the present invention. FIG. 2 is a plan view and a front view showing an example of a conventional multilayer printed circuit board. 1, 11... Printed circuit board, 2, 12... External connection circuit, 3... Resist coating section, 4... Electronic components, 5, 15... End of printed circuit board, 6... Indicates printed board mounting direction. Arrow, 7...Socket, 8...Device body.
Claims (1)
と同時に電気的に接続されている電子装置に使用
される多層プリント基板において、プリント基板
の端部の両面に、表面層および内層の配線面が一
定の幅で露出するよう部品実装面に平行な複数の
段を設け、前記複数の段のそれぞれに、プリント
基板実装方向に平行に一定間隔で同一幅の外部接
続用回路を並列に設けたことを特徴とする多層プ
リント基板構造。 In multilayer printed circuit boards used in electronic devices where the main body of the device and the printed circuit board are structurally coupled and electrically connected at the same time, the wiring surfaces of the surface layer and inner layer are uniform on both sides of the edge of the printed circuit board. A plurality of steps are provided parallel to the component mounting surface so as to be exposed with a width of Features a multilayer printed circuit board structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221388U JPH01174962U (en) | 1988-05-31 | 1988-05-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7221388U JPH01174962U (en) | 1988-05-31 | 1988-05-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01174962U true JPH01174962U (en) | 1989-12-13 |
Family
ID=31297387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7221388U Pending JPH01174962U (en) | 1988-05-31 | 1988-05-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01174962U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013115110A (en) * | 2011-11-25 | 2013-06-10 | Tanaka Kikinzoku Kogyo Kk | Printed wiring board of step structure |
-
1988
- 1988-05-31 JP JP7221388U patent/JPH01174962U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013115110A (en) * | 2011-11-25 | 2013-06-10 | Tanaka Kikinzoku Kogyo Kk | Printed wiring board of step structure |