JPH01161736A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPH01161736A
JPH01161736A JP62320332A JP32033287A JPH01161736A JP H01161736 A JPH01161736 A JP H01161736A JP 62320332 A JP62320332 A JP 62320332A JP 32033287 A JP32033287 A JP 32033287A JP H01161736 A JPH01161736 A JP H01161736A
Authority
JP
Japan
Prior art keywords
case
cap
package
peripheral wall
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62320332A
Other languages
Japanese (ja)
Inventor
Shuichi Kawai
川井 秀一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62320332A priority Critical patent/JPH01161736A/en
Publication of JPH01161736A publication Critical patent/JPH01161736A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the moisture resistance of a package by so forming a sealing path of a bonded part of a case with a cap covering the case in combination faces of obliques or uneven parts as to become longer than a horizontal linear distance. CONSTITUTION:In a package for a semiconductor device having a ceramic or glass case 1, a cap 2 covering the upper opening of the case 1, and a resin sealer 6 for sealing the bonded part of the case 1 with the cap 2, a sealing path between an inside and an outside of the bonded part is so formed in combination faces of obliques or uneven parts as to become longer than a horizontal linear distance. For example, the upper face of the peripheral wall of the case 1 is formed in its section with a protrusion shape. A recess to be engaged with the protrusion of the peripheral wall of the case is formed on the periphery of the cap 2 sealingly bonded with the case 1 by the sealer 6, and the protrusion of the peripheral wall of the case 1 is engaged through the sealer 6 with the recess of the periphery of the cap 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の樹脂シール相よるパッケージに
関し、特にパッケージの耐湿性を向上させる事に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package of a semiconductor device using a resin seal phase, and particularly relates to improving the moisture resistance of the package.

〔従来の技術〕[Conventional technology]

第3図は従来のパッケージを用いた半導体装置の断面図
である。第3図において、セラミック製のケース11の
中央凹所に半導体チップ7がマウントされ、チップ7の
電極とケース11の側面にとり付けられている外部リー
ド5につながっているケース11の肩部の配線との間を
ボンディングワイヤ8で接続後、ケース110周壁土面
にガラス製の板状のキャップ12を重ね、樹脂シール剤
6によりシールされている。
FIG. 3 is a sectional view of a semiconductor device using a conventional package. In FIG. 3, a semiconductor chip 7 is mounted in the central recess of a ceramic case 11, and wiring on the shoulder of the case 11 connects the electrodes of the chip 7 to the external leads 5 attached to the side of the case 11. After connecting with the bonding wire 8, a glass plate-shaped cap 12 is placed on the surface of the surrounding wall of the case 110, and the cap 12 is sealed with a resin sealant 6.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の従来のパッケージでは、ケース周壁土面のキャッ
プに対する接合面は周壁に対し直角な水平面となってい
る。そのため、パッケージの内側と外側との間に通じる
樹脂シール剤6によるシールバスは周壁の厚さに等しい
最短距離である。したがって、小さいパッケージでは周
壁の厚さも当然薄いものとなっているため、シールバス
も非常に短いものとなり、耐湿性が充分でないという欠
点があら。
In the conventional package described above, the joint surface of the earth surface of the case peripheral wall with the cap is a horizontal plane perpendicular to the peripheral wall. Therefore, the sealing bath formed by the resin sealant 6 between the inside and outside of the package is the shortest distance equal to the thickness of the peripheral wall. Therefore, in a small package, the thickness of the peripheral wall is naturally thin, so the sealing bath is also very short, which has the drawback of insufficient moisture resistance.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点に対し本発明では、限定された一定の厚さの
周壁をもつケースとその上に蓋をするキャップとの接合
部のシールバスをできるだけ長くするために、接合面を
斜めにするとか、または凹凸の組合せ面としている。
In order to solve the above problem, the present invention makes the joint surface oblique in order to make the sealing bath as long as possible at the joint between the case, which has a circumferential wall of a limited constant thickness, and the cap that covers the case. , or a combination of uneven surfaces.

〔実施例〕〔Example〕

つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.

第1図は本発明の一実施例のパッケージを用いて組立て
られた半導体装置の断面図である。第1図において、半
導体チップ7がマウントされているセラミック製のケー
ス10周壁土面部は、断面が凸字形に形成されている。
FIG. 1 is a sectional view of a semiconductor device assembled using a package according to an embodiment of the present invention. In FIG. 1, the surface of the peripheral wall of a ceramic case 10 on which a semiconductor chip 7 is mounted has a convex cross section.

樹脂シール剤6によりケース1と接合シールされている
ガラス製のキャップ2の周辺には、ケース周壁の凸部と
嵌合する凹みが設けられ、樹脂シール剤6.をはさんで
ケース1の周壁の凸部とキャップ2の周辺の凹みを嵌め
合せてシールされている。したがって、ケースの内側か
ら外側に通じるケースとキャップの接合部のシールバス
は、第3図に示す従来のものと比べ、凸部の垂直部の2
倍の長さだけ長くなり、それだけ湿気が通り難くなって
耐湿性が改善されている。
Around the glass cap 2 which is bonded and sealed to the case 1 by the resin sealant 6, a recess is provided that fits into a convex portion of the case peripheral wall. The protrusion on the peripheral wall of the case 1 and the recess around the cap 2 are fitted together to form a seal. Therefore, the seal bus at the joint between the case and the cap that communicates from the inside to the outside of the case is different from the conventional one shown in FIG.
It is twice as long, making it more difficult for moisture to pass through, improving moisture resistance.

第2図は本発明の他の実施例のパッケージによる半導体
装置の断面図である。図において、ケース3の周壁土面
の接合部の断面形状は、中央部が円孤状に盛上った形を
し、これに対しキャップ4の周辺にはこの円弧に合致す
る弧状の凹みが設けられ、樹脂シール剤をはさんで凸に
凹みが嵌め合わされてシールされているので、この場合
も従来の周壁厚さだけのシールバスに比べ長いシールバ
スとなっているので、長い分だけ耐湿性の向上が得られ
る。本例は第1図の例に比ベシールバスでは劣るが加工
が容易であるという長所がある。
FIG. 2 is a sectional view of a semiconductor device using a package according to another embodiment of the present invention. In the figure, the cross-sectional shape of the joint between the surrounding wall soil surface of the case 3 has a raised circular arc shape at the center, whereas the cap 4 has an arc-shaped recess that matches this circular arc around the cap 4. Since the convex and concave grooves are fitted together with a resin sealant in between and sealed, the seal bath is longer than the conventional seal bath with only the thickness of the peripheral wall, so the longer seal bath is moisture resistant. Improves sexual performance. Although this example is inferior to the example shown in FIG. 1 in terms of seal bath, it has the advantage of being easy to process.

なお、シールバスを長くする手段としては上側に限らず
、ケースの周壁を斜めに切った接合面とすることでも実
現できる。
Note that the means for lengthening the seal bath is not limited to the upper side, but can also be realized by using a joint surface cut diagonally from the peripheral wall of the case.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、樹脂シール剤によるパッ
ケージにおいて、シールバスを長<スることにより、パ
ッケージの耐湿性を向上させる効果がある。
As explained above, the present invention has the effect of improving the moisture resistance of a package using a resin sealant by extending the sealing bath.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のパッケージを用いて組立て
た半導体装置の断面図、第2図は本発明の他の実施例に
よる半導体装置の断面図、第3図は従来の半導体装置用
パッケージによる半導体装置の断面図である。 1.3,11・・・・・・セラミックケース、2,4゜
12・・・・・・ガラスキャップ、訃;−・外部リード
、6・・・・・・樹脂シール剤、7・・・・・・半導体
チップ、8・・・・;・ポンディングワイヤ。 代理人 弁理士  内 原   晋
FIG. 1 is a sectional view of a semiconductor device assembled using a package according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a sectional view of a conventional semiconductor device. FIG. 2 is a cross-sectional view of a semiconductor device in a package. 1.3,11...Ceramic case, 2,4゜12...Glass cap, -External lead, 6...Resin sealant, 7... ...Semiconductor chip, 8...;・Ponding wire. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims]  セラミックまたはガラス製のケースと、このケースの
上部開口に蓋をするキャップと、前記ケースとキャップ
との接合部をシールする樹脂シール剤とを含む半導体装
置用パッケージにおいて、前記接合部における内側と外
側との間のシールバスが水平直線距離より長くなるよう
に斜面または凹凸の組合せ面とされていることを特徴と
する半導体装置用パッケージ。
In a semiconductor device package that includes a case made of ceramic or glass, a cap that covers the upper opening of the case, and a resin sealant that seals the joint between the case and the cap, the inside and outside of the joint are 1. A package for a semiconductor device, characterized in that the surface has a slope or a combination of concave and convex surfaces so that the seal bus between the two surfaces is longer than the horizontal straight line distance.
JP62320332A 1987-12-17 1987-12-17 Package for semiconductor device Pending JPH01161736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62320332A JPH01161736A (en) 1987-12-17 1987-12-17 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62320332A JPH01161736A (en) 1987-12-17 1987-12-17 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPH01161736A true JPH01161736A (en) 1989-06-26

Family

ID=18120299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62320332A Pending JPH01161736A (en) 1987-12-17 1987-12-17 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPH01161736A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120366A (en) * 1992-10-06 1994-04-28 Sony Corp Semiconductor device
JPH06188325A (en) * 1992-12-17 1994-07-08 Kyocera Corp Package for semiconductor-element housing
JPH06196583A (en) * 1992-12-24 1994-07-15 Kyocera Corp Semiconductor device
US5889323A (en) * 1996-08-19 1999-03-30 Nec Corporation Semiconductor package and method of manufacturing the same
US6218730B1 (en) * 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
JP2002043450A (en) * 2001-06-15 2002-02-08 Sony Corp Semiconductor device
WO2003030275A1 (en) * 2001-09-28 2003-04-10 Osram Opto Semiconductors Gmbh Improved sealing for oled devices
US6856015B1 (en) * 2003-08-21 2005-02-15 Siliconware Precision Industries Co., Ltd. Semiconductor package with heat sink
JP5680226B2 (en) * 2012-07-27 2015-03-04 京セラ株式会社 Wiring board and package, and electronic device
JP2017120799A (en) * 2015-12-28 2017-07-06 株式会社Jvcケンウッド Package, manufacturing method of package, and image display device
CN108520866A (en) * 2018-04-27 2018-09-11 宁波江丰电子材料股份有限公司 Welding structure and semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120366A (en) * 1992-10-06 1994-04-28 Sony Corp Semiconductor device
JPH06188325A (en) * 1992-12-17 1994-07-08 Kyocera Corp Package for semiconductor-element housing
JPH06196583A (en) * 1992-12-24 1994-07-15 Kyocera Corp Semiconductor device
US5889323A (en) * 1996-08-19 1999-03-30 Nec Corporation Semiconductor package and method of manufacturing the same
US6218730B1 (en) * 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
JP2002043450A (en) * 2001-06-15 2002-02-08 Sony Corp Semiconductor device
WO2003030275A1 (en) * 2001-09-28 2003-04-10 Osram Opto Semiconductors Gmbh Improved sealing for oled devices
JP2005505141A (en) * 2001-09-28 2005-02-17 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Sealing member for OLED device
US6933537B2 (en) * 2001-09-28 2005-08-23 Osram Opto Semiconductors Gmbh Sealing for OLED devices
CN100407475C (en) * 2001-09-28 2008-07-30 奥斯兰姆奥普托半导体有限责任公司 Improved sealing for OLED devices
US6856015B1 (en) * 2003-08-21 2005-02-15 Siliconware Precision Industries Co., Ltd. Semiconductor package with heat sink
JP5680226B2 (en) * 2012-07-27 2015-03-04 京セラ株式会社 Wiring board and package, and electronic device
JP2017120799A (en) * 2015-12-28 2017-07-06 株式会社Jvcケンウッド Package, manufacturing method of package, and image display device
CN108520866A (en) * 2018-04-27 2018-09-11 宁波江丰电子材料股份有限公司 Welding structure and semiconductor device

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