JPH06120366A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06120366A JPH06120366A JP4292247A JP29224792A JPH06120366A JP H06120366 A JPH06120366 A JP H06120366A JP 4292247 A JP4292247 A JP 4292247A JP 29224792 A JP29224792 A JP 29224792A JP H06120366 A JPH06120366 A JP H06120366A
- Authority
- JP
- Japan
- Prior art keywords
- base
- moisture
- semiconductor device
- groove
- upper lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基台と上蓋との間に半
導体素子を収納して成る中空パッケージの半導体装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hollow package semiconductor device in which a semiconductor element is housed between a base and an upper lid.
【０００２】[0002]
【従来の技術】ＩＣ（集積回路）やＣＣＤ（Ｃｈａｒｇ
ｅ Ｃｏｕｐｌｅｄ Ｄｅｖｉｃｅ）等の半導体装置の
パッケージとして、セラミックスやプラスチック等を用
いた中空パッケージが用いられている。この中空パッケ
ージから成る半導体装置を図７の断面図に基づいて説明
する。すなわち、この半導体装置１は、略中央部に半導
体素子１０を搭載するためのセラミックスやプラスチッ
ク等から成る基台２と、この基台２上で半導体素子１０
を上方から包囲する状態で載置される上蓋３とから構成
されるもので、基台２と上蓋３との間に中空空間が設け
られ、この中空空間内に半導体素子１０が配置されてい
る。2. Description of the Related Art ICs (integrated circuits) and CCDs (Charges)
As a package of a semiconductor device such as e Coupled Device, a hollow package made of ceramics or plastic is used. A semiconductor device including the hollow package will be described with reference to the sectional view of FIG. That is, the semiconductor device 1 includes a base 2 made of ceramics, plastics or the like for mounting the semiconductor element 10 in a substantially central portion, and the semiconductor element 10 on the base 2.
The upper lid 3 is mounted so as to surround the upper lid 3. A hollow space is provided between the base 2 and the upper lid 3, and the semiconductor element 10 is arranged in the hollow space. .
【０００３】基台２と上蓋３との載置部分４には、樹脂
シーラーや紫外線照射硬化型接着剤等から成る封止剤４
１が塗布されており、基台２と上蓋３との間の中空空間
内に配置された半導体素子１０、および半導体素子１０
とリードフレーム７とを配線するボンディングワイヤー
８を密封状態にしている。On the mounting portion 4 between the base 2 and the upper lid 3, a sealant 4 made of a resin sealer, an ultraviolet irradiation curing adhesive or the like is used.
1 is applied and is arranged in the hollow space between the base 2 and the upper lid 3, and the semiconductor element 10
The bonding wire 8 that connects the lead frame 7 and the lead frame 7 is sealed.
【０００４】ＩＣ等から成る半導体装置１の場合には、
基台２および上蓋３ともにセラミックスまたはプラスチ
ック等が用いられ、ＣＣＤ等の光学系部品から成る半導
体装置１の場合には、セラミックスまたはプラスチック
等の基台２と、光の透過率の高い透明プラスチックやガ
ラス等の上蓋３が用いられている。In the case of the semiconductor device 1 including an IC or the like,
In the case of the semiconductor device 1 in which both the base 2 and the top cover 3 are made of ceramics or plastic, and the semiconductor device 1 is composed of an optical system component such as CCD, the base 2 made of ceramics or plastic and a transparent plastic having a high light transmittance are used. An upper lid 3 made of glass or the like is used.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな半導体装置には次のような問題がある。すなわち、
基台と上蓋との載置部分から湿気が侵入したり、載置部
分に塗布した封止剤が湿気を透過して中空空間内に入り
込み、基台や上蓋内面での結露発生につながる。特に、
ＣＣＤ等の光学系部品から成る半導体装置において、こ
のような結露が発生すると、光の透過率が低下して画像
等に悪影響を及ぼしてしまう。また、中空空間内に湿気
が侵入すると、配置された半導体素子等の誤動作の原因
となる。However, such a semiconductor device has the following problems. That is,
Moisture may enter from the mounting portion of the base and the upper lid, or the sealant applied to the mounting portion may permeate the moisture and enter the hollow space, leading to dew condensation on the inner surface of the base and the upper lid. In particular,
When such dew condensation occurs in a semiconductor device including an optical system component such as a CCD, the transmittance of light is reduced and the image or the like is adversely affected. Further, if moisture penetrates into the hollow space, it may cause malfunction of the semiconductor element or the like arranged therein.
【０００６】このため、特開昭５６−１４４５６１号に
示された如く、載置部分の形状を斜めやくさび型にして
湿気の侵入経路を長くしたり、湿気を透過しにくい封止
剤を用いたり、また封止剤の厚さを極力薄くしたりする
ことが考えられているが、いずれにおいてもこの程度で
は不十分である。さらに、中空空間内に水分吸湿剤を載
置することも考えられるが、この場合、吸湿能力が向上
する反面、水分吸湿剤からのダストの発生や、水分吸湿
剤を載置する場所の問題、作業性等の問題から現実的で
ない。よって、本発明は吸湿能力が高く、ダストの発生
がない半導体装置を提供することを目的とする。For this reason, as shown in Japanese Patent Laid-Open No. 56-144561, the mounting portion is formed into a slanted or wedge shape to lengthen the moisture invasion path or to use a sealing agent which does not easily transmit moisture. Alternatively, it has been considered to make the thickness of the sealant as thin as possible, but in any case, this level is insufficient. Further, it is also possible to place a moisture absorbent in the hollow space, in this case, while moisture absorption capacity is improved, the generation of dust from the moisture absorbent, the problem of the place to place the moisture absorbent, It is not realistic due to workability issues. Therefore, an object of the present invention is to provide a semiconductor device which has a high moisture absorption capacity and does not generate dust.
【０００７】[0007]
【課題を解決するための手段】本発明は、このような課
題を解決するために成された半導体装置である。すなわ
ち、この半導体装置は、基台の略中央に半導体素子を搭
載し、この基台上に上蓋を載置して半導体素子を上方か
ら包囲するもので、基台と上蓋との載置部分に吸湿用の
溝を備えた吸湿領域を設けるものである。また、この吸
湿用の溝内に水分吸湿剤を配置したり、この水分吸湿剤
を溝内において封止剤で覆うものでもある。The present invention is a semiconductor device made to solve the above problems. That is, this semiconductor device is one in which a semiconductor element is mounted in the approximate center of a base, and an upper lid is placed on the base to surround the semiconductor element from above. A moisture absorption region having a groove for moisture absorption is provided. Further, a moisture absorbent may be arranged in the moisture absorbing groove, or the moisture absorbent may be covered with a sealant in the groove.
【０００８】[0008]
【作用】基台と上蓋との載置部分に設けられた吸湿領域
により、外部から侵入する湿気をこの吸湿領域にて遮断
することになる。特に、吸湿領域に備えた溝で湿気を保
持することになるとともに、溝内に配置した水分吸湿剤
にて、この溝内に保持される湿気を吸収することにな
る。また、水分吸湿剤を封止剤にて覆うことで、吸湿領
域における吸湿能力がより向上するとともに、水分吸湿
剤から発生するダストが封止されて溝から中空空間内に
散乱しなくなる。With the moisture absorption region provided in the mounting portion of the base and the upper lid, moisture invading from the outside is blocked by this moisture absorption region. In particular, the moisture is held in the groove provided in the moisture absorption region, and the moisture held in the groove is absorbed by the moisture absorbent arranged in the groove. In addition, by covering the moisture absorbent with the sealant, the moisture absorption capacity in the moisture absorption region is further improved, and dust generated from the moisture absorbent is sealed and does not scatter from the groove into the hollow space.
【０００９】[0009]
【実施例】以下に、本発明の半導体装置の実施例を図に
基づいて説明する。図１は、本発明の半導体装置１を説
明する断面図である。すなわち、この半導体装置１は、
略中央に半導体素子１０を搭載するためにセラミックス
またはプラスチック等から形成された基台２と、この基
台２上で半導体素子１０を上方から包囲する状態に載置
された上蓋３とから構成されており、基台２と上蓋３と
の間に設けられる中空空間に半導体素子１０が配置され
るものである。Embodiments of the semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view illustrating a semiconductor device 1 of the present invention. That is, the semiconductor device 1 is
It is composed of a base 2 formed of ceramics or plastics for mounting the semiconductor element 10 at substantially the center thereof, and an upper lid 3 placed on the base 2 so as to surround the semiconductor element 10 from above. The semiconductor element 10 is arranged in a hollow space provided between the base 2 and the upper lid 3.
【００１０】基台２と上蓋３との載置部分４には、樹脂
シーラーや紫外線照射硬化型接着剤等から成る封止剤４
１が塗布されており、中空空間内を密封状態にしてい
る。すなわち、この中空空間内に配置された半導体素子
１０、およびこの半導体素子１０とリードフレーム７と
を配線するボンディングワイヤー８とがこの中空空間内
で封止状態となっている。On the mounting portion 4 between the base 2 and the upper lid 3, a sealant 4 made of a resin sealer, an ultraviolet irradiation curing adhesive or the like is used.
1 is applied, and the inside of the hollow space is sealed. That is, the semiconductor element 10 arranged in the hollow space and the bonding wire 8 for wiring the semiconductor element 10 and the lead frame 7 are sealed in the hollow space.
【００１１】さらに、この基台２と上蓋３との載置部分
４には、溝５を備えた吸湿領域Ｓが設けられている。例
えば、載置部分４の基台２側に溝５が設けられ、この上
に上蓋３が載置されている。また、必要に応じて上蓋３
に溝５と嵌合するような凸部を設けてもよい。このよう
に載置部分４に吸湿領域Ｓを設けることで、外部から中
空空間内に侵入しようとする湿気を保持することにな
り、中空空間内に配置された半導体素子１０を湿気から
保護することができる。Further, the mounting portion 4 of the base 2 and the upper lid 3 is provided with a moisture absorption region S having a groove 5. For example, the groove 5 is provided on the base 2 side of the mounting portion 4, and the upper lid 3 is mounted thereon. Also, if necessary, the upper lid 3
You may provide the convex part which fits in the groove | channel 5. By providing the moisture absorption region S in the mounting portion 4 in this way, moisture that tries to enter the hollow space from the outside is retained, and the semiconductor element 10 arranged in the hollow space is protected from moisture. You can
【００１２】また、この溝５内に水分吸湿剤６を配置し
てもよく、吸湿領域Ｓで保持した湿気をこの水分吸湿剤
６にて吸収することになる。水分吸湿剤６としては、ダ
ストの発生がなく成形性の良いシート状のものが望まし
く、溝５からはみ出ないような形状にして配置すればよ
い。さらに、溝５内に配置された水分吸湿剤６を封止剤
４１にて覆う状態にしてもよい。このようにすれば、水
分吸湿剤６を溝５内に確実に配置できるとともに、吸湿
領域Ｓにおける水分の吸湿をこの封止剤４１と水分吸湿
剤６との両方で行うことができるため吸湿能力が向上す
る。しかも、水分吸湿剤６から発生するダストが溝５内
に封止されて中空空間内に散乱しなくなる。Further, the moisture absorbent 6 may be disposed in the groove 5, and the moisture retained in the moisture absorption region S is absorbed by the moisture absorbent 6. As the moisture absorbent 6, a sheet-like material which does not generate dust and has good moldability is desirable, and the moisture absorbent 6 may be arranged so as not to protrude from the groove 5. Furthermore, the moisture absorbent 6 arranged in the groove 5 may be covered with the sealant 41. By doing so, the moisture absorbent 6 can be reliably arranged in the groove 5, and moisture in the moisture absorbing region S can be absorbed by both the sealant 41 and the moisture absorbent 6, so that the moisture absorbing ability is improved. Is improved. Moreover, the dust generated from the moisture absorbent 6 is sealed in the groove 5 and does not scatter in the hollow space.
【００１３】次に、本発明の半導体装置１の他の例を図
２〜図６の断面図に基づいて説明する。先ず、図２に示
す半導体装置１は、載置部分４に設けられた吸湿領域Ｓ
の溝５を中空として、この中に水分吸湿剤６を配置した
ものである。このため、載置部分４のうち基台２の上蓋
３との接触部分にのみ封止剤４１が塗布された状態とな
っている。外部からの湿気が載置部分４から侵入した場
合には、この湿気が中空の溝５内に溜まり、水分吸湿剤
６にて吸収されることになる。このような半導体装置１
では、吸湿効果を発揮しつつ封止剤４１を基台２と上蓋
３との接続に必要な量のみにすることができるため、特
に半導体装置１を大量生産する場合において大幅なコス
トダウンを図ることができる。Next, another example of the semiconductor device 1 of the present invention will be described with reference to the sectional views of FIGS. First, in the semiconductor device 1 shown in FIG. 2, the moisture absorption region S provided in the mounting portion 4 is
The groove 5 is made hollow, and the moisture absorbent 6 is placed therein. Therefore, the sealant 41 is applied only to the portion of the mounting portion 4 that is in contact with the upper lid 3 of the base 2. When moisture from the outside enters from the mounting portion 4, this moisture is accumulated in the hollow groove 5 and is absorbed by the moisture absorbent 6. Such a semiconductor device 1
Then, since the amount of the sealing agent 41 required for connecting the base 2 and the upper lid 3 can be exerted while exhibiting the moisture absorption effect, a significant cost reduction is achieved especially when the semiconductor devices 1 are mass-produced. be able to.
【００１４】また、図３に示す半導体装置１は、吸湿領
域Ｓの溝５が基台２側と上蓋３側に渡って設けられたも
のである。これにより、溝５の容積が増加して大きな水
分吸湿剤６を配置することができるため、吸湿能力が増
加することになる。また、さらに吸湿能力を増加させた
い場合には、この溝５内に封止剤４１を充填するように
すればよい。In the semiconductor device 1 shown in FIG. 3, the groove 5 of the moisture absorption region S is provided over the base 2 side and the upper lid 3 side. As a result, the volume of the groove 5 is increased and a large moisture absorbent 6 can be placed, so that the moisture absorption capacity is increased. If it is desired to further increase the moisture absorption capacity, the groove 5 may be filled with the sealant 41.
【００１５】次に、図４に示す半導体装置１は、吸湿領
域Ｓの溝５を上蓋３側に設け、この溝５内に水分吸湿剤
６を配置したものである。基台２の材質としてセラミッ
クス等の硬質材料を用いた場合には、基台２側に溝５を
形成するのが困難な場合があり、ＣＣＤ等の光学系部品
から成る半導体装置１では、上蓋３として透明プラスチ
ックを用いる場合があるため、溝５を上蓋３側に形成し
た方が容易である。この場合、予め封止剤４１にて水分
吸湿剤６を溝５内に埋め込んでおけば、基台２と上蓋３
との取り付けが行いやすくなる。Next, in the semiconductor device 1 shown in FIG. 4, the groove 5 of the moisture absorption region S is provided on the upper lid 3 side, and the moisture absorbent 6 is arranged in the groove 5. When a hard material such as ceramics is used as the material of the base 2, it may be difficult to form the groove 5 on the side of the base 2. Therefore, in the semiconductor device 1 including an optical system component such as a CCD, the upper lid is used. Since a transparent plastic may be used as the material 3, it is easier to form the groove 5 on the upper lid 3 side. In this case, if the moisture absorbent 6 is embedded in the groove 5 with the sealant 41 in advance, the base 2 and the upper lid 3
It becomes easy to install with.
【００１６】また、図５と図６に示す半導体装置１は、
他のパッケージ形状に適応したものである。図５に示す
半導体装置１は、リードフレーム７が基台２内に埋設さ
れて側面から導出したパッケージ形状であり、また図６
に示す半導体装置１は、リード７ａが基台２の下面から
下方に向けて導出したパッケージ形状である。いずれの
場合であっても、基台２と上蓋３との載置部分４に溝５
を備えた吸湿領域Ｓが設けられており、この溝５内に水
分吸湿剤６が配置されている。これらのパッケージ形状
の半導体装置１では、基台２の材質として主にプラスチ
ックが用いられており、基台２の形成時に使用する金型
内にリードフレーム７またはリード７ａを配置して一体
的に形成している。この際、金型に溝５と対応した形状
を設けておけば、基台２の形成と同時に溝５を形成する
ことができることになる。The semiconductor device 1 shown in FIG. 5 and FIG.
It is adapted to other package shapes. The semiconductor device 1 shown in FIG. 5 has a package shape in which the lead frame 7 is embedded in the base 2 and is led out from the side surface.
The semiconductor device 1 shown in (1) has a package shape in which the leads 7a are led out downward from the lower surface of the base 2. In any case, the groove 5 is formed in the mounting portion 4 of the base 2 and the upper lid 3.
Is provided, and the moisture absorbent 6 is arranged in the groove 5. In these package-shaped semiconductor devices 1, plastic is mainly used as the material of the base 2, and the lead frame 7 or the leads 7a are arranged in a mold used when the base 2 is formed to be integrated. Is forming. At this time, if the mold is provided with a shape corresponding to the groove 5, the groove 5 can be formed simultaneously with the formation of the base 2.
【００１７】なお、これらの実施例において、吸湿領域
Ｓを載置部分４の一部分に設けてもよいが、基台２と上
蓋３との間に設けられる中空空間を囲む状態に溝５を形
成して吸湿領域Ｓを設けるのが望ましく、吸湿能力を最
も高めることができる。また、本実施例では基台２と上
蓋３との接続を封止剤４１を用いて行ったが、本発明は
これに限定されず、例えば超音波溶着やレーザ溶接を用
いて接続してもよい。In these embodiments, the moisture absorption area S may be provided in a part of the mounting portion 4, but the groove 5 is formed so as to surround the hollow space provided between the base 2 and the upper lid 3. It is desirable to provide the moisture absorption region S to maximize the moisture absorption capacity. Further, in the present embodiment, the base 2 and the upper lid 3 were connected by using the sealant 41, but the present invention is not limited to this, and may be connected, for example, by ultrasonic welding or laser welding. Good.
【００１８】[0018]
【発明の効果】以上説明したように、本発明の半導体装
置によれば次のような効果がある。すなわち、基台と上
蓋との載置部分に吸湿領域が設けられているため、外部
から中空空間内に湿気が侵入しない。このため、湿気に
よる半導体素子の誤動作を低減できるとともに、湿気に
よる基台や上蓋内面への結露がないため、特にＣＣＤ等
の光学系部品から成る半導体装置においては、光の透過
率が低下することがなく、良好な画像を得ることができ
る。また、水分吸湿剤を溝内に配置することで、水分吸
湿剤から発生するダストが中空空間内に散乱しないた
め、半導体素子にダストが付着することがないととも
に、水分吸湿剤を用いた場合における半導体装置の組立
作業性が向上することになる。したがって、吸湿能力が
高く、しかもダストの発生がない半導体装置を容易に提
供することが可能となる。特に、基台と上蓋の材質とし
てプラスチックを使用して大量生産を図る半導体装置に
おいて本発明は有効なものとなる。As described above, the semiconductor device of the present invention has the following effects. That is, since the moisture absorption area is provided in the mounting portion of the base and the upper lid, moisture does not enter the hollow space from the outside. Therefore, malfunction of the semiconductor element due to moisture can be reduced, and since there is no dew condensation on the inner surface of the base or the upper lid due to moisture, the light transmittance is reduced particularly in a semiconductor device including an optical system component such as CCD. And a good image can be obtained. Further, by disposing the moisture absorbent in the groove, since the dust generated from the moisture absorbent does not scatter in the hollow space, the dust does not adhere to the semiconductor element, and in the case of using the moisture absorbent. Assembling workability of the semiconductor device is improved. Therefore, it is possible to easily provide a semiconductor device which has a high hygroscopic capacity and does not generate dust. In particular, the present invention is effective in a semiconductor device in which plastic is used as the material of the base and the upper lid for mass production.
【図１】本発明の半導体装置を説明する断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.
【図２】本発明の他の実施例を説明する断面図（その
１）である。FIG. 2 is a sectional view (No. 1) for explaining another embodiment of the present invention.
【図３】本発明の他の実施例を説明する断面図（その
２）である。FIG. 3 is a sectional view (No. 2) for explaining another embodiment of the present invention.
【図４】本発明の他の実施例を説明する断面図（その
３）である。FIG. 4 is a sectional view (No. 3) for explaining another embodiment of the present invention.
【図５】本発明の他の実施例を説明する断面図（その
４）である。FIG. 5 is a sectional view (No. 4) for explaining another embodiment of the present invention.
【図６】本発明の他の実施例を説明する断面図（その
５）である。FIG. 6 is a sectional view (5) for explaining another embodiment of the present invention.
【図７】半導体装置の従来例を説明する断面図である。FIG. 7 is a cross-sectional view illustrating a conventional example of a semiconductor device.
１ 半導体装置 ２ 基台 ３ 上蓋 ４ 載置部分 ５ 溝 ６ 水分吸湿剤 ７ リードフレーム ８ ボンディングワイヤー １０ 半導体素子 ４１ 封止剤 Ｓ 吸湿領域 1 Semiconductor Device 2 Base 3 Upper Lid 4 Mounting Part 5 Groove 6 Moisture Absorber 7 Lead Frame 8 Bonding Wire 10 Semiconductor Element 41 Sealant S Moisture Absorption Area
Claims (3)
と、 前記基台上で前記半導体素子を上方から包囲する状態で
載置される上蓋とから成る半導体装置において、 前記基台と前記上蓋との載置部分に吸湿用の溝を備えた
吸湿領域が設けられていることを特徴とする半導体装
置。1. A semiconductor device comprising a base on which a semiconductor element is mounted substantially in the center, and an upper lid mounted on the base in a state of surrounding the semiconductor element from above, wherein the base and the A semiconductor device, wherein a moisture absorption region having a groove for moisture absorption is provided in a mounting portion with the upper lid.
れていることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a moisture absorbent is arranged in the moisture absorbing groove.
剤が封止剤にて覆われていることを特徴とする請求項２
記載の半導体装置。3. The moisture absorbing agent arranged in the moisture absorbing groove is covered with a sealant.
The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29224792A JP3513168B2 (en) | 1992-10-06 | 1992-10-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29224792A JP3513168B2 (en) | 1992-10-06 | 1992-10-06 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001181257A Division JP2002043450A (en) | 2001-06-15 | 2001-06-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06120366A true JPH06120366A (en) | 1994-04-28 |
| JP3513168B2 JP3513168B2 (en) | 2004-03-31 |
Family
ID=17779357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29224792A Expired - Fee Related JP3513168B2 (en) | 1992-10-06 | 1992-10-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3513168B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5898571A (en) * | 1997-04-28 | 1999-04-27 | Lsi Logic Corporation | Apparatus and method for clip-on attachment of heat sinks to encapsulated semiconductor packages |
| US5977622A (en) * | 1997-04-25 | 1999-11-02 | Lsi Logic Corporation | Stiffener with slots for clip-on heat sink attachment |
| US6011304A (en) * | 1997-05-05 | 2000-01-04 | Lsi Logic Corporation | Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid |
| JP2008078668A (en) * | 2007-09-28 | 2008-04-03 | Kyocera Corp | Package for housing solid-state imaging sensor and imaging device |
| JP2009290023A (en) * | 2008-05-29 | 2009-12-10 | Sumitomo Bakelite Co Ltd | Semiconductor device |
| WO2015079811A1 (en) * | 2013-11-29 | 2015-06-04 | 株式会社日立エルジーデータストレージ | Seal structure for video-image output device |
| CN107408536A (en) * | 2015-03-11 | 2017-11-28 | 田中贵金属工业株式会社 | Electronic component sealing cap |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161736A (en) * | 1987-12-17 | 1989-06-26 | Nec Corp | Package for semiconductor device |
| JPH0485859A (en) * | 1990-07-26 | 1992-03-18 | Mitsui Petrochem Ind Ltd | Airtightly sealed package and bonding member |
-
1992
- 1992-10-06 JP JP29224792A patent/JP3513168B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01161736A (en) * | 1987-12-17 | 1989-06-26 | Nec Corp | Package for semiconductor device |
| JPH0485859A (en) * | 1990-07-26 | 1992-03-18 | Mitsui Petrochem Ind Ltd | Airtightly sealed package and bonding member |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977622A (en) * | 1997-04-25 | 1999-11-02 | Lsi Logic Corporation | Stiffener with slots for clip-on heat sink attachment |
| US5898571A (en) * | 1997-04-28 | 1999-04-27 | Lsi Logic Corporation | Apparatus and method for clip-on attachment of heat sinks to encapsulated semiconductor packages |
| US6011304A (en) * | 1997-05-05 | 2000-01-04 | Lsi Logic Corporation | Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid |
| JP2008078668A (en) * | 2007-09-28 | 2008-04-03 | Kyocera Corp | Package for housing solid-state imaging sensor and imaging device |
| JP4646960B2 (en) * | 2007-09-28 | 2011-03-09 | 京セラ株式会社 | Package for storing solid-state imaging device and imaging apparatus |
| JP2009290023A (en) * | 2008-05-29 | 2009-12-10 | Sumitomo Bakelite Co Ltd | Semiconductor device |
| WO2015079811A1 (en) * | 2013-11-29 | 2015-06-04 | 株式会社日立エルジーデータストレージ | Seal structure for video-image output device |
| CN107408536A (en) * | 2015-03-11 | 2017-11-28 | 田中贵金属工业株式会社 | Electronic component sealing cap |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3513168B2 (en) | 2004-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100565891C (en) | Semiconductor device and manufacture method thereof | |
| KR960009089B1 (en) | Mold for package molding and plastic charge-coupled device and the manufacturing method using the mold | |
| KR100608523B1 (en) | A semiconductor optical sensing apparatus | |
| KR940022807A (en) | Semiconductor device and mold for semiconductor device | |
| US20050285265A1 (en) | Frame scale package using contact lines through the elements | |
| KR920003484A (en) | Semiconductor device and manufacturing method thereof | |
| CA2196268A1 (en) | Package | |
| JPH1197656A (en) | Semiconductor photosensor device | |
| JP3513168B2 (en) | Semiconductor device | |
| US6940140B1 (en) | Package structure of solid-state image sensor | |
| JP3407218B2 (en) | Semiconductor optical sensor device | |
| JP2006344902A (en) | Semiconductor module | |
| US7592197B2 (en) | Image sensor chip package fabrication method | |
| JPH0728014B2 (en) | Solid-state imaging device | |
| JP2002043450A (en) | Semiconductor device | |
| JP2878875B2 (en) | CCD module | |
| JPS60113950A (en) | Semiconductor device | |
| JPH0726844Y2 (en) | Hybrid integrated circuit | |
| JP4466203B2 (en) | Solid-state image sensor storage package | |
| KR960002343Y1 (en) | Semiconductor package | |
| JPS6222551B2 (en) | ||
| KR950006440Y1 (en) | Package glasslid structure of pccd | |
| JP2687707B2 (en) | Light receiving semiconductor device and assembling method thereof | |
| JPS5869174A (en) | Solid-state image pickup device | |
| KR200265306Y1 (en) | Multichip Package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040109 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080116 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090116 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100116 Year of fee payment: 6 |
|
| LAPS | Cancellation because of no payment of annual fees |