JPH03238848A - Semiconductor device sealing container - Google Patents
Semiconductor device sealing containerInfo
- Publication number
- JPH03238848A JPH03238848A JP2035427A JP3542790A JPH03238848A JP H03238848 A JPH03238848 A JP H03238848A JP 2035427 A JP2035427 A JP 2035427A JP 3542790 A JP3542790 A JP 3542790A JP H03238848 A JPH03238848 A JP H03238848A
- Authority
- JP
- Japan
- Prior art keywords
- sealing member
- bonding
- cap
- semiconductor device
- lower ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007789 sealing Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000919 ceramic Substances 0.000 claims abstract description 17
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 238000010008 shearing Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000005394 sealing glass Substances 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は半導体装置封止用容器に関し、特に、セラミッ
ク封止容器に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a container for sealing a semiconductor device, and particularly to a ceramic sealing container.
【従来の技術Ｊ
従来、この種の半導体装置封止用容器は、第３図に示す
ように１例えば、板状の下部セラミック封止部材ｌとキ
ャップ状上部封止部材２よりなり、半導体チップ３は下
部セラミック封止部材ｌの上面中央部に載置され、それ
ぞれの電極はボンディング線４および内一部電極メタラ
イズ層５とを介し外部リード端子６と接続される。ここ
で、７は内部電極メタライズ層５と外部リード端子６と
を封止部材ｌの側面で接続するリード・ロー付は材、ま
た、８は環状のアルミナ絶縁層９を挟んで下部セラミッ
ク封止部材１とキャップ状上部封止部材２とを接着する
封止ガラス材をそれぞれ示す。[Prior Art J] Conventionally, as shown in FIG. 3, this type of semiconductor device sealing container is made up of, for example, a plate-shaped lower ceramic sealing member L and a cap-shaped upper sealing member 2. 3 is placed at the center of the upper surface of the lower ceramic sealing member l, and each electrode is connected to an external lead terminal 6 via a bonding wire 4 and an inner partial electrode metallized layer 5. Here, 7 is a lead brazing material that connects the internal electrode metallized layer 5 and the external lead terminal 6 on the side surface of the sealing member l, and 8 is a material for lower ceramic sealing with an annular alumina insulating layer 9 in between. The sealing glass material for bonding the member 1 and the cap-shaped upper sealing member 2 is shown, respectively.
【発明が解決しようとする課題ｌ
しかしながら、上述した従来の半導体装置封止用容器は
、下部封止部材ｌと上部封止部材２の接着面が下部封止
部材ｌの上面と同一水平面上にあるため、接着面に位置
ずれを起し易い。Problem to be Solved by the Invention 1 However, in the conventional semiconductor device sealing container described above, the bonding surfaces of the lower sealing member 1 and the upper sealing member 2 are on the same horizontal plane as the upper surface of the lower sealing member 1. Therefore, it is easy to cause misalignment on the adhesive surface.
また、図示のように、せん断心力Ｆが水平方向に加わっ
たときのせん断強度も低いという欠点がある。Further, as shown in the figure, there is a drawback that the shear strength is low when the shear core force F is applied in the horizontal direction.
本発明の目的は、上記の情況に鑑み、板状の下部セラミ
ック封止部材とキャップ状上部封止部材との接着面に生
じ易い位置ずれおよびせん断強度不足の従来欠点を解決
した半導体装置封止用容器を提供することである。In view of the above-mentioned circumstances, an object of the present invention is to provide a semiconductor device encapsulation solution that solves the conventional drawbacks of misalignment and insufficient shear strength that tend to occur at the bonding surface between a plate-shaped lower ceramic encapsulation member and a cap-shaped upper encapsulation member. The aim is to provide containers for
〔課題を解決するための手段１
本発明によれば、半導体チップを載置する板状の下部セ
ラミック封止部材と該下部セラミック封止部材上で前記
半導体チップを気密封止するキャップ状上部封止部材と
から成り、前記板状の下部セラミック封止部材とキャッ
プ状上部封止部材との接着面が傾斜面で形成されること
を含んで構成される。[Means for Solving the Problems 1] According to the present invention, there is provided a plate-shaped lower ceramic sealing member on which a semiconductor chip is placed, and a cap-shaped upper sealing member that hermetically seals the semiconductor chip on the lower ceramic sealing member. The bonding surface between the plate-shaped lower ceramic sealing member and the cap-shaped upper sealing member is formed as an inclined surface.
本発明によれば、上下の各封止部材は、傾斜面で接着さ
れているので、従来問題とされた接着面の位置ずれおよ
び水平応力に対する弱さが何れも解決される。According to the present invention, since the upper and lower sealing members are bonded at the inclined surfaces, the conventional problems of misalignment of the bonding surfaces and weakness against horizontal stress are solved.
［実施例］ 次に図面を参照して本発明の詳細な説明する。[Example] Next, the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例を示す半導体装置封止用容器
の断面構造図である。本実施例は本発明を超高周波用Ｇ
ａＡｓ電界効果トランジスタに実施した場合を第３図と
共通符号を用いて示したもので、半導体チップ３は、接
着面を外部に向けて約３０°の傾斜面をもつように形成
した板状の下部セラミック封止部材ｌとキャップ状の上
部封止部材２内に封着される。すなわち、下部のセラミ
ック封止部材１の周縁部は約３０°の傾斜面をもつよう
に削除され、また、上部のキャップ状封止部材２の封着
端面もこれに対応する角度に切除され、それぞれ研磨仕
上される。FIG. 1 is a cross-sectional structural diagram of a container for sealing a semiconductor device showing an embodiment of the present invention. This example demonstrates how the present invention can be applied to ultra-high frequency G
The case where the semiconductor chip 3 is applied to an aAs field effect transistor is shown using the same reference numerals as in FIG. It is sealed within a lower ceramic sealing member 1 and a cap-shaped upper sealing member 2. That is, the peripheral edge of the lower ceramic sealing member 1 is removed to have an inclined surface of approximately 30°, and the sealing end surface of the upper cap-shaped sealing member 2 is also cut at an angle corresponding to this. Each has a polished finish.
接着面がこのような傾斜をもつと、上部のキャップ状封
止部材２の下部封止部材ｌに対する位置が必然的に決ま
るのでその横滑りは抑制される。また、上部のキャップ
状封止部材２に対する水平せん断心力方向と接着面とは
互いに交差するため、接続面に加わるせん断応力は実質
的に小さくなり、更に接着面積も従来より広くなってい
るため、せん断強度は格段に向上する。When the adhesive surface has such an inclination, the position of the upper cap-shaped sealing member 2 with respect to the lower sealing member l is inevitably determined, so that sideways sliding thereof is suppressed. In addition, since the direction of the horizontal shear center force on the upper cap-shaped sealing member 2 and the bonding surface intersect with each other, the shear stress applied to the connection surface is substantially reduced, and the bonding area is also larger than before. Shear strength is significantly improved.
第２図は本発明の他の実施例を示す半導体装置封止用容
器の断面構造図である０本実施例は上下の各封止部材１
ｉ３よび２の接着面が４５°の傾斜面をもつ場合で、前
実施例と同様な効果をあげ得ることを示す。FIG. 2 is a cross-sectional structural diagram of a container for sealing a semiconductor device showing another embodiment of the present invention.
It is shown that the same effect as in the previous example can be achieved in the case where the bonding surfaces of i3 and 2 have an inclined surface of 45°.
〔発明の効果Ｊ
以上詳細に説明したように、本発明によれば、上下の各
封止部材を傾斜させて接着することにより、接着位置を
確定し、また、接着面積を増やし、かつ、接着面に対す
るせん断応力の方向をかわすことができるので、接着強
度の極めて強固な半導体装置封止用容器を得ることが可
能である。[Effects of the Invention J As described in detail above, according to the present invention, by bonding the upper and lower sealing members at an angle, the bonding position can be determined, the bonding area can be increased, and the bonding Since the direction of shear stress on the surface can be avoided, it is possible to obtain a semiconductor device sealing container with extremely strong adhesive strength.
第１図は本発明の一実施例を示す半導体装置封止用容器
の断面構造図、第２図は本発明の他の実施例を示す半導
体装置封止用容器の断面構造図、第３図は従来の半導体
装置封止用容器の断面構造図である。
１・・・板状下部セラミック封止部材、２・・・キャッ
プ状上部封止部材、
３・・・半導体チップ、
４−・ボンディング線、
５・−・内部電極メタライズ層、
６・−外部リード端子、
７・・−リード・ロー付は材、
８−・・封止ガラス、
９・・・アルミナ絶縁層。FIG. 1 is a cross-sectional structural diagram of a semiconductor device sealing container showing one embodiment of the present invention, FIG. 2 is a cross-sectional structural diagram of a semiconductor device sealing container showing another embodiment of the present invention, and FIG. 1 is a cross-sectional structural diagram of a conventional container for sealing a semiconductor device. DESCRIPTION OF SYMBOLS 1... Plate-shaped lower ceramic sealing member, 2... Cap-shaped upper sealing member, 3... Semiconductor chip, 4-- Bonding wire, 5-- Internal electrode metallized layer, 6-- External lead Terminal, 7... - Material with lead and solder, 8 - Sealing glass, 9... Alumina insulating layer.
Claims (1)
と該下部セラミック封止部材上で前記半導体チップを気
密封止するキャップ状上部封止部材とから成り、前記板
状の下部セラミック封止部材とキャップ状上部封止部材
との接着面が傾斜面で形成されることを特徴とする半導
体装置封止用容器。The plate-shaped lower ceramic sealing member is composed of a plate-shaped lower ceramic sealing member on which a semiconductor chip is placed, and a cap-shaped upper sealing member that hermetically seals the semiconductor chip on the lower ceramic sealing member. 1. A container for sealing a semiconductor device, wherein an adhesive surface between the cap-shaped upper sealing member and the cap-shaped upper sealing member is formed as an inclined surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2035427A JPH03238848A (en) | 1990-02-15 | 1990-02-15 | Semiconductor device sealing container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2035427A JPH03238848A (en) | 1990-02-15 | 1990-02-15 | Semiconductor device sealing container |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03238848A true JPH03238848A (en) | 1991-10-24 |
Family
ID=12441566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2035427A Pending JPH03238848A (en) | 1990-02-15 | 1990-02-15 | Semiconductor device sealing container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03238848A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008160020A (en) * | 2006-12-26 | 2008-07-10 | Toyota Motor Corp | Reactor core and reactor |
-
1990
- 1990-02-15 JP JP2035427A patent/JPH03238848A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008160020A (en) * | 2006-12-26 | 2008-07-10 | Toyota Motor Corp | Reactor core and reactor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20200382096A1 (en) | Piezoelectric resonator device | |
| JPH03238848A (en) | Semiconductor device sealing container | |
| JPH01161736A (en) | Package for semiconductor device | |
| JPS62142341A (en) | Semiconductor device and manufacture thereof | |
| CN102006030B (en) | Reinforced-airtightness oscillator device wafer-grade packaging structure | |
| JPS5992552A (en) | Semiconductor device | |
| JPH03212965A (en) | Lead frame | |
| JPS6079749A (en) | Semiconductor device | |
| JPS614251A (en) | Semiconductor package | |
| JPH03120849A (en) | Semiconductor device | |
| JPS6218737A (en) | Ceramic package for semiconductor device | |
| JPS6334275Y2 (en) | ||
| JPS63248155A (en) | Semiconductor device | |
| JPS61150352A (en) | Semiconductor device | |
| JPH05299469A (en) | Semiconductor device and manufacture thereof | |
| JPH03148157A (en) | Glass-sealed ceramic package | |
| KR100345163B1 (en) | Ball grid array package | |
| JPH01123442A (en) | Ceramic package for semiconductor device | |
| JPH02205053A (en) | Semiconductor device | |
| KR200331874Y1 (en) | Multi-pin Package of Semiconductor | |
| JPH04188657A (en) | Semiconductor device package | |
| JPS60171745A (en) | Semiconductor device | |
| JPS60200542A (en) | Semiconductor device | |
| JPS62293742A (en) | Semiconductor element container | |
| JPS6223142A (en) | Lead frame |