JPH02109410A - Resin seal type semiconductor device - Google Patents
Resin seal type semiconductor deviceInfo
- Publication number
- JPH02109410A JPH02109410A JP26231588A JP26231588A JPH02109410A JP H02109410 A JPH02109410 A JP H02109410A JP 26231588 A JP26231588 A JP 26231588A JP 26231588 A JP26231588 A JP 26231588A JP H02109410 A JPH02109410 A JP H02109410A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bonding
- semiconductor chips
- chips
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000011347 resin Substances 0.000 title claims abstract description 11
- 229920005989 resin Polymers 0.000 title claims abstract description 11
- 239000011796 hollow space material Substances 0.000 claims abstract description 6
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 239000000565 sealant Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- -1 AΩ or solder Chemical class 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体チップを樹脂封止する樹脂封止型半導
体装置の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an improvement in a resin-sealed semiconductor device in which a semiconductor chip is sealed with a resin.
［発明の概要］ 本発明は、樹脂封止型パッケージ構造において。[Summary of the invention] The present invention relates to a resin-sealed package structure.
２つのチップのうち、そのいずれか一方に凹部を形成し
、両チップを接合したとき、前記凹部によす、チップの
素子領域を中空状空間に表出させ得る中空部分を形成す
るようにしたものである。A recess is formed in one of the two chips, and when the two chips are bonded together, a hollow portion is formed in the recess that allows the element region of the chip to be exposed in the hollow space. It is something.
［従来の技術］
従来１表面弾性波素子のように、パッケージ内に中空部
分を設ける必要がある場合、セラミックパッケージある
いは金属パッケージを用いた気密封止構造のものが多用
されている。第６図はその代表的な気密封止構造を示し
たものであって、１はセラミックベース、２は半導体チ
ップ、３はボンディングワイヤ、４はリッド、５は外部
リードである。[Prior Art] When it is necessary to provide a hollow portion in a package, as in the conventional surface acoustic wave device, a hermetically sealed structure using a ceramic package or a metal package is often used. FIG. 6 shows a typical hermetic sealing structure, in which 1 is a ceramic base, 2 is a semiconductor chip, 3 is a bonding wire, 4 is a lid, and 5 is an external lead.
［発明が解決しようとする課題］
しかし、上記気密封止パッケージ構造は、樹脂封止型パ
ッケージに比べて著しくコストが高く。[Problems to be Solved by the Invention] However, the hermetically sealed package structure is significantly more expensive than the resin-sealed package.
経済性および生産性に劣っており、それが生産効率を高
めるうえでの妨げの一つとなっている。It is inferior in economic efficiency and productivity, which is one of the obstacles to increasing production efficiency.
［発明の目的］
本発明は、パッケージ内に中空部を設け、かつ樹脂封止
のできる半導体装置を提供することを主たる目的として
いるものである。[Object of the Invention] The main object of the present invention is to provide a semiconductor device in which a hollow portion is provided in a package and which can be sealed with resin.
［課題を解決するための手段］
本発明は、上記目的を達成するため、少なくとも一方に
素子領域が形成された２つの半導体チップと、そのいず
れかの半導体チップに形成された凹部を中空状とすると
共にその中空状空間に前記素子領域を表出するように両
生導体チップを接合する手段と、接合された両生導体チ
ップを封止する樹脂封止材とで構成することにより、上
述した問題点の解決を図ったものである。[Means for Solving the Problems] In order to achieve the above object, the present invention includes two semiconductor chips in which an element region is formed on at least one of the chips, and a recess formed in one of the semiconductor chips in a hollow shape. At the same time, the above-mentioned problems can be solved by comprising means for joining the amphiphilic conductor chips so as to expose the element area in the hollow space, and a resin sealing material for sealing the joined amphiphilic conductor chips. This is an attempt to solve the problem.
［作用］
上記構成の樹脂封止型半導体装置においては、２つの半
導体チップを接合することにより、その一方に設けられ
た凹部により、素子領域を表出する中空部分が形成され
るので、それを樹脂で封止すれば、中空部分を有する樹
脂封止型パラケラジー構造が得られる。[Function] In the resin-sealed semiconductor device having the above configuration, by bonding two semiconductor chips together, a hollow portion exposing the element region is formed by a recess provided in one of the chips. If it is sealed with a resin, a resin-sealed parachelasic structure having a hollow portion can be obtained.
［実施例］
第１図乃至第５図は、本発明の一実施例を示すものであ
る。[Embodiment] FIGS. 1 to 5 show an embodiment of the present invention.
同図において、Ａ、Ｂは接合される半導体チップである
。一方の半導体チップＡは、第２図および第３図に示す
ように、その接合面にチップ接合用リング６およびワイ
ヤボンディング用パッド７が設けられている。前記チッ
プ接合用リング６は、ウェーハプロセス中に蒸着あるい
はメツキ等の手段により形成される。リングの材料とし
ては例えばＡｕが好ましいが、それに限らず、ＡΩ、ハ
ンダなど、容易に金属接合できるものであればよく、ま
た耐熱性、耐湿性に優れた樹脂接着材でもよい。In the figure, A and B are semiconductor chips to be bonded. As shown in FIGS. 2 and 3, one semiconductor chip A is provided with a chip bonding ring 6 and a wire bonding pad 7 on its bonding surface. The chip bonding ring 6 is formed by means such as vapor deposition or plating during the wafer process. The material for the ring is preferably, for example, Au, but is not limited thereto, and may be any material that can be easily joined to metals, such as AΩ or solder, or may be a resin adhesive with excellent heat resistance and moisture resistance.
ワイヤボンディング用パッドは、アンダーパスあるいは
二層配線手段により、リング内部の素子領域部８と接続
されている。The wire bonding pad is connected to the element region 8 inside the ring by an underpass or a two-layer wiring means.
他方の半導体チップＢは、第４図および第５図に示すよ
うに、前記半導体チップＡと同様なチップ接合用リング
９が形成され、リング内部の素子領域１０はエツチング
により、必要な深さの凹部１１に形成されている。なお
、予め必要な凹部が確保されているものであれば、エツ
チングは不要である。As shown in FIGS. 4 and 5, the other semiconductor chip B has a chip bonding ring 9 similar to that of the semiconductor chip A, and the element region 10 inside the ring is etched to a required depth. It is formed in the recess 11. Note that if the necessary recesses are secured in advance, etching is not necessary.
上記構成の半導体チップＡ、Ｂは、アセンブリ工程中に
おいて、各チップに形成された接合用リング６．９を介
して超音波熱圧着等の適当な手段により接合されたとき
、チップＢの凹部１ｏにより、素子領域を中空状空間に
表出する中空部１２が形成される。During the assembly process, when the semiconductor chips A and B having the above configuration are joined by an appropriate means such as ultrasonic thermocompression bonding via the joining ring 6.9 formed on each chip, the recess 1o of the chip B is As a result, a hollow portion 12 is formed that exposes the element region into a hollow space.
前記半導体チップＡ、Ｂの接合後、チップＡのポンディ
ングパッド７が外部リード１３を有するリードフレーム
１４にボンディングワイヤ１５によって接続され、リー
ドフレームの外部リードを除き、ダイステージ１６に搭
載された半導体チップＡ、Ｂとワイヤボンディング領域
が樹脂封止材１７により封止されている。半導体チップ
Ａ、 Ｂの素子領域の接続は、周知の手段であるバンプ
電極等を用いて行うことができる。After the semiconductor chips A and B are bonded, the bonding pad 7 of the chip A is connected to the lead frame 14 having the external leads 13 by the bonding wire 15, and the semiconductor mounted on the die stage 16, excluding the external leads of the lead frame, is connected to the bonding pad 7 of the chip A. Chips A and B and the wire bonding area are sealed with a resin sealant 17. The element regions of semiconductor chips A and B can be connected using well-known means such as bump electrodes.
［発明の効果］
以上に述べたように、本発明によれば、２つの半導体チ
ップを接合し、それを樹脂封止する構成としているので
、パッケージ内に中空部を有する樹脂封止型半導体装置
が容易に得ることができ。[Effects of the Invention] As described above, according to the present invention, two semiconductor chips are bonded and then resin-sealed, so that a resin-sealed semiconductor device having a hollow portion in the package can be manufactured. can be easily obtained.
かつ従来のセラミックおよび金属パッケージによる気密
封止構造に比べ使用部品の材料費の大幅な節減を図るこ
とができる。Furthermore, compared to conventional hermetically sealed structures using ceramic and metal packages, material costs for the parts used can be significantly reduced.
また、本発明によれば、チップを複数個搭載できるので
、その実装密度を著しく向上させることもできる。Further, according to the present invention, since a plurality of chips can be mounted, the packaging density can be significantly improved.
第１図は本発明の一実施例を示す樹脂封止型半導体装置
の縦断面図、第２図は接合される一方の半導体チップの
斜視図、第３図はその切断面図。
第４図は他方の半導体チップの斜視図、第５図はその切
断面図、第６図は従来のパッケージ封止型半導体装置の
縦断面図である。
Ａ、Ｂ・・・・・・・・・半導体チップ、 ６，９・・
・・・・・・・接合用リング、７・・・・・・・・・ポ
ンディングパッド、８゜１０・・・・・・・・・素子領
域、１１・・・・・・・・・凹部、１２・・・・・・・
・・中空部、１３・・・・・・・・・外部リード、１４
・・・・・・・・・リードフレーム、１５・・・・・・
・・・ボンディングワイヤ、１６・・・・・・・・・ダ
イステージ、１７・・・・・・・・・樹脂封止材。FIG. 1 is a longitudinal sectional view of a resin-sealed semiconductor device showing an embodiment of the present invention, FIG. 2 is a perspective view of one of the semiconductor chips to be bonded, and FIG. 3 is a sectional view thereof. FIG. 4 is a perspective view of the other semiconductor chip, FIG. 5 is a sectional view thereof, and FIG. 6 is a vertical sectional view of a conventional packaged semiconductor device. A, B... Semiconductor chip, 6,9...
......Bonding ring, 7...Ponding pad, 8゜10...Element area, 11... Recessed portion, 12...
...Hollow part, 13...External lead, 14
......Lead frame, 15...
. . . Bonding wire, 16 . . . Die stage, 17 . . . Resin sealing material.
Claims (1)
ップと、そのいずれかの半導体チップに形成された凹部
を中空状とすると共にその中空状空間に前記素子領域を
表出するように両半導体チップを接合する手段と、接合
された両半導体チップを封止する樹脂封止材とで構成さ
れていることを特徴とする樹脂封止型半導体装置。Two semiconductor chips each having an element region formed on at least one of the semiconductor chips, a recess formed in one of the semiconductor chips being hollow, and both semiconductor chips being arranged so that the element region is exposed in the hollow space. A resin-sealed semiconductor device comprising a means for bonding and a resin sealant for sealing both bonded semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26231588A JPH02109410A (en) | 1988-10-18 | 1988-10-18 | Resin seal type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26231588A JPH02109410A (en) | 1988-10-18 | 1988-10-18 | Resin seal type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02109410A true JPH02109410A (en) | 1990-04-23 |
Family
ID=17374070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26231588A Pending JPH02109410A (en) | 1988-10-18 | 1988-10-18 | Resin seal type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02109410A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09213840A (en) * | 1996-01-31 | 1997-08-15 | Nec Corp | Resin-sealed type semiconductor device |
| WO2003061006A3 (en) * | 2002-01-09 | 2004-06-17 | Micron Technology Inc | Stacked die in die bga package |
-
1988
- 1988-10-18 JP JP26231588A patent/JPH02109410A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09213840A (en) * | 1996-01-31 | 1997-08-15 | Nec Corp | Resin-sealed type semiconductor device |
| WO2003061006A3 (en) * | 2002-01-09 | 2004-06-17 | Micron Technology Inc | Stacked die in die bga package |
| US7282392B2 (en) | 2002-01-09 | 2007-10-16 | Micron Technology, Inc. | Method of fabricating a stacked die in die BGA package |
| US7282390B2 (en) | 2002-01-09 | 2007-10-16 | Micron Technology, Inc. | Stacked die-in-die BGA package with die having a recess |
| US7309623B2 (en) | 2002-01-09 | 2007-12-18 | Micron Technology, Inc. | Method of fabricating a stacked die in die BGA package |
| US7332819B2 (en) | 2002-01-09 | 2008-02-19 | Micron Technology, Inc. | Stacked die in die BGA package |
| US7332820B2 (en) | 2002-01-09 | 2008-02-19 | Micron Technology, Inc. | Stacked die in die BGA package |
| US7344969B2 (en) | 2002-01-09 | 2008-03-18 | Micron Technology, Inc. | Stacked die in die BGA package |
| US7358117B2 (en) | 2002-01-09 | 2008-04-15 | Micron Technology, Inc. | Stacked die in die BGA package |
| US7371608B2 (en) | 2002-01-09 | 2008-05-13 | Micron Technology, Inc. | Method of fabricating a stacked die having a recess in a die BGA package |
| US7575953B2 (en) | 2002-01-09 | 2009-08-18 | Micron Technology, Inc. | Stacked die with a recess in a die BGA package |
| US7799610B2 (en) | 2002-01-09 | 2010-09-21 | Micron Technology, Inc. | Method of fabricating a stacked die having a recess in a die BGA package |
| US8373277B2 (en) | 2002-01-09 | 2013-02-12 | Micron Technology, Inc. | Stacked die in die BGA package |
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