JPH0115102B2 - - Google Patents
Info
- Publication number
- JPH0115102B2 JPH0115102B2 JP58246673A JP24667383A JPH0115102B2 JP H0115102 B2 JPH0115102 B2 JP H0115102B2 JP 58246673 A JP58246673 A JP 58246673A JP 24667383 A JP24667383 A JP 24667383A JP H0115102 B2 JPH0115102 B2 JP H0115102B2
- Authority
- JP
- Japan
- Prior art keywords
- service processor
- processing unit
- input
- central processing
- channel device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24667383A JPS60142764A (ja) | 1983-12-29 | 1983-12-29 | 計算機インタフエ−ス方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24667383A JPS60142764A (ja) | 1983-12-29 | 1983-12-29 | 計算機インタフエ−ス方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60142764A JPS60142764A (ja) | 1985-07-27 |
| JPH0115102B2 true JPH0115102B2 (enExample) | 1989-03-15 |
Family
ID=17151909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24667383A Granted JPS60142764A (ja) | 1983-12-29 | 1983-12-29 | 計算機インタフエ−ス方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60142764A (enExample) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583246B2 (ja) * | 1978-08-09 | 1983-01-20 | 富士通株式会社 | デ−タ処理システム |
| JPS6024495B2 (ja) * | 1980-12-26 | 1985-06-13 | 富士通株式会社 | インタフェ−ス制御方式 |
| JPS57111763A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Device connecting system of multi-system |
-
1983
- 1983-12-29 JP JP24667383A patent/JPS60142764A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60142764A (ja) | 1985-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4112490A (en) | Data transfer control apparatus and method | |
| IL134870A (en) | Data transfer system for use in an information processing system | |
| EP0862116A3 (en) | A smart debug interface circuit | |
| US5341495A (en) | Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols | |
| JPH0115102B2 (enExample) | ||
| JPH07295947A (ja) | データ転送管理装置及び方法 | |
| US5056007A (en) | Cross-coupling of service processor driven system control facilities in a multiple service processor data processing system | |
| US6085271A (en) | System bus arbitrator for facilitating multiple transactions in a computer system | |
| US5974477A (en) | Image forming apparatus capable of receiving data in high speed in accordance with high speed data transmission interface | |
| JPH0348544B2 (enExample) | ||
| JPS6347864A (ja) | メモリ間のデ−タ転送方法 | |
| JPS6162158A (ja) | デ−タ授受システム | |
| JPS58163055A (ja) | デ−タ処理システム | |
| KR930011348B1 (ko) | 데코더 ic와 scsi ic간의 인터페이스 회로 | |
| JPS62180443A (ja) | 計算機システムの初期設定方式 | |
| JPS62192824A (ja) | 処理装置アクセス方式 | |
| JP2563671B2 (ja) | データモニタ装置 | |
| JPS62143151A (ja) | 共有メモリの診断方式 | |
| JPS6223894B2 (enExample) | ||
| JPS6349935A (ja) | 中央制御装置 | |
| JPS6212540B2 (enExample) | ||
| EP0537898A2 (en) | Computer system including video subsystem | |
| JPS61131156A (ja) | マルチプロセツサシステム | |
| JPS63156263A (ja) | アダプタのメインテナンス方式 | |
| JPS6240748B2 (enExample) |