JPH01140368A - サイクリックマルチプロセッサシステム - Google Patents
サイクリックマルチプロセッサシステムInfo
- Publication number
- JPH01140368A JPH01140368A JP62299035A JP29903587A JPH01140368A JP H01140368 A JPH01140368 A JP H01140368A JP 62299035 A JP62299035 A JP 62299035A JP 29903587 A JP29903587 A JP 29903587A JP H01140368 A JPH01140368 A JP H01140368A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- processors
- output
- storage device
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/30—Hydrogen technology
- Y02E60/50—Fuel cells
Landscapes
- Multi Processors (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62299035A JPH01140368A (ja) | 1987-11-27 | 1987-11-27 | サイクリックマルチプロセッサシステム |
| US07/133,298 US5062043A (en) | 1986-12-16 | 1987-12-15 | Information collecting and distributing system providing plural sources and destinations with synchronous alternating access to common storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62299035A JPH01140368A (ja) | 1987-11-27 | 1987-11-27 | サイクリックマルチプロセッサシステム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01140368A true JPH01140368A (ja) | 1989-06-01 |
| JPH0542026B2 JPH0542026B2 (enExample) | 1993-06-25 |
Family
ID=17867370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62299035A Granted JPH01140368A (ja) | 1986-12-16 | 1987-11-27 | サイクリックマルチプロセッサシステム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01140368A (enExample) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4831846A (enExample) * | 1971-08-30 | 1973-04-26 | ||
| JPS5797133A (en) * | 1980-12-05 | 1982-06-16 | Minolta Camera Co Ltd | Control system of data transfer |
| JPS5864558A (ja) * | 1981-10-14 | 1983-04-16 | Hitachi Ltd | 計算機システム |
-
1987
- 1987-11-27 JP JP62299035A patent/JPH01140368A/ja active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4831846A (enExample) * | 1971-08-30 | 1973-04-26 | ||
| JPS5797133A (en) * | 1980-12-05 | 1982-06-16 | Minolta Camera Co Ltd | Control system of data transfer |
| JPS5864558A (ja) * | 1981-10-14 | 1983-04-16 | Hitachi Ltd | 計算機システム |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542026B2 (enExample) | 1993-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0138964B1 (en) | Apparatus for controlling access to a memory | |
| US4835684A (en) | Microcomputer capable of transferring data from one location to another within a memory without an intermediary data bus | |
| US4903197A (en) | Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank | |
| JPH0728758A (ja) | ダイナミックタイムループ調停及び装置 | |
| EP0055623B1 (en) | Direct memory-access mode for a high-speed memory system | |
| EP0395377B1 (en) | Status register for microprocessor | |
| JPH01140368A (ja) | サイクリックマルチプロセッサシステム | |
| JP2003281074A (ja) | ダイレクトメモリアクセス装置 | |
| JPS6232832B2 (enExample) | ||
| JPH0333951A (ja) | マイクロコンピュータシステム | |
| KR940002595Y1 (ko) | Cpu보드상의 이중 포트 기억장치 회로 | |
| WO1987006365A1 (fr) | Systeme de commande d'analyse de signaux pour un controleur de machines programmables (pmc) | |
| JPS60134956A (ja) | 情報処理システム | |
| JPH05100991A (ja) | データ読出回路 | |
| JPH01296352A (ja) | 二重化処理装置 | |
| JPH01116861A (ja) | データ転送システム | |
| JPS646495B2 (enExample) | ||
| JPH03220683A (ja) | マイクロコンピュータ | |
| JPS6336021B2 (enExample) | ||
| JPH02125358A (ja) | 多重バスメモリアクセス調停方式 | |
| JPS59189433A (ja) | ダイレクトメモリアクセスによるデ−タ消去方式 | |
| JPS6132710B2 (enExample) | ||
| JPS59154524A (ja) | 分散形処理装置のデ−タ転送装置 | |
| JPS5856891B2 (ja) | 情報処理システム | |
| JPH11167519A (ja) | メモリリフレッシュ制御回路、メモリ、メモリモジュー ル、デジタル装置 |