JPH0113210B2 - - Google Patents
Info
- Publication number
- JPH0113210B2 JPH0113210B2 JP57153766A JP15376682A JPH0113210B2 JP H0113210 B2 JPH0113210 B2 JP H0113210B2 JP 57153766 A JP57153766 A JP 57153766A JP 15376682 A JP15376682 A JP 15376682A JP H0113210 B2 JPH0113210 B2 JP H0113210B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- substrate
- insulating film
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H10P14/2905—
-
- H10P14/24—
-
- H10P14/271—
-
- H10P14/3411—
Landscapes
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57153766A JPS59134819A (ja) | 1982-09-03 | 1982-09-03 | 半導体基板の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57153766A JPS59134819A (ja) | 1982-09-03 | 1982-09-03 | 半導体基板の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59134819A JPS59134819A (ja) | 1984-08-02 |
| JPH0113210B2 true JPH0113210B2 (en:Method) | 1989-03-03 |
Family
ID=15569659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57153766A Granted JPS59134819A (ja) | 1982-09-03 | 1982-09-03 | 半導体基板の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134819A (en:Method) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4758531A (en) * | 1987-10-23 | 1988-07-19 | International Business Machines Corporation | Method of making defect free silicon islands using SEG |
| US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
| US5135884A (en) * | 1991-03-28 | 1992-08-04 | Sgs-Thomson Microelectronics, Inc. | Method of producing isoplanar isolated active regions |
| US5213989A (en) * | 1992-06-24 | 1993-05-25 | Motorola, Inc. | Method for forming a grown bipolar electrode contact using a sidewall seed |
-
1982
- 1982-09-03 JP JP57153766A patent/JPS59134819A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59134819A (ja) | 1984-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4530149A (en) | Method for fabricating a self-aligned vertical IGFET | |
| US4637127A (en) | Method for manufacturing a semiconductor device | |
| US5266813A (en) | Isolation technique for silicon germanium devices | |
| US6399429B1 (en) | Method of forming monocrystalline silicon layer, method for manufacturing semiconductor device, and semiconductor device | |
| KR100244812B1 (ko) | 반도체 장치 및 그 제조 방법 | |
| US4619033A (en) | Fabricating of a CMOS FET with reduced latchup susceptibility | |
| JPH0582439A (ja) | 絶縁層の上に成長層を有する半導体装置の製造方法およびmos半導体装置 | |
| JPS5893221A (ja) | 半導体薄膜構造とその製造方法 | |
| JPH0240923A (ja) | バイポーラ・トランジスタの製造方法 | |
| US4992846A (en) | Polycrystalline silicon active layer for good carrier mobility | |
| JP2654055B2 (ja) | 半導体基材の製造方法 | |
| JPH09115921A (ja) | 半導体装置及びその製造方法 | |
| JPH0563439B2 (en:Method) | ||
| JP2989051B2 (ja) | 炭化シリコンバイポーラ半導体装置およびその製造方法 | |
| JPH0113210B2 (en:Method) | ||
| JP2560376B2 (ja) | Mosトランジスタの製造方法 | |
| JPH04373121A (ja) | 結晶基材の製造方法 | |
| JPH0249019B2 (ja) | Handotaisochinoseizohoho | |
| JP2527016B2 (ja) | 半導体膜の製造方法 | |
| JPH0470771B2 (en:Method) | ||
| KR940010920B1 (ko) | Soi 구조의 반도체 장치 제조 방법 | |
| JPS58121642A (ja) | 半導体装置の製造方法 | |
| JP2527015B2 (ja) | 半導体膜の製造方法 | |
| JP2981777B2 (ja) | 半導体基板の製造方法 | |
| KR930001558B1 (ko) | 바이폴라 트렌지스터의 제조방법. |