JPH011233A - Method for manufacturing semiconductor devices and masks used in the method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technique for forming a groove, particularly a deep groove (trench) with a narrow groove width, in the main surface of a semiconductor substrate in semiconductor device manufacturing, such as a groove element. Concerning current technology applied to isolation and trench capacitor manufacturing technology.

[Conventional technology]

As a technology for electrically isolating each element in an integrated circuit (isolation technology), a full-surface pnn junction using a pn junction is used.
Junction isolation technology Sidewall insulation isolation technology Full-surface insulation isolation technology is known. In addition, in the sidewall insulator isolation technology, L, 0CO3 (Local Oxidation
n of 5i-1icon), l5oplana
Selective oxidation method called r, ■-groove, U-1so (
Trench filling method (trench isolation) called U-gr-oove l5olation)
There is.

Regarding the groove filling method, for example, Science
“Very LSI Device Handbook J” published by Forum Inc.
It is described in 19B3, P139-P143.

[Problem that the invention seeks to solve]

ICs and chips incorporating integrated circuits (ICs) and the like are manufactured by manufacturing unit integrated circuit elements vertically and horizontally on two semiconductor substrates (wafers), and then dividing the wafer vertically and horizontally. For this reason, forming more unit integrated circuit elements on -1 wafer leads to a reduction in ICC ramp burst.

As a means of making unit integrated circuit elements smaller, it is important to further reduce the size of each element in the unit integrated circuit element.
It is also important to shorten the width of the ii region (isolation region).

As a technique for shortening the width of the isolation region, a trench filling method called "■=groove, U-1so" has been developed as described above.

According to this groove embedding method, the width of the groove is, for example, 2μ.
It can be made about m. Further, the depth of the groove can be set to a desired depth regardless of the groove width, for example, 5 μm.
It can also be made as deep as m.

For these reasons, this groove is also called a trench (deep groove).

By the way, 5 things about trench isolation like this!
The inventor of the present invention has revealed that, as described below, a phenomenon occurs in which sufficient isolation withstand voltage cannot be obtained at the corners of the element.

That is, FIG. 11 is a plan view showing an outline of the conventional isolation mask 1. As shown in FIG. In this figure, the hatched area is a translucent area 2 that does not transmit light, and the other strip-shaped blank area is a translucent area (strip-shaped translucent portion) 3 that transmits light. Trench isolation is usually provided in the shape of a rectangular frame, and elements such as transistors are formed in islands (wells) within this rectangular frame. Therefore, the band-shaped transparent portion 3 in the mask 1 basically has a rectangular frame pattern 4.

By the way, when a trench (groove: deep groove) is formed on the main surface of a semiconductor substrate (wafer) using such a mask 1,
As shown in FIG. 12, in the corner part 7 of the trench 6 arranged in a rectangular shape on the surface of the wafer 5, the inner part of the corner protrudes so as to sandwich the width of the trench 6, and the protruding part 8 , and the outer corner is not bent at 90 degrees, but draws an arc so as to sandwich the width of the trench 6, forming a rounded part 9, and the groove width a of this corner 7 extends linearly. A phenomenon occurs in which the groove width of the trench portion becomes narrower than the trench width. This is because, for reasons such as forming a fine pattern, the resist is exposed to light using a minimum exposure time, that is, so-called underexposure. For this reason, as mentioned above, in the photosensitive pattern exposed in the shape of a rectangular frame, poor exposure occurs at the corners 7,
As shown in FIG. 1O, the inner corner portion becomes sharp and the outer corner portion becomes arcuate.

The trench 6 is, for example, as shown in FIG.
It is provided on the main surface of the wafer 5. Uni/\5 is, for example, a semiconductor substrate 10 made of p-type silicon, and an n+ type buried layer 1 formed on the main surface of this semiconductor substrate 10, respectively.
1 and an n-type layer 12 provided on this buried layer 11.

Also, when forming the trench 6, the main surface of Ueno X5 should be! ! ! A lamina is provided. This insulating film includes, for example, the SiO2 film 13 on the main surface of the wafer 5 in the figure;
It consists of a Si3N4 film 14 in place of the 5iOz film 13.

In such a trench 6, if the trench width W is small, the interval between the n+ type buried layers 11 becomes narrow, and the parasitic pnp
This makes it easier for the h transistor to operate.

Furthermore, if the depth d of the trench 6 from the lower edge of the buried layer 11 is small, the isolation breakdown voltage deteriorates, resulting in failure of the device during high-speed or low-speed operation.

Furthermore, if the groove bottom becomes sharp due to insufficient etching due to the narrow exposure width of the resist,
When an insulating film (not shown) is formed on the side surface of the trench, crystal defects are likely to occur.

An object of the present invention is to provide a groove forming technique that can form a desired groove width even in a bent pattern portion.

Another object of the present invention is to provide a technology for manufacturing semiconductor devices with high isolation voltage.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows: In the present invention, a light-transmitting area has a rectangular frame shape and a pattern-based mask is used. After that, the resist on the main surface of the wafer is under-exposed, and then, after removing the exposed portion of the resist due to exposure, when forming a trench using the remaining resist as a mask, in the rectangular frame-shaped belt-shaped bent transparent part of the mask, , an auxiliary transparent region is provided inside the corner of the bent portion.

[Effect]

According to the above-mentioned means, according to the present invention, when a resist is exposed in a rectangular frame shape on the main surface of the wafer by under-exposure in forming U-1so in the manufacture of semiconductor devices, the rectangular frame shape of the mask Since an auxiliary light-transmitting area is provided in the band-shaped bent light-transmitting area, even if the photosensitive area is exposed in the rectangular frame shape of the resist due to underexposure, the loss of exposure due to underexposure is compensated for even at the corners. Since it is exposed to light so that it has a desired width, it is possible to form a groove (trench) having a desired isolation voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic plan view of a mask according to an embodiment of the present invention, FIG. 2 is a plan view of a wafer showing the photosensitive pattern of the resist, and FIG. 3 is a mask approximating the Yask pattern actually used. FIGS. 4 to 9 are sectional views showing the trench formation process, FIG. 4 is a sectional view of the wafer showing the developed resist portion, and FIG. 5 is a sectional view of the wafer showing the developed resist portion. 1! A cross-sectional view of the wafer showing a state where the edge 1 film is partially etched, FIG. 6 is a cross-sectional view of the wafer with a trench provided, and FIG. 7 is a U-Tso formed by filling the trench with an insulating film. 8 and 9 are cross-sectional views showing the process of embedding polycrystalline silicon (PolySi) into the trench, and FIG. In this embodiment, the main surface of the silicon semiconductor substrate is
An example in which a well is formed using 1so and a transistor is formed in this well will be explained below.

The U-1so is formed with a width of 1.91 tm and a depth of 5 μm. In this case, the width of the band-shaped transparent part of the mask is 0.
．． It becomes 9 μm.

First, a wafer 5 is prepared. As shown in FIG. 4, this wafer 5 includes a semiconductor substrate 10 made of, for example, p-type silicon, an nx-shaped buried layer II formed on the main surface of this semiconductor substrate 10, and this buried layer. 11 and an n-type layer 12 provided on top of the n-type layer 12. Also, U-1
Prior to the formation of so, trenches 6 are formed as shown in FIG. In order to form this trench 6, as shown in FIG. 4, the entire main surface of the wafer 5 is completely covered. A film and resist 15 are provided.

This insulating film consists of a Si○2H213 with a thickness of about O01 μm placed on the main surface of the wafer 5, an S+tN film I4 with a thickness of about 0.5 μm placed on this Si○2 film 13, and this Si:+Nn1114 PSC (phosphorus silicate glass) film 16 with a thickness of about 1.6 μm placed on top
It consists of

Such a wafer 5 is processed by a reduction projection exposure apparatus, for example,
It is exposed with a 5:1 stepper and developed to form grooves 17 as shown in FIG. in this case,
The mask l used has a pattern as shown in FIG. In the figure, the area indicated by hunting is the light-shielding area 2, and the blank area is the light-transmitting area (band-shaped light-transmitting part) 3. The band-shaped transparent portion 3 shown in the figure is a basic pattern for forming a well, and constitutes a rectangular frame pattern 4. Therefore, this band-shaped transparent portion 3
has band-shaped bent light-transmitting portions 18 at four locations.

The mask 1 of this embodiment differs from the conventional mask 1 shown in FIG. 11 in the following points. The mask 1 of this embodiment has triangular auxiliary light-transmitting regions 19 inside the corners of the rectangular frame pattern 4, that is, the band-shaped bent light-transmitting portions 18.

That is, the four corners of the rectangular well light-shielding region 2a surrounded by the band-shaped light-transmitting portion 3 are chipped as if they were chamfered at 45 degrees, and these triangular chipped portions are A transparent region 19 is configured.

Generally, in order to form a fine pattern, the resist is exposed to light using the minimum amount of exposure, that is, so-called under-exposure. Therefore, in this underexposure, at the corners of the rectangular frame pattern 4, as shown in FIG. In the pattern, the exposure amount is small, so in the band-shaped bent transparent portion 18, the 12th
A phenomenon of insufficient exposure occurs as shown in the figure.

Therefore, in this embodiment, auxiliary transparent areas 1 are provided at the corners of the rectangular frame pattern 4 to compensate for the insufficient amount of angry light.
9, the bent portion of the rectangular frame pattern of the resist 15 is also exposed over a sufficient width, as shown in FIG. As a result, the resist 15 is punched out in the shape of a rectangular frame, and the corners of the rectangular frame have a shape in which a groove of a constant width is bent at a right angle. A trench 6, which will be described later, is formed to match this fine rectangular frame-shaped photosensitive pattern 20. Note that the photosensitive pattern 20 is indicated by hatching in FIG.

Next, using the resist 15 as a mask, the PSG film 1 is
6 is etched. In this case as well, the etching is performed accurately in accordance with the punched pattern of the resist 15, resulting in a fine pattern. Thereafter, the resist 15 is removed, and as shown in FIG. 5, the Si, N, film 14 and 5iOz film 13 are etched and removed using different etchants. This S! 3 The N4 film 14 and the SIO □ film 13 are etched accurately according to the punching pattern of the film portion 3 resist 15, resulting in a fine pattern.

Next, as shown in FIG. 6, anisotropic dry etching is performed to continuously etch the n-type layer 12 and the buried layer 11, forming a deep trench (trench) that reaches the surface layer of the semiconductor substrate IO. form 6. This trench 6 has a groove width of 1.2 μm and a depth of 5 μm. In addition, in this etching, since the rectangular frame pattern formed by the resist 15 is a fine pattern as described above, the corner 7 of the trench 6 is also etched without damaging the shape. As shown in FIG. 6, the trench width is not narrower than the trench width of the trench 6 extending linearly. Furthermore, the bottom of the trench 6 is also etched without being etched away. As a result, the buried layer 1
The depth d from 1 to the bottom of the l-wrench 6 and the groove width W are:
Each has the desired dimensions, and the desired isolation withstand voltage can be obtained.

Next, as shown in FIG. 7, PS on the n-type layer 12 is
After removing the G film 16, the inner wall of the trench 6 is oxidized,
An insulating film, for example, a SiO□ film 21 is formed. Next, after removing the S ir N4HJI 4, as shown in FIG. 8, a polysilicon film 23 is deposited by, for example, the CVD method to fill the trench 6. Thereafter, the excess polysilicon film 23 is removed by etching to form U-1so24 as shown in FIG. This etching is a planarization process, and by this process, the well (functional element part) 25 surrounded by U-Iso24 and U-Iso24
are made to have the same height to planarize the main surface of the wafer 5. After that, the insulating film 13 is removed by etching, and then the U
An insulating film 22 is formed on the top of the trench, completing the U-groove isolation.

Thereafter, using this wafer 5, functional elements such as an emifter (E), a base (B), and a collector (C) are placed in the well 25 as shown in FIG.
Form a transistor consisting of The transistor has a p-type base region 26 provided on a part of the surface layer of the n-type layer 12, and an n-type emitter electrode 27 provided on a part of the surface layer of the base region 26. ing. Also,
A base electrode 28 is provided on the base region 26,
Further, an emitter electrode 29 is provided on the emitter region 27. The n-type layer 12 also has a lower buried layer 1.
1, and a collector electrode 31 is provided on this n4- shadow region 30. Note that 32 is an insulating film.

In this way, functional elements are formed in the wells 25 of the wafer 5. Note that the U-Iso 24 is provided closely adjacent to the main surface of the wafer 5. Therefore, a mask I as shown in FIG. 3 is used for forming the trench for forming U-1so24. This figure is a schematic diagram in which 3&[l frame-shaped band-shaped transparent parts 3 are provided to form three wells. In this case, the adjacent rectangular frame pattern 4
has a structure in which one side of the rectangular frame pattern 4 is shared. Corners of each rectangular frame pattern 4, that is, band-shaped bent transparent portions 1
8, each is provided with an auxiliary light-transmitting area 19,
The corners of the trench 6 are formed finely. Note that if the auxiliary transparent area 19 is not provided, the 12th
The phenomenon in which the groove width at the corners of the trench 6 becomes narrower as shown in FIG.
The occurrence becomes more difficult in the portion where 8 is in a butt state. Therefore, in some cases, it may be unnecessary to provide the auxiliary light-transmitting region 19 in the band-shaped bent light-transmitting portion 18 in a portion where the band-shaped light-transmitting portion 3 extends in the shape of a cross or a T-junction. This may be selectively determined depending on the desired degree of isolation breakdown voltage.

According to such an embodiment, the following effects can be obtained.

(1) In the trench-forming mask of the present invention, when exposing the resist in the shape of a rectangular frame, the strip-shaped bent light-transmitting portion of the mask has a shape that is suitable for the eye freezing caused by the exposure caused by underexposure. Since the triangular auxiliary light-transmitting area is provided, the strip pattern of the resist bent at right angles is exposed to the desired dimensions. As a result, the trenches provided in a rectangular frame pattern on the main surface of the wafer are also formed by appropriate etching, which eliminates the possibility of the trench width becoming partially narrow at the bent corners or the trench bottom becoming sharp. This effect can be obtained.

(2) According to the above (1), according to the present invention, since the groove width and depth of the trench can be formed appropriately, it is possible to form a trench having a high isolation voltage with good reproducibility. Round.

(3) According to the above (2), according to the present invention, the manufacturing margin of the trench is improved.

(4) According to the above (2), according to the present invention, by coating the trench with an insulating film or embedding an insulating film, etc., the U-1SO
The effect is that it is possible to form a .

(5) According to the above (2), according to the present invention, the groove bottom of the trench described in item 11 does not become locally sharp, so that crystal defects such as dislocations occur in the semiconductor crystal during the heat treatment for depositing the insulating film. U-1 that no longer occurs and has excellent quality and high confidence
The effect that so can be formed is obtained.

(6) According to the above (1) to (5), according to the present invention, U-Iso with high isolation voltage and narrow isolation width can be formed with a high yield.
A synergistic effect can be obtained in that high-density, high-integration semiconductor devices can be provided at low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

In the above description, the invention made by the present inventor was mainly applied to the U-groove isolation technology, which is the background field of application, but the present invention is not limited thereto. For example, it can be applied to a trench capunk technique in which an insulating film is deposited on the wall surface of a trench and polycrystalline silicon serving as an electrode is buried in the trench. It is also applicable to a latch-up countermeasure technique in which U-[so is provided between an n-type well and a p-type well.

At least the present invention is applicable to trench formation technology.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

According to the present invention, U − in the manufacture of semiconductor devices
[When forming a resist in the form of a rectangular frame on the main surface of the wafer by under-exposure, an auxiliary light-transmitting area must be provided in the rectangular frame-shaped band-shaped bent light-transmitting part of the mask. Therefore, even with underexposure, the exposed areas in the rectangular frame shape of the resist are exposed in such a way that the loss of exposure due to underexposure is compensated for even at the corners, so that exposure can be performed with a desired width. Therefore, a trench having a desired isolation voltage can be formed. Therefore, a semiconductor device with excellent isolation breakdown voltage can be manufactured.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a mask according to an embodiment of the present invention. FIG. 2 is a plan view of a wafer showing the photosensitive pattern of the resist. FIG. 3 is a schematic plan view of a mask that approximates the mask pattern actually used. , FIG. 4 is a cross-sectional view of the wafer showing the developed resist portion in the trench formation process, FIG. 5 is a cross-sectional view of the wafer showing the insulating film partially etched, and FIG. 6 is the trench-forming step. FIG. 7 to FIG. 9 are cross-sectional views showing a method of manufacturing U-1SO formed by embedding an insulating film in a trench, and FIG. 11 is a schematic plan view showing a conventional mask; FIG. 12 is a plan view of a wafer showing a groove formed using a conventional mask; FIG. 13 is also a sectional view of the groove. DESCRIPTION OF SYMBOLS 1... Mask, 2... Light shielding area, 3... Band-shaped transparent part, 4... Rectangular frame pattern, 5... Wafer, 6...
・Trench, 7...Corner, 8...Protrusion, 9...
Rounded portion, IO...Semiconductor substrate, 11...Buried layer, 1
2...n-type layer, 13...5iO=film, 14...5
i3N- film, 15...Resist, 16...PSG film, 17...Groove, 1st...Band-shaped bent transparent part, 19...
- Auxiliary transparent area, 20... Photosensitive pattern, 21...
5iOz film, 22...insulating film, 24...U-1so
, 25...well, 26...base region, 27...
- Emitter region, 28...Base electrode, 29...Emitter electrode, 30...N+ type region 31...Collector electrode. -1 Agent Patent Attorney Katsuma Ogawa No. 1 Figure 2! , 7 Figure 6 σ-Ugo/＼ a-Tojisu Figure 8 Figure 9 Figure 1

Claims (1)

[Claims] 1. Forming an insulating film on the main surface of a semiconductor substrate and a photoresist film provided on the insulating film, and exposing the photoresist film using a mask having a band-shaped bent light-transmitting part. a step of removing the photoresist film portion exposed to light; a step of removing the insulating film using the photoresist film as a mask; and an anisotropic dry etching step using the photoresist film and/or the insulating film as a mask. forming a groove in a main surface of a substrate, the method comprising the step of forming a groove in a main surface of a substrate, the band-shaped bent light-transmitting portion of the mask having an auxiliary light-transmitting region provided inside a corner of the bent portion; A method for manufacturing a semiconductor device, characterized in that: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the exposure is performed by underexposure. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is an isolation groove. 4. A mask having a band-shaped bent light-transmitting portion, wherein the band-shaped bent light-transmitting portion of the mask is provided with an auxiliary light-transmitting region inside a corner of the bent portion.