JP3004116B2 - Method for manufacturing semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit .
Law, a manufacturing method <br/> separation type semiconductor device having a more specific depths different monocrystalline silicon (Si) island in the same substrate in the.

[0002]

2. Description of the Related Art As a semiconductor device having a dielectric isolation structure, there is a dielectric isolation type semiconductor device in which semiconductor elements having different depths, such as high breakdown voltage and low breakdown voltage, are mixedly mounted on the same substrate. In such a dielectric isolation type semiconductor device, for example,
As described in -97037, the island where the high breakdown voltage element is formed is made deeper according to the depletion layer width at the time of reverse bias,
The island where the low breakdown voltage element is formed is made shallow to reduce the collector resistance of the vertical NPN transistor. By forming the depth of each single-crystal Si island in this way, attempts have been made to optimize the island depth in accordance with the characteristics of the internal element.

FIG. 4 is a plan view of a dielectric isolation type semiconductor device having a different depth according to the prior art. FIG. 5 is a diagram showing a manufacturing process of the semiconductor device shown in FIG.
3 shows a cross section taken along line AA ′ of FIG. In these figures, reference numerals H1 to H5 indicate high withstand voltage islands, reference numerals L1 to L5 indicate low withstand voltage islands, and reference numeral 1 indicates a single crystal silicon substrate.

A process for forming a semiconductor device as shown in FIG. 4 using the silicon substrate 1 will be described below with reference to FIG. First, a single crystal silicon substrate 1 having an N-type (100) crystal orientation plane is oxidized, and a pattern of a thermal oxide film 2 is formed on one main surface by ordinary photolithographic etching (a).

Next, the silicon substrate 1 is anisotropically etched using the thermal oxide film 2 as a mask to form a recess 3 (b), and thereafter, the thermal oxide film 2 is removed and the silicon substrate 1 is removed from the main surface of the silicon substrate. A thermal oxide film is grown.

Next, a thermal oxide film 4 is formed by ordinary photolithographic etching (c).

Next, the V-groove 5 is formed by performing anisotropic etching again using the thermal oxide film 4 as a mask (d).

Next, after removing the thermal oxide film 4, an N ⁺ buried layer 6 is formed on the main surface of the silicon substrate 1, and an isolation insulating film 7 is formed on the N ⁺ buried layer 6; A support layer 8 of polycrystalline silicon or the like is formed on the isolation insulating film 7 (e).

Finally, the main surface on the opposite side (the lower side in the figure) of the silicon substrate 1 is ground and polished until the tip of the V-groove 5 is exposed, that is, the line a-a in FIG.
A dielectric isolation substrate having islands having different depths, that is, deep islands and shallow islands is completed.

The deep island formed in this manner becomes a high breakdown voltage element formation region, and the shallow island becomes a low breakdown voltage element region.

[0011]

However, in such a dielectric isolation type semiconductor device having different depths, the high breakdown voltage element and the low breakdown voltage element are arranged without particular distinction.
There is a problem in that the shape of the island on which the low breakdown voltage element is formed is lost and the electrical characteristics are impaired.

That is, in the dielectric isolation type semiconductor device in which single-crystal silicon islands having different depths are arranged in the same substrate without particular distinction, the following problems occur in the manufacturing process. .

In the photolithography process shown in FIG. 5C, as shown in FIG. 6A, the resist 12 easily accumulates at the boundary 11 between the deep island and the shallow island, and as shown in FIG. Pool 15 around the deep island region 13
Occurs. As described above, when the difference in the film thickness of the resist 12 becomes large, it becomes difficult to optimize the exposure conditions for forming the thermal oxide film, and as shown in FIG. In practice, a thermal oxide film 4 as shown by a solid line is formed.

Therefore, as shown in FIG. 6 (2b), the pattern shape of the thermal oxide film 4 is broken, and finally, as shown in FIG.
(c) As shown in (2c), the shape of the shallow island to be formed as shown by the dotted line portion collapses as shown by the solid line portion, adversely affecting the electrical characteristics of the semiconductor device formed in those islands. I will.

Further, as shown in FIG. 6 (2a), when the shape of the deep island region 13 has a dent portion 14 or the like, there is a problem that the resist 12 tends to accumulate particularly, and a shallow island cannot be formed. .

As described above, in the prior art, since shallow islands and deep islands are randomly arranged, the amount of resist pool increases, and the area where shallow islands are formed is limited. Therefore,
Such a conventional semiconductor integrated device has disadvantages in that designing and manufacturing are difficult, the chip size is large, and the cost is high.

The present invention solves the drawbacks of the prior art and provides a method of manufacturing a semiconductor integrated device having dielectric isolation substrates of different depths which is easy to design and manufacture and realizes a small chip size. The purpose is to provide.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor integrated device having a dielectric isolation structure including shallow islands having different depths and deep islands in the same substrate. In a first part, the deep island is located in a second part. In addition, the shallow island and the deep island are arranged such that the boundary is substantially straight.

[0019]

According to the present invention, a shallow island and a deep island are divided into a first portion and a second portion, respectively, and the islands are arranged so that the boundary between these islands is substantially straight. By adopting such an arrangement, it is possible to prevent an excessively large amount of resist from accumulating, so that a shallow island can be easily formed.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated device according to the present invention.

FIG. 1 is a schematic plan view showing an embodiment of a semiconductor integrated device having a dielectric isolation semiconductor substrate including shallow islands and deep islands having different depths in the same substrate. FIG. 2 is a cross-sectional view taken along a dashed line BB ′ shown in FIG.

In FIG. 1, reference numerals H1 to H5 indicate high withstand voltage islands as deep islands, reference numerals L1 to L5 indicate low withstand voltage islands as shallow islands, and reference numerals D1 to D3 indicate dummy islands. As shown in FIG.
H5 is collectively arranged in the first part (the left side in the figure),
In addition, the low withstand voltage islands L1 to L5 are connected to the second part (the right side in the figure).
And put them together. Thereby, deep island H and shallow island L
The area of the boundary portion is reduced to reduce the amount of resist pool generated in the manufacturing process of the semiconductor integrated device.

The semiconductor integrated device according to the present embodiment can be manufactured by the same steps as the manufacturing method described in the prior art. In this embodiment, the same components as those of the conventional technology are denoted by the same reference numerals. That is, in FIG. 2, reference numeral 6 denotes an N ⁺ buried layer, reference numeral 7 denotes an isolation insulating film, and reference numeral 8 denotes a support layer such as polycrystalline silicon.

In this embodiment, as shown in FIG. 1, the deep island H is arranged at the boundary between the deep island H and the shallow island L.
The boundaries between H1, H3, and H5 and the shallow islands L1, L2, and L4 are linearly arranged. This makes it possible to prevent abnormal accumulation of resist as shown in FIG.

In this embodiment, as shown in FIG.
At the boundary between the deep island H and the shallow island L, dummy islands D1 to D3 of shallow islands where no semiconductor element is formed are provided linearly in correspondence with the deep island H and the shallow island L. By arranging the dummy island D at the boundary, even if the shape of the island collapses at the boundary, the dummy island D is a dummy island in which no semiconductor element is formed, and thus may affect the electrical characteristics of the semiconductor integrated device. Absent.

FIG. 3 is a perspective view including a cross section when the semiconductor integrated device shown in FIG. 1 is completed. As shown in the figure, the wiring patterns M1 to D3 are arranged on the dummy islands D (D1 to D3).
If it is used as the area of M4, it can be considered that the increase in chip size due to the dummy island D does not become substantial. If these wiring patterns M1 to M4 are used for power supply wiring and the like, the upper region of the dummy island D can be used very effectively. Therefore, even if the dummy islands D are provided as in this embodiment, the chip size does not substantially increase.

In this embodiment, the deep island H, the shallow island L, and the dummy island D disposed at the boundary are arranged as shown in FIG. 1, but the deep island H, the shallow island L, and the dummy island D are arranged as shown in FIG. The number and arrangement are not particularly limited in this way, and variations and modifications that can be made by those skilled in the art without departing from the spirit of the present invention are included in the scope of the present invention.

[0028]

As described above, the manufacture of the semiconductor integrated device of the present invention is described .
According to the manufacturing method, shallow island and deep island in the method of manufacturing the same
By adding a step of forming a dummy island at the boundary with the resist, it is possible to prevent an abnormally large amount of resist from remaining in the photolithography step, thereby facilitating the formation of a shallow island. Therefore, a semiconductor integrated device having a dielectric isolation substrate having a different depth for mounting a high breakdown voltage element and a low breakdown voltage element is manufactured.
By applying the present invention at this time , the design and manufacturing are facilitated, and the effects of reducing the chip size and reducing the cost can be expected.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an embodiment of a semiconductor integrated device having a dielectric isolation structure according to the present invention;

FIG. 2 is an alternate long and short dash line BB 'in the embodiment shown in FIG.
Sectional view when cut between,

FIG. 3 is a perspective view including a cross section of the embodiment shown in FIG. 1,

FIG. 4 is a schematic plan view of a semiconductor integrated device having a dielectric isolation structure according to the related art;

FIG. 5 is a process diagram showing a manufacturing process of a semiconductor integrated device having a dielectric isolation structure according to the related art;

FIG. 6 is an explanatory diagram for explaining a problem of a semiconductor integrated device having a dielectric isolation structure according to a conventional technique.

[Explanation of symbols]

 H1 to H3 High withstand voltage island L1 to L3 Low withstand voltage island D1 to D3 Dummy island M1 to M4 Wiring pattern

Claims (1)

(57) [Claims] A main surface and a back surface different from said main surface.
Preparing a semiconductor substrate having, and a step of masking a partial region of the main surface, removing the main surface is not masked, the
Forming a region of unevenness on the main surface side, removing the mask, and forming a deep island mask on the region of the protrusion.
Performing a masking step, a step of forming a mask for a shallow island in the region of the concave portion , and a step of forming a mask for the deep island in the region of the concave portion.
Make a dummy island mask between the shallow island mask
A process for each of the deep island, the shallow island, and the dummy island.
Forming a separation groove in a region of the uneven portion where no mask is formed.
That the process, and removing the respective masks, the area of the uneven portion, the separation absolute
Forming an edge film and a support layer; and the back surface of the semiconductor substrate until reaching the separation groove.
And removing the side.
A method for manufacturing a release type semiconductor integrated device.