JPH01116458U - - Google Patents
Info
- Publication number
- JPH01116458U JPH01116458U JP1208288U JP1208288U JPH01116458U JP H01116458 U JPH01116458 U JP H01116458U JP 1208288 U JP1208288 U JP 1208288U JP 1208288 U JP1208288 U JP 1208288U JP H01116458 U JPH01116458 U JP H01116458U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- utility
- scope
- registration request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は、本考案に係るリードフレームの平面
図、第２図は、そのリード線の断面図、第３図は
、従来のリードフレームの平面図、第４図は、樹
脂封止方法を説明するための断面図である。
Ａ…樹脂封止位置、２２…リード線、２４…放
熱板兼アイランド、Ｂ…粗面。
Fig. 1 is a plan view of a lead frame according to the present invention, Fig. 2 is a sectional view of its lead wire, Fig. 3 is a plan view of a conventional lead frame, and Fig. 4 is a resin sealing method. It is a sectional view for explanation. A... Resin sealing position, 22... Lead wire, 24... Heat sink/island, B... Rough surface.
Claims (1)
外部露出部表面を粗面にしたことを特徴とするリ
ードフレーム。 A lead frame characterized by roughened surfaces of externally exposed parts such as lead wires and heat sinks adjacent to resin-sealed positions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1208288U JPH01116458U (en) | 1988-01-29 | 1988-01-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1208288U JPH01116458U (en) | 1988-01-29 | 1988-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01116458U true JPH01116458U (en) | 1989-08-07 |
Family
ID=31221208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1208288U Pending JPH01116458U (en) | 1988-01-29 | 1988-01-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01116458U (en) |
-
1988
- 1988-01-29 JP JP1208288U patent/JPH01116458U/ja active Pending