JPH01114241A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To demodulate a particular modulated wave where the combination form of switching time is changed, as well within the time of one bit by directly holding the output pulse of a reception circuit by a first shift register, and at the same time, inverting it, and holding it by a second shift register, and detecting it by a matrix circuit. CONSTITUTION:The output pulse of the reception circuit 22 is held directly by the first shift register 23, and at the same time, is inverted, and is held by the second shift register 27 as well, and '0', '1' of the data signal outputted by these shift registers 23, 27 is detected by the matrix circuit 28, and is demodulated through a gate circuit 29 and a latch circuit 30 into '0', '1' or a particular data signal corresponding to the output pulse of the reception circuit varying variously within one bit period of the data signal. Thus, by including this particular data in the transmission format of the data signal, the necessary data and a delimiter or a preamble indicating the start or the finish of the data can be easily distinguished, and the reliability of the contents of the data at the time of data transmission is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a demodulation circuit that demodulates a received signal subjected to FSK modulation in N cycles or N/2 cycles within one bit time of a data signal.

[Prior Art and Disadvantages] With the increase in the number of data devices in recent years, there has been an increasing demand for data exchange between these devices.

Therefore, it is necessary to make effective use of the line by using a single coaxial line for transmitting the data signals of each data device, and modulating the data signal with a carrier wave in a burst wave shape and transmitting the data signal. Furthermore, data is generally configured into packets.

Furthermore, there are only two types of data signals: rOJr and IJ, and a special data signal /IPRI-/ is used to make the start, end, end, etc. of data more clear. Things have been done.

Diagram M4 shows a configuration example of a conventional demodulation circuit.

In the figure, the modulated data signal input from terminal 1 is
As shown in FIG. 5(a), when the data signal is rOJ, the voltage changes for two periods within one bit time, and when it is "1", the voltage changes for one period. Receiving circuit 1 that receives this
In step 2, the modulated data signal is amplified to a voltage of a specified value, and shaped into a pulse signal by an internal comparator as shown in FIG. 5 [b]. The synchronizing signal generating circuit 13 generates a clock pulse based on the signal generated at the rising edge or falling nip of the signal.

In order to keep the period of this clock pulse stable, a crystal resonator 14 is connected to the synchronization signal generation circuit 13. The oscillation frequency of this vibrator 14 is divided by an internal counter, and the bird resets this internal counter with a signal to initialize and synchronize. The clock/2 pulse thus obtained is applied to the shift register 15, and the pulse signal shown in FIG. (hereinafter referred to as "EX-OR circuit") is applied to 16 input terminals. The waveform at this time is shown in FIG. 5(c). The other input terminal of the EX OR circuit 16 includes the fifth
The pulse signal shown in Figure (b) is added. The EX OR circuit 16 outputs I'' when the two input levels do not match.
Since the l level signal is output, its output waveform is shown in Figure 5 (
d), and is output to the terminal 17 as a demodulated data signal.

However, such a demodulation circuit can only handle two types of data signals: roJ and rlJ, and cannot demodulate data signals with other special meanings.

Therefore, instead of the above special data signal, this l
By combining two types of data signals, such as IQ 111 and 1110J, it is necessary to create an i4 turn that is not used in normal data signals, which limits the data signals that can be handled. When transmitting data signals in a packet format composed of frames, it is difficult to obtain a frame synchronization signal for separating frames of each data signal when a bit error occurs.

[Object of the invention] This invention was made in view of the above-mentioned circumstances.
In a demodulation circuit that receives a signal modulated by switching daughter transmission in N periods or N/2R periods within 1 bit time by rOJ rlJ of a digital data signal, 1
It is an object of the present invention to provide a demodulation circuit that can also demodulate a special modulated wave in which the combination of the switching times of the two cycles is changed within the bit time.

[Summary of the Invention] The present invention allows the output pulses of the receiving circuit to be directly held in a first shift register, inverted and held in a second shift register, and to adjust the rOJ rlJ of the data signals output from these shift registers. is detected by a matrix circuit, and one of the data signals is detected via a gate circuit and a latch circuit.
It is designed to demodulate data signals rOJ rlJ and other special data signals corresponding to the output pulses of the receiving circuit which vary in a bit cycle.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its circuit configuration. In the figure, 21 is a terminal to which a modulated signal is input, 22 is a receiving circuit that receives the signal input from this terminal 2, and 23 is a pulse output from this receiving circuit 22 (a pulse that shifts and holds the i number). 1 is a shift register, 24 is a crystal oscillator, 25 is a synchronous signal generation circuit that generates a synchronous/4' pulse by the crystal oscillator 24, 26 is an inverter, 27 is this inverter 26
28 is a matrix circuit, 29 is a gate circuit, 30 is a latch circuit, 31 to 33;
#'i each. .about.D2, and 34 is a bit synchronization generation circuit.

A modulated wave having a waveform as shown in FIG. 2 fa) and (b) is input to the terminal 2). This modulated wave is rOJ
6 shows a packet structure that is sent in the form of a burst wave by combining rlJ and a special data pattern, "S" is the silence time when there is no signal, and rpJ is the synchronization signal on the receiving side. Indicates the preamble time for confirmation. This Figure 3(a).

(value) indicates the case where the signal form of the preamplifier is [0101J]. In the figure, "SD" indicates a start delimiter indicating the start of data, "D" indicates valid data, and "ED" indicates an end delimiter indicating the end of data. When the modulated waves having the waveforms shown in FIGS. 2(a) and 2(b) are input to the terminal 21 and sent to the receiving circuit 22,
The receiving circuit 22 amplifies and shapes the waveform as shown in FIG. 2(c).
A signal with the waveform shown in is output.

Here, the waveform of the data signal received by the receiving circuit 22 is 4 as shown in FIG.
Assume that there are different types. For example, in the figure, the data signal "0"
are TH, T within 1 bit time.

shows a two-cycle change in which T is at an "H" level and T, , T is at an "L" level. Similarly, for the data signal "1", TH9To is at "H" level within one bit time, T, TI.

becomes [, J level, indicating a one-cycle change. Data signal 1'-NNJ is special data indicating a non-data pair; 'rHe'r, , 'r, 1'8 is rHJ level, ToITDIT, 'r is 2 bits of 'L' level. Consists of time. Furthermore, in the data signal "S" when there is no signal, all TII-TA are at the rLJ level.

Now, the modulated wave amplified and waveform-shaped by the receiving circuit 22 is
The waveform becomes as shown in FIG. 2(c). When this signal is sent to the synchronization signal generation circuit 25, the synchronization signal generation circuit 25
is the period in which one bit time of the data signal is divided by the rising or falling edge of the pulse, here 4
Generates synchronization pulses with divided periods. This synchronization pulse is controlled by a crystal oscillator 24 in order to keep its period stable.

The first shift register 23 sequentially holds and shifts the signals output from the receiving circuit 22 according to the synchronization signal output from the synchronization signal generation circuit 25. The contents held in the first shift register 23 are sent as they are to the matrix circuit 28 as outputs QA-QH. On the other hand, the signal output from the receiving circuit 22 is inverted by the inverter 26 and then sent to the second shift register 27 as well. This second shift register 27 also holds and shifts the signal from the receiving circuit 22 every time a synchronizing pulse from the synchronizing signal generating circuit 25 is input. The contents held in this second shift register 27 are also sent to the matrix circuit 28 as output QA-QH. Instead of the output of the inverter 26, an inverted output of a converter or a regulator in the receiving circuit 22 may be used. As a result of the above configuration, the outputs QA to QH of the first shift register 23 and the output QA of the second shift register 27 input to the matrix circuit 28
~Q! 1 has the opposite polarity.

Note that the two shift registers 23 and 27 described above have a multi-stage configuration with a number of stages of 8, but this can be arbitrarily determined depending on the number of divisions in one bit of the data signal and the type of data. By configuring the two shift registers 23 and 27 like this, if the data signal transmission speed is high, or if the number of divisions within one bit time of the data signal is increased, it is possible to use the configuration shown in Fig. 2 (c). Even if the pulse width of the received waveform within 1 bit time shown in is narrowed, the output QA~QH1QA~ of the shift register 23.27
Since the time relationship between the two signals is synchronized with the synchronization pulse from the synchronization signal generation circuit 25, the time difference can be reduced.

If the second shift register 27 is not used and the output of the first shift register 23 is inverted via an inverter in each stage, a time delay will occur in the inverter and the high speed This is disadvantageous because it will not be able to handle remote transfers.

The matrix circuit 28 receives a waveform of "H" in FIG.
Output Q on the first shift register 23 side when the level is
In order to select A-QH, the received waveform is
In the figure, when the level is "L", the second shift register 2
Diode 2B to select output QA to 9H on the 7 side
&~,? Set Q. For example, when the data type is "0", by providing diodes 281 to 28n to select QHIQ, ,Q, ,Q,
Is the pattern of TH-w T in Figure 3 rl O10J and the detection pulse output corresponding to the data type "0"? - can be applied to the gate circuit 29. This output timing is determined only when the received signal TH reaches QH of the first shift register 23. For other data types, by setting the diodes 28h to 28n to be selected in the same manner as described above, a detection pulse output corresponding to the data type can be provided to the gate circuit 29.

The bit synchronization generation circuit 34 generates a synchronization signal corresponding to one bit time of the data signal, and is constituted by a counter that divides the frequency of the synchronization signal from the synchronization signal generation circuit 25. This counter is activated when a data signal arrives, that is, when QH, QG, Q, ,Q are at "H" level.
The data "B" in FIG. 3 is reset to the digit t, and thereafter, a bit synchronization pulse is output at the beginning of each 1-bit time.

The output waveform at this time is shown in FIG. 2fgl. The gate circuit 29 handles the data types roJ rxJ shown in FIG.
In order to eliminate mutual interference of the detection pulses corresponding to rNNJrsJ, the bit synchronization pulse and the AND (not shown)
It is output to the latch circuit 30 via the circuit.

The latch circuit 30 uses the bit synchronization pulse shown in FIG. 2(g) from the bit synchronization generation circuit 34 to cause the gate circuit 2
By holding the detection pulse from 9, an output corresponding to the type of data signal, that is, a demodulated signal, is sent to terminal 31.
~ Signal from 33. -Output as D2. The signal waveforms at this time are as shown in FIGS. 2(d) to 2(f). Signal here. represents the data signal rOJ rlJ, which is at the "L" level when the data signal is "0" and is at the "H" level when the data signal is "1". In addition, the signal D1Vi
, which indicates the arrival of a data signal, is at the "H" level when there is no signal, that is, when the data signal is "S", and is at the "L" level at other times. Furthermore, if the change in the signal D1 is to be held until the rise time of the non-data bear "NNJ" of the signal D2, as shown in the broken line part of the waveform shown in FIG. In this case, the data signal and the preamble “P
'' has the advantage of making the distinction clearer.

Signal D2 is a non-data pair “NN” which is special data.
”, and only when NNJ or rsJ
It becomes l level.

As mentioned above, here, the four types of data handled are "0", "1", "NN", and "S", but the data types and data signal types are not limited to these.
It is also possible to change the number of divisions within a bit, increase the number of bits, and add special data configurations to the types of data signals.

[Effects of the Invention] As detailed above, according to the present invention, the output /'P pulse of the receiving circuit is held directly in the first shift register, and is also inverted and held in the second shift register. rOJ of the data signals output from these shift registers
rlJ is detected by a matrix circuit, and rlJ corresponding to the output pulse of the receiving circuit that changes variously within one bit period of the data signal is detected via a gate circuit and a latch circuit.
Since it is demodulated into other special data signals, by including this special data in the data signal transmission format, it is easy to distinguish between necessary data and delimiters and preambles indicating the start and end of data. This improves the reliability of the data content during data transmission, and in order to obtain polar pairs of the modulated waveforms received by the two shift registers, even if the input to the registers is high speed. It is possible to provide a demodulation circuit that can perform high-speed data demodulation without creating a time difference between the outputs of both registers.

[Brief explanation of the drawing]

Figures 1 to 3 show an embodiment of this invention.
Figure 1 is a block diagram showing the circuit configuration, Figure 2 is a diagram showing signal waveforms at each part in Figure 1, Figure 3 is a diagram showing data types, their received waveforms, and output states, and Figure 4 is a diagram showing the conventional FIG. 5 is a block diagram showing the configuration of the demodulation circuit, and FIG. 5 is a diagram showing the signal waveform at the part numbered in the fourth figure. 11,'21...Input terminal, 12.22...Receiving circuit, 13.25...Synchronizing signal generation circuit, 14.24.
...Crystal oscillator, 15...Shift register, 17.3
1 to 33... Output terminal, 23... First shift register, 26... Inverter, 27... Second shift register, 28... Matrix circuit, 29... Gate circuit, 30 ...Latch circuit, 34...Bit synchronization generation circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 5 Procedural amendments Showa 2.1.2.2019

Claims (1)

[Claims] In a demodulation circuit that receives a signal modulated by switching a carrier wave in N cycles or N/2 cycles within 1 bit time by "0" and "1" of a digital data signal, 2 obtained from the synchronization signal that is synchronized with the received signal
A capture means for capturing the received signal into a multi-stage first shift register using a clock signal of N periods, and capturing an inverted received signal into a multi-stage second shift register; detection means consisting of a matrix circuit that detects "0" and "1" of data signals from the outputs of each stage of the first shift register and the second shift register; While detecting special data transferred at a special cycle, a bit synchronization signal of 1 bit time is generated, and the data signal is changed to "0" or "0".
1. A demodulation circuit comprising: a gate circuit for separating data into "1" and special data; and a holding means for holding the output of the gate circuit.