JPS59125143A - Asynchronous modulating and demodulating device - Google Patents

Abstract

PURPOSE:To transmit synchronous data with no synchronous clock by setting a counter after detecting the synchronous code of start and producing a shift signal when the counted value reaches a prescribed level. CONSTITUTION:The leading pad in the received data is supplied to a demodulating circuit 21 and then stored in a reception register 23 via a timing compensating circuit 22. When the leading pads are stored by an amount equivalent to one byte, they are transferred to a comparator 30 to be compared with the synchronous codes. Then a start signal is decided, and the comparator 30 delivers (b). At the same time, a bit counter 28 starts counting the bit number of the received data. When the data of 8 bits is stored in the register 23, the counter 28 delivers (h) and gives an indication to a control circuit 32 for transfer of data. In this case, the 8 bits of data of the register 23 are transferred to the circuit 32 through a bus 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a modem device (modem device) used when transmitting and receiving data using a telephone line or the like, and particularly to an asynchronous modem device that can transmit and receive synchronous signals.

1 to 4 show the transmission/reception system of a conventional modem device.

FIG. 1 is a diagram showing a transmission/reception system using an asynchronous modem. In FIG. 1, 1 is an input information terminal through which input information is input. 2 is an output information terminal that outputs output information. 3 is a terminal device that converts input information 1 into a digital signal and sends it to path 4, and converts the digital signal from path 5 to output information 2. An asynchronous modem 6 modulates the digital signal from the path 4 and sends it to a telephone line etc. 7, demodulates the signal from the telephone line etc. 7 into a digital signal and sends it to the path 5. Reference numeral 7 denotes a telephone line or the like through which modulated and demodulated signals go back and forth. 8 is an asynchronous modem which modulates the digital signal from the path 10 and sends it to the telephone line etc. 7, demodulates the signal from the telephone line etc. 7 into a digital signal and sends it to the path 9. 1 is a center device that data-processes the digital signal from the path 9 and sends it to the path 10.

First, input information is input to the input information terminal 1, converted into a digital signal by the terminal device 3, and sent through the path 4 to the asynchronous modem 6. The input information in the form of a digital signal is processed by the asynchronous modem 6, and the high frequency signal is processed by the central device 11 through a path 9 and output. This output digital signal is modulated by an asynchronous modem 8 from a path 10, passed through a telephone line 7, and demodulated by an asynchronous modem 6 to the original output digital signal. The digital signal output from the asynchronous modem 6 passes through a path 5 and is output from the output information terminal 2 by the terminal device 3 as output information. Note that the signals traveling back and forth on the telephone line 7 are obtained by modulating the asynchronous data shown in FIG. Here, 1 byte of asynchronous data is data 8
The start bit and stop bit are used to start and stop data transmission using the start bit and stop bit.

Figure 3 shows a conventional transmitting/receiving system using synchronous (DEM) output to the information terminal 2.The difference between the transmitting/receiving system in Figure 1 and the transmitting/receiving system in Figure 3 is the synchronous modem 12.14. In other words, the signals handled by the synchronous modem 12.14 are
As shown in the figure, there are two types of signals, and the modulated signal is sent to the telephone line 7.
transmitted to. FIG. 4 is a waveform diagram of the synchronous data 15 and synchronous clock 16 signals transmitted and received over the telephone line 7.

The difference between the asynchronous data in Figure 2 and the synchronous data in Figure 4 is that asynchronous data has a start bit and stop bit added to the data, but synchronous data does not have a start bit or stop bit; It uses synchronous black and white. This synchronized clock 16 is connected to path 4.5.9.
．． 10 is also transmitted simultaneously with the synchronization data 15.

In the asynchronous data transmission system shown in FIG. 2, two bits, a start bit and a stop bit, are added to the eight bits of data, so the data transmission speed is slow and inefficient. In the synchronous data transmission system shown in FIG. 4, the data is transmitted as 8 bits, so the transmission speed is improved, but since a synchronous clock is introduced, it is expensive.

As described above, both conventional asynchronous data and synchronous data transmission systems have their advantages and disadvantages and have been problematic.

OBJECTS OF THE INVENTION It is an object of the present invention to transmit only synchronous data without using a synchronous clock, thereby improving transmission speed and reducing costs.

Structure of the Invention An asynchronous modulation/demodulation device is equipped with a clock generator that divides data by 20 in an asynchronous modem, and after detecting a start synchronization code, samples the center of each bit using two counters. be.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram illustrating a portion of an asynchronous modem according to the present invention. First, the case of transmitting data will be described. 17 is a clock generator, which generates 2n (n
is an integer) and is used for the timing correction circuit 22 that synchronizes the received data and the clock, the quaternary counter 25, and the octal counter 26. 18 is a sending data bus, and 8-bit data is sent from the control circuit 32 to the sending shift register 19 via the sending data bus 18.
sent to. After the transmission data is accumulated in the transmission soft register 19, it is modulated by the modulation circuit 20 and sent to the terminal 7-1.
from there to the telephone line 7.

When receiving data next, the signal transmitted through the telephone line 7 in FIG. 1 is demodulated by the demodulation circuit 21 and reaches the timing correction circuit 22. The timing correction circuit 22 receives the demodulated signal from the demodulation circuit 21 and outputs it to the change detection section 24 and the reception register 23. The timing correction circuit 22 is
It functions to synchronize the rise and fall timing of the pulse signal of the received data with the pulse signal of the black and white generator 17.

The change detection section 24 receives the signal from the timing correction circuit 22 and outputs it to the quaternary counter 25 . Change detection section 24
Now, the change in the signal of the timing correction circuit 22 (0 → 1.1
→0), the clock generator 17 outputs a pulse corresponding to one cycle of the clock (FIG. 7d). Quaternary counter 25
When detecting the output pulse from the change detection section 24, it starts the clock pulse, and after four clock cycles of the clock generator 17, generates a pulse for one clock cycle (FIG. 7e). Reference numeral 26 denotes an octal counter, which starts clock counting when the output pulse of the quaternary counter 25 falls, and generates a pulse for one clock period in the eighth period of the clock (FIG. 7f). Quaternary count 25 and 8
The output of the advance counter 26 is logically summed by the OR circuit 27, and the output (FIG. 7g) is supplied to the reception l register 23, the bit color register 28, and the control circuit 32. With 23 receiving registers, one output pulse from the OR circuit 27 shifts the receiving register 23 by one stage. 28 is a bit counter,
OR, the output pulses of the circuit 27 are counted, and when the counted value is 8 bits, the output signal is sent to the control circuit 32 (see FIG. , and transferred to the control circuit 32.

FIG. 5 is a diagram showing the format of the synchronization data signal.

When transmitting synchronous data using an asynchronous modem, the data sampling timing is not output from the asynchronous modem when it is received, so there is a problem that the timing of data reception does not match. Synchronous data is to be transmitted using a specific synchronization code, including 5 bytes at the start (leading pad) and 2 bytes at the stop (trailing band) of data transmission, so in the present invention, after detecting this synchronization code, This is the one that has been modified to import data. Next, a circuit configuration for detecting a leading pad will be explained.

In FIG. 6, 29 is a synchronization code generation circuit, and this synchronization code generation circuit 29 generates signals for five start bytes and two stop bytes in the synchronization code. 3
0 is a comparator which compares 8 bits of data in the reception register 23 and 8 bits of the signal from the synchronization code generation circuit Z29. Once the comparator 30 determines that the received data is 5 bytes of a particular start, it generates a signal (FIG. 7b) that causes the bit counter 28 to begin counting 8 bits.

Next, the operation of this embodiment will be explained using the block diagram of FIG. 6 and the waveform diagram of FIG. 7. FIG. 7 is a diagram showing waveforms of signals at various parts in FIG. 6.

When the leading pad in the received data is input to the demodulation circuit 21, it is first stored in the reception register 23 via the timing correction circuit 22.

When one byte (8 bits) is accumulated, it is transferred to the comparator 30, which compares it with the signal from the synchronization code generation circuit 29, and if it is a signal indicating a start, it sequentially compares the next four bytes as well. . If the comparator 30 determines that the 5 bytes are a signal representing a start, it outputs the comparator output l) shown in FIG. Upon the output of the comparator, the bit counter 28 starts counting the number of bits of the received data. The portion after the start 5 bytes of the received data is the information content. If the received data C is "°1" after the output of the comparator output shown in FIG. Output.

This pulse d causes the quaternary counter 25 to start counting. After four cycles of clock a, that is, at timing t2 in FIG. 7, a quaternary count output e is generated. The output eu of the quaternary counter 25 passes through the OR circuit 27, and the data in the reception register 23 is shifted by one stage.

Next, when the received data C changes from 1'' to O'', the change detection section 24 outputs the pulse of the change detection section d in FIG. OR
A pulse g is output from the circuit 27, and the data in the reception register 23 is further shifted by one stage.

Further, when the received data C continues as °0" and "o", the change output unit 24 cannot detect the change, but instead the octal counter 26 detects a change of 8 at the timing 13 in FIG.
The output f of the digit counter is outputted, and the output g shown in FIG. 7 is outputted from the OR circuit 27. This pulse gK causes the data in the reception register 23 to be further shifted by one stage. Note 8
The base counter 26 is normally reset by the output C of the quaternary counter, and when there is no output e of the quaternary counter, as at timing 13 in FIG. 7, the output f of the octal counter is output. .

In this way, when eight bits of data are accumulated in the reception register 23, the bit counter 28 outputs the output 11 of the bit counter shown in FIG.
Instructs data transfer to.

At this time, the 8 bits of data in the reception register 23 are
The data is transferred to the control circuit 32 via the reception data bus 31.

As described above, when 1 byte (=8 bits) of received data is transferred to the control circuit 32, the next 1 byte is transferred in the same way, until the trailing pad in FIG. The data is successively transferred to the control circuit 32 in byte units. When the comparator 30 detects two bytes of the stop signal, reception ends.

Effects of the Invention The present invention has the above configuration, and according to the present invention, the following effects can be obtained.

The asynchronous modulation/demodulation device of the present invention detects bit-by-bit changes in received data, sets a counter with the detected signal, and generates a software signal when a predetermined count is reached. synchronous data can be transmitted. Therefore, since start bits and stop bits can be made unnecessary, highly accurate data transmission can be performed at low cost.

Kirani, the information content of the received data is all 1 byte, 0"
Alternatively, even if the signal is 1", it can be received by counting the counter.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a data transmission system using a conventional asynchronous modem, Figure 2 is a diagram showing the data content of one node used in the data transmission system of Figure 1 above, and Figure 3 is a diagram showing the conventional data transmission system. FIG. 4 is a block diagram showing the data transmission system using the synchronous modem of FIG. A diagram showing the structure of all bytes of synchronous data used, FIG. 6 is a block diagram of the main parts of an asynchronous modem in an embodiment of the present invention, and FIGS. It is. 4... Input terminal of asynchronous modem, 5... Output terminal of asynchronous modem, 7... Telephone line, 17... Clock generator, 2I - Demodulation circuit, 22... Timing correction circuit, 2
3...Receiving register, 24...Change detection section, 25...4
Decimal counter, 26...octal counter, 27...Ol
(.Circuit, 28...Bit counter, 29...Synchronization code generation circuit, 30...Comparator, 32...Control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 21

Claims (1)

[Claims] A clock generation circuit that generates 20 clocks for each pin of input received data, an n-ary counter that starts counting from the rising or falling edge of the received data and counts the clock, and counts the clock. An asynchronous modulation/demodulation device comprising a 2n-ary counter that is reset by the output of the n-ary counter, and a reception register that sequentially shifts the received data using the outputs of both counters.