JPS63198432A - Synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To attain the synchronizing communication of the HDLC system by oscillating a basic clock at the reception side, counting the basic clock synchronously with the reception data and generating a synchronizing clock synchronously with the reception data. CONSTITUTION:A reception data line 12 is constituted in such a way that the clock component for bit synchronization only whose transmission speed in the bit communication line using the HDLC system is not sent. A basic clock generating section 8 is provided to the reception side of the data line 12 and the generating section 8 generates a clock being several times of the transmission speed of the communication line. A basic clock number count section 9 counts the clock generated by the generating section 8, reset in the detection timing of a trailing detection section 10 of the received data and the clock synchronously with the received data is outputted to a synchronizing clock output line 11. Thus, the synchronizing communication of the HDLC system is applied even through a transmission line where the synchronizing clock component is not superimposingly sent.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronous clock generation circuit for a data communication receiver.

2. Description of the Related Art Conventionally, when performing data communication (using the HDLC system), it has been necessary to superimpose a synchronous clock on data and transmit it in order to obtain sample timing on the receiving side.

Problems to be Solved by the Invention However, the above-described conventional system has a problem in that the modulation rate required for the communication line is several times the transmission rate by superimposing a synchronous clock component on data.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to generate a synchronous clock on the receiving side so that HDLC communication can be realized using a communication line with the same modulation rate and transmission rate.

In order to achieve the above object, the present invention oscillates a basic clock on the receiving side and synchronizes the basic clock with the received data by counting. Generates a synchronous clock.

Effect: According to the present invention, it is possible to perform synchronous communication using the HDLC method even on a communication line that cannot transmit synchronous clock components.

EXAMPLES Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a data communication line suitable for implementing the present invention. In FIG. 1, 1 is a terminal device 1, 2 is a transmitter of the terminal device 1, 3 is a receiver of the terminal device 1, and 4-a
, 4-b is a data communication line, 5 is a terminal device 2, 6 is a receiving section of the terminal device 2, and 7 is a transmitting section of the terminal device 2.

FIG. 2 is a block diagram of a synchronous clock generation circuit to which the present invention is applied. In FIG. 2, 8 is a basic clock oscillation section, 9 is a basic clock number counting section 1o is a falling edge detection section of received data, 11 is a synchronous clock output line, 1
2 is a receiving data line, and 13 is a data receiving circuit.

FIG. 3 is a timing chart of various parts of the circuit of the present invention. In FIG. 3, (a) is the output signal of the basic clock oscillation section, (b) is the received data, (c) is the output of the falling edge detection section, and (b) is the output of the basic clock number counting section.

Since HDLC type communication is a bit synchronous type, a synchronous clock indicating the reception timing for each bit is required during reception. This synchronous clock is generally transmitted superimposed on communication data. However, it may not be possible to superimpose the synchronized clock on communication data due to limitations such as the performance of the modem used for communication and the characteristics of the transmission path. In this case, communication using the HDLC method is basically not possible. However, the HDLC method is far superior to other communication methods in many respects, such as bit error detection and flow control functions, and there are cases in which it is desirable to employ the HDLC method even when there are the aforementioned limitations. In such a case, the synchronous clock generation device of the present invention is required.

Hereinafter, the operation of the synchronous clock generation device of the present invention will be explained in detail.

First, the basic clock oscillator 8 generates a clock having a frequency sufficiently higher than the transmission speed of the received data (about 8 times or more). The clock generated by the basic clock generating section 8 is counted by the basic clock number counting section e to match the transmission speed of the received data, but simply counting does not synchronize with the received data. However, HDLC
The method has the following characteristics.

■ The beginning and end of the frame are 7 with “01111110”
It's a rug.

■ There are no more than six consecutive °1''s in areas other than flags.

Therefore, at the timing when the received data changes from °1 to °0, the basic clock count is reset and restarted at the same time. If this operation is carried out, the clock that generated the received data can always be synchronized at the beginning of the second frame due to the feature (2) above. In addition, due to the feature (■) above, it is possible to resynchronize the received data and clock once every 6 bits within 7 frames, so even if it is a long message frame, the received data can be clocked in the latter half of the frame. There is no possibility that the synchronization will be lost.

By generating a synchronized clock for reception using the above-described method, it becomes possible to perform communication using the HDLC method even when using a modem or a transmission line with the above-mentioned limitations.

Effects of the Invention By using the present invention, it becomes possible to perform bit-synchronized communication such as HDLC even on a transmission path where it is not possible to transmit communication data with a synchronized clock component superimposed thereon.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a data communication line suitable for carrying out the present invention, Fig. 2 is a block diagram of a synchronous clock generation circuit according to an embodiment of the invention, and Fig. 3 is a timing diagram of the synchronous clock generation circuit. It is a chart. 1...Terminal device, 1-2...Data transmitting section of terminal device 1, 3...Data receiving section of terminal device 1, 4-a. 4-b...data communication line, 6...terminal device 2.6...data receiving section of terminal device 2,
7... Data transmission section of the terminal device 2, 8...
...Basic clock oscillation section, 9...Basic clock number counting section, 10... Falling edge detection section of received data, 11... Synchronous clock output line, 12
......Receiving data line, 13...Data receiving circuit.

Claims (1)

[Claims] The transmission speed of a bit synchronization communication line using the HDLC method is limited.On the receiving side of a communication line that cannot simply transmit the clock component for bit synchronization, a basic clock oscillator with a speed several times the transmission speed of the previous communication line is used. The synchronous clock component consists of a basic clock number counting section, a reset section for clearing the basic clock count at the falling edge of received data, and a synchronous clock output section that outputs the counted basic clock in synchronization with the received data. 1. A synchronous clock generation circuit characterized in that a synchronous clock is generated from received data without a synchronous clock.