JP7707511B2 - ウェハ及びウェハの製造方法 - Google Patents

ウェハ及びウェハの製造方法

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Publication number
JP7707511B2
JP7707511B2 JP2021135446A JP2021135446A JP7707511B2 JP 7707511 B2 JP7707511 B2 JP 7707511B2 JP 2021135446 A JP2021135446 A JP 2021135446A JP 2021135446 A JP2021135446 A JP 2021135446A JP 7707511 B2 JP7707511 B2 JP 7707511B2
Authority
JP
Japan
Prior art keywords
region
conductive bumps
area
conductive
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021135446A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023030360A (ja
JP2023030360A5 (enExample
Inventor
研吾 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2021135446A priority Critical patent/JP7707511B2/ja
Priority to US17/816,805 priority patent/US20230054800A1/en
Priority to KR1020220099076A priority patent/KR20230029522A/ko
Priority to CN202210995634.XA priority patent/CN115910961A/zh
Publication of JP2023030360A publication Critical patent/JP2023030360A/ja
Publication of JP2023030360A5 publication Critical patent/JP2023030360A5/ja
Application granted granted Critical
Publication of JP7707511B2 publication Critical patent/JP7707511B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/1451—Function
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    • H01L2924/0133—Ternary Alloys

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JP2005093461A (ja) 2003-09-12 2005-04-07 Casio Comput Co Ltd 半導体基板、半導体基板の製造方法および半導体装置の製造方法
JP2007013063A (ja) 2005-07-04 2007-01-18 Fujitsu Ltd 半導体装置

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JP2003168700A (ja) 2001-09-18 2003-06-13 Seiko Epson Corp 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP2005093461A (ja) 2003-09-12 2005-04-07 Casio Comput Co Ltd 半導体基板、半導体基板の製造方法および半導体装置の製造方法
JP2007013063A (ja) 2005-07-04 2007-01-18 Fujitsu Ltd 半導体装置

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