JP7660075B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7660075B2
JP7660075B2 JP2021566372A JP2021566372A JP7660075B2 JP 7660075 B2 JP7660075 B2 JP 7660075B2 JP 2021566372 A JP2021566372 A JP 2021566372A JP 2021566372 A JP2021566372 A JP 2021566372A JP 7660075 B2 JP7660075 B2 JP 7660075B2
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transistor
oxide
circuit
conductor
insulator
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JPWO2021130591A5 (https=
JPWO2021130591A1 (https=
Inventor
達也 大貫
宗広 上妻
健 青木
隆徳 松嵜
佑樹 岡本
将志 太田
修平 長塚
寛司 國武
舜平 山崎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2025058192A priority Critical patent/JP7778264B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
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    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Mathematical Physics (AREA)
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  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2021566372A 2019-12-27 2020-12-14 半導体装置 Active JP7660075B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2025058192A JP7778264B2 (ja) 2019-12-27 2025-03-31 半導体装置
JP2025197409A JP2026027489A (ja) 2019-12-27 2025-11-18 半導体装置

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JP2019238710 2019-12-27
JP2019238710 2019-12-27
JP2020005295 2020-01-16
JP2020005295 2020-01-16
JP2020169003 2020-10-06
JP2020169003 2020-10-06
PCT/IB2020/061872 WO2021130591A1 (ja) 2019-12-27 2020-12-14 半導体装置

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JPWO2021130591A1 JPWO2021130591A1 (https=) 2021-07-01
JPWO2021130591A5 JPWO2021130591A5 (https=) 2023-12-06
JP7660075B2 true JP7660075B2 (ja) 2025-04-10

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JP2025058192A Active JP7778264B2 (ja) 2019-12-27 2025-03-31 半導体装置
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US (2) US12426313B2 (https=)
JP (3) JP7660075B2 (https=)
KR (1) KR20220120598A (https=)
CN (1) CN114902414A (https=)
DE (1) DE112020006360T5 (https=)
WO (1) WO2021130591A1 (https=)

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CN117094281B (zh) * 2023-10-19 2024-02-13 杭州行芯科技有限公司 获取热力学参数的方法、电子设备及存储介质

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008147340A (ja) 2006-12-08 2008-06-26 Nec Electronics Corp 半導体装置、半導体装置の製造方法、及びｓｒａｍセル
WO2019038664A1 (ja) 2017-08-25 2019-02-28 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2019033233A (ja) 2017-08-10 2019-02-28 株式会社半導体エネルギー研究所 半導体装置、および電子機器
JP2019036280A (ja) 2017-08-11 2019-03-07 株式会社半導体エネルギー研究所 グラフィックスプロセッシングユニット、コンピュータ、電子機器及び並列計算機
JP2019046199A (ja) 2017-09-01 2019-03-22 株式会社半導体エネルギー研究所 プロセッサ、および電子機器
JP2019047006A (ja) 2017-09-05 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、電子機器
JP2019153655A (ja) 2018-03-02 2019-09-12 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009277334A (ja) * 2008-04-14 2009-11-26 Hitachi Ltd 情報処理装置および半導体記憶装置
JP6001900B2 (ja) 2011-04-21 2016-10-05 株式会社半導体エネルギー研究所 信号処理回路
TWI536502B (zh) 2011-05-13 2016-06-01 半導體能源研究所股份有限公司 記憶體電路及電子裝置
KR101889383B1 (ko) * 2011-05-16 2018-08-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 프로그래머블 로직 디바이스
US8837203B2 (en) 2011-05-19 2014-09-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP6013682B2 (ja) 2011-05-20 2016-10-25 株式会社半導体エネルギー研究所 半導体装置の駆動方法
JP2013130802A (ja) 2011-12-22 2013-07-04 Semiconductor Energy Lab Co Ltd 半導体装置、画像表示装置、記憶装置、及び電子機器
JP6027898B2 (ja) 2012-01-23 2016-11-16 株式会社半導体エネルギー研究所 半導体装置
WO2013146154A1 (en) 2012-03-29 2013-10-03 Semiconductor Energy Laboratory Co., Ltd. Power supply control device
US9372694B2 (en) 2012-03-29 2016-06-21 Semiconductor Energy Laboratory Co., Ltd. Reducing data backup and recovery periods in processors
KR102107591B1 (ko) 2012-07-18 2020-05-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 기억 소자 및 프로그래머블 로직 디바이스
JP2014112213A (ja) 2012-10-30 2014-06-19 Semiconductor Energy Lab Co Ltd 表示装置の駆動方法
US9437273B2 (en) 2012-12-26 2016-09-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9786350B2 (en) 2013-03-18 2017-10-10 Semiconductor Energy Laboratory Co., Ltd. Memory device
US9172369B2 (en) 2013-05-17 2015-10-27 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device and semiconductor device
US8994430B2 (en) 2013-05-17 2015-03-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9406348B2 (en) 2013-12-26 2016-08-02 Semiconductor Energy Laboratory Co., Ltd. Memory cell including transistor and capacitor
JP6442321B2 (ja) 2014-03-07 2018-12-19 株式会社半導体エネルギー研究所 半導体装置及びその駆動方法、並びに電子機器
JP6580863B2 (ja) 2014-05-22 2019-09-25 株式会社半導体エネルギー研究所 半導体装置、健康管理システム
US10236884B2 (en) 2015-02-09 2019-03-19 Semiconductor Energy Laboratory Co., Ltd. Word line driver comprising NAND circuit
KR20170122771A (ko) 2015-02-26 2017-11-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 메모리 시스템 및 정보 처리 시스템
JP2016225614A (ja) * 2015-05-26 2016-12-28 株式会社半導体エネルギー研究所 半導体装置
US10490142B2 (en) 2016-01-29 2019-11-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic device
US10685614B2 (en) 2016-03-17 2020-06-16 Semiconductor Energy Laboratory Co., Ltd. Display device, display module, and electronic device
WO2018211349A1 (ja) 2017-05-19 2018-11-22 株式会社半導体エネルギー研究所 半導体装置
US11302726B2 (en) 2017-07-14 2022-04-12 Semiconductor Energy Laboratory Co., Ltd. Imaging device and electronic device
KR102396806B1 (ko) * 2017-08-31 2022-05-12 마이크론 테크놀로지, 인크 반도체 장치, 하이브리드 트랜지스터 및 관련 방법
US11139298B2 (en) 2017-09-06 2021-10-05 Semiconductor Energy Laboratory Co., Ltd. Electronic device
US10796221B2 (en) 2017-10-19 2020-10-06 General Electric Company Deep learning architecture for automated image feature extraction
JP2019164868A (ja) * 2018-03-20 2019-09-26 東芝メモリ株式会社 半導体記憶装置
WO2020031031A1 (ja) * 2018-08-09 2020-02-13 株式会社半導体エネルギー研究所 半導体装置および半導体装置の作製方法
US12002535B2 (en) 2019-09-20 2024-06-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising memory cell array and arithmetic circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008147340A (ja) 2006-12-08 2008-06-26 Nec Electronics Corp 半導体装置、半導体装置の製造方法、及びｓｒａｍセル
JP2019033233A (ja) 2017-08-10 2019-02-28 株式会社半導体エネルギー研究所 半導体装置、および電子機器
JP2019036280A (ja) 2017-08-11 2019-03-07 株式会社半導体エネルギー研究所 グラフィックスプロセッシングユニット、コンピュータ、電子機器及び並列計算機
WO2019038664A1 (ja) 2017-08-25 2019-02-28 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2019046199A (ja) 2017-09-01 2019-03-22 株式会社半導体エネルギー研究所 プロセッサ、および電子機器
JP2019047006A (ja) 2017-09-05 2019-03-22 株式会社半導体エネルギー研究所 半導体装置、電子機器
JP2019153655A (ja) 2018-03-02 2019-09-12 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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