JP7519248B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP7519248B2
JP7519248B2 JP2020157679A JP2020157679A JP7519248B2 JP 7519248 B2 JP7519248 B2 JP 7519248B2 JP 2020157679 A JP2020157679 A JP 2020157679A JP 2020157679 A JP2020157679 A JP 2020157679A JP 7519248 B2 JP7519248 B2 JP 7519248B2
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Japan
Prior art keywords
insulating layer
wiring
layer
reinforcing
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020157679A
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English (en)
Japanese (ja)
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JP2022051283A (ja
JP2022051283A5 (https=
Inventor
哲史 本藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2020157679A priority Critical patent/JP7519248B2/ja
Priority to US17/447,608 priority patent/US11688669B2/en
Publication of JP2022051283A publication Critical patent/JP2022051283A/ja
Publication of JP2022051283A5 publication Critical patent/JP2022051283A5/ja
Application granted granted Critical
Publication of JP7519248B2 publication Critical patent/JP7519248B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/657—Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2020157679A 2020-09-18 2020-09-18 配線基板及びその製造方法 Active JP7519248B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2020157679A JP7519248B2 (ja) 2020-09-18 2020-09-18 配線基板及びその製造方法
US17/447,608 US11688669B2 (en) 2020-09-18 2021-09-14 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020157679A JP7519248B2 (ja) 2020-09-18 2020-09-18 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2022051283A JP2022051283A (ja) 2022-03-31
JP2022051283A5 JP2022051283A5 (https=) 2023-03-31
JP7519248B2 true JP7519248B2 (ja) 2024-07-19

Family

ID=80740783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020157679A Active JP7519248B2 (ja) 2020-09-18 2020-09-18 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US11688669B2 (https=)
JP (1) JP7519248B2 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7841689B2 (ja) * 2022-03-17 2026-04-07 新光電気工業株式会社 配線基板及びその製造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243813A (ja) 2002-02-14 2003-08-29 Alps Electric Co Ltd 端子構造
JP2007317842A (ja) 2006-05-25 2007-12-06 Elpida Memory Inc プリント配線基板及びこれを用いた半導体パッケージ
JP2009016818A (ja) 2007-07-04 2009-01-22 Samsung Electro-Mechanics Co Ltd 多層印刷回路基板及びその製造方法
JP2009147053A (ja) 2007-12-13 2009-07-02 Elpida Memory Inc 半導体装置及びその製造方法
JP2012039197A (ja) 2010-08-04 2012-02-23 Canon Inc 電気機械変換装置及びその作製方法
JP2012156257A (ja) 2011-01-25 2012-08-16 Fujitsu Ltd 回路基板及び電子装置
JP2013074054A (ja) 2011-09-27 2013-04-22 Renesas Electronics Corp 電子装置、配線基板、及び、電子装置の製造方法
JP2017022190A (ja) 2015-07-08 2017-01-26 パナソニックＩｐマネジメント株式会社 実装構造体

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US20060076639A1 (en) * 2004-10-13 2006-04-13 Lypen William J Schottky diodes and methods of making the same
US7245025B2 (en) * 2005-11-30 2007-07-17 International Business Machines Corporation Low cost bonding pad and method of fabricating same
US7592710B2 (en) * 2006-03-03 2009-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure for wire bonding
US8183698B2 (en) * 2007-10-31 2012-05-22 Agere Systems Inc. Bond pad support structure for semiconductor device
US7993950B2 (en) * 2008-04-30 2011-08-09 Cavendish Kinetics, Ltd. System and method of encapsulation
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
JP5185885B2 (ja) 2009-05-21 2013-04-17 新光電気工業株式会社 配線基板および半導体装置
US20140054742A1 (en) * 2012-08-27 2014-02-27 Agency For Science, Technology And Research Semiconductor Structure
US9349700B2 (en) * 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
KR20150058778A (ko) * 2013-11-21 2015-05-29 삼성전자주식회사 반도체 장치 및 그 제조 방법, 상기 반도체 장치를 포함하는 반도체 패키지 및 그 제조 방법
US10163661B2 (en) * 2015-06-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9871009B2 (en) * 2016-06-15 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN110634852B (zh) * 2018-06-21 2021-06-25 群创光电股份有限公司 半导体装置
US10886260B2 (en) * 2018-09-07 2021-01-05 Innolux Corporation Display device
US10872842B2 (en) * 2019-02-25 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US11289802B2 (en) * 2019-04-08 2022-03-29 Apple Inc. Millimeter wave impedance matching structures
US11670608B2 (en) * 2019-09-27 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Prevention of metal pad corrosion due to exposure to halogen
US11244914B2 (en) * 2020-05-05 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad with enhanced reliability
US11545450B2 (en) * 2020-07-16 2023-01-03 Nvidia Corporation Interlocked redistribution layer interface for flip-chip integrated circuits

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243813A (ja) 2002-02-14 2003-08-29 Alps Electric Co Ltd 端子構造
JP2007317842A (ja) 2006-05-25 2007-12-06 Elpida Memory Inc プリント配線基板及びこれを用いた半導体パッケージ
JP2009016818A (ja) 2007-07-04 2009-01-22 Samsung Electro-Mechanics Co Ltd 多層印刷回路基板及びその製造方法
JP2009147053A (ja) 2007-12-13 2009-07-02 Elpida Memory Inc 半導体装置及びその製造方法
JP2012039197A (ja) 2010-08-04 2012-02-23 Canon Inc 電気機械変換装置及びその作製方法
JP2012156257A (ja) 2011-01-25 2012-08-16 Fujitsu Ltd 回路基板及び電子装置
JP2013074054A (ja) 2011-09-27 2013-04-22 Renesas Electronics Corp 電子装置、配線基板、及び、電子装置の製造方法
JP2017022190A (ja) 2015-07-08 2017-01-26 パナソニックＩｐマネジメント株式会社 実装構造体

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Publication number Publication date
US20220093493A1 (en) 2022-03-24
JP2022051283A (ja) 2022-03-31
US11688669B2 (en) 2023-06-27

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