JP7484700B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP7484700B2 JP7484700B2 JP2020214119A JP2020214119A JP7484700B2 JP 7484700 B2 JP7484700 B2 JP 7484700B2 JP 2020214119 A JP2020214119 A JP 2020214119A JP 2020214119 A JP2020214119 A JP 2020214119A JP 7484700 B2 JP7484700 B2 JP 7484700B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- conductive member
- heat
- thermal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 249
- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000007789 sealing Methods 0.000 claims description 38
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 230000020169 heat generation Effects 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 229910002804 graphite Inorganic materials 0.000 description 5
- 239000010439 graphite Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000002470 thermal conductor Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
開示の技術の実施例について以下に説明する。下記の表1に示す実施例1~3及び比較例に係るサンプルを作製し、第1の半導体チップ11A、11B及び第2の半導体チップ12を発熱させたときの、各半導体チップの温度を測定した。各サンプルにおいて、第1の半導体チップ11A、11Bの発熱量を10Wとし、第2の半導体チップ12の発熱量を0.1Wとした。また、各サンプルにおいて、第2の熱伝導部材22として使用した材料は全て同じであり、グラファイトシート(パナソニック製 TC2XY=1500W/m・k、TC2Z=5W/m・k)を使用した。
第1の半導体チップと、
前記第1の半導体チップよりも発熱量の小さい第2の半導体チップと、
前記第1の半導体チップの少なくとも一部の上層に配置された第1の熱伝導部材と、
前記第2の半導体チップの上層及び前記第1の熱伝導部材の周囲に配置された第2の熱伝導部材と、
前記第2の熱伝導部材の上層で、前記第1の半導体チップ及び前記第2の半導体チップが並ぶ方向である平面方向に沿って配置された放熱部材と、
を含み、
前記第1の熱伝導部材の熱伝導率は、前記第2の熱伝導部材の前記平面方向における熱伝導率よりも低い
半導体装置。
前記第2の熱伝導部材は、前記平面方向と交差する方向である高さ方向における熱伝導率が、前記平面方向における熱伝導率よりも低い
付記1に記載の半導体装置。
前記第2の熱伝導部材の前記高さ方向における熱伝導率は、前記第1の熱伝導部材の熱伝導率よりも低い
付記2に記載の半導体装置。
前記第1の熱伝導部材の上層の、前記第2の熱伝導部材の厚さが1mm以下である
付記3に記載の半導体装置。
前記第1の半導体チップ及び前記第2の半導体チップを封止する封止部材を更に含み、
前記第1の熱伝導部材は、前記封止部材から露出した前記第1の半導体チップの上層に配置されており、
前記第2の熱伝導部材は、前記封止部材から露出した前記第2の半導体チップの上層に配置されている
付記1から付記4のいずれか1つに記載の半導体装置。
前記第1の半導体チップと前記第2の半導体チップとを電気的に接続する再配線層を更に含む
付記1から付記5のいずれか1つに記載の半導体装置。
前記第1の半導体チップは単結晶シリコンからなる基板を有し、前記第2の半導体チップは化合物半導体からなる基板を有する
付記1から付記6のいずれか1つに記載の半導体装置。
前記第2の熱伝導部材は、グラファイトシートである
付記1から付記7のいずれか1つに記載の半導体装置。
第1の半導体チップ及び前記第1の半導体チップよりも発熱量の小さい第2の半導体チップを封止部材で封止する工程と、
前記封止部材を研削して前記第1の半導体チップ及び前記第2の半導体チップの表面を前記封止部材から露出させる工程と、
前記第1の半導体チップの前記封止部材から露出した上層に第1の熱伝導部材を配置する工程と、
前記第2の半導体チップの前記封止部材から露出した上層及び前記第1の熱伝導部材の周囲に第2の熱伝導部材を配置する工程と、
前記第2の熱伝導部材の上層で、前記第1の半導体チップ及び前記第2の半導体チップが並ぶ方向である平面方向に沿って放熱部材を配置する工程と、
を含み、
前記第1の熱伝導部材の熱伝導率は、前記平面方向における熱伝導率よりも低い
半導体装置の製造方法。
11A、11B 第1の半導体チップ
12 第2の半導体チップ
21 第1の熱伝導部材
22 第2の熱伝導部材
30 封止部材
40 再配線層
41 配線
50 放熱部材
Claims (7)
- 第1の半導体チップと、
前記第1の半導体チップよりも発熱量の小さい第2の半導体チップと、
前記第1の半導体チップの少なくとも一部の上層に配置された第1の熱伝導部材と、
前記第2の半導体チップの上層及び前記第1の熱伝導部材の周囲に配置された第2の熱伝導部材と、
前記第2の熱伝導部材の上層で、前記第1の半導体チップ及び前記第2の半導体チップが並ぶ方向である平面方向に沿って配置された放熱部材と、
を含み、
前記第1の熱伝導部材の熱伝導率は、前記第2の熱伝導部材の、前記平面方向における熱伝導率よりも低い
半導体装置。 - 前記第2の熱伝導部材は、前記平面方向と交差する方向である高さ方向における熱伝導率が、前記平面方向における熱伝導率よりも低い
請求項1に記載の半導体装置。 - 前記第2の熱伝導部材の前記高さ方向における熱伝導率は、前記第1の熱伝導部材の熱伝導率よりも低い
請求項2に記載の半導体装置。 - 前記第1の熱伝導部材の上層の、前記第2の熱伝導部材の厚さが1mm以下である
請求項3に記載の半導体装置。 - 前記第1の半導体チップ及び前記第2の半導体チップを封止する封止部材を更に含み、
前記第1の熱伝導部材は、前記封止部材から露出した前記第1の半導体チップの表面を覆っており、
前記第2の熱伝導部材は、前記封止部材から露出した前記第2の半導体チップの表面を覆っている
請求項1から請求項4のいずれか1項に記載の半導体装置。 - 前記第1の半導体チップと前記第2の半導体チップとを電気的に接続する再配線層を更に含む
請求項1から請求項5のいずれか1項に記載の半導体装置。 - 第1の半導体チップ及び前記第1の半導体チップよりも発熱量の小さい第2の半導体チップを封止部材で封止する工程と、
前記封止部材を研削して前記第1の半導体チップ及び前記第2の半導体チップの表面を前記封止部材から露出させる工程と、
前記第1の半導体チップの前記封止部材から露出した上層に第1の熱伝導部材を配置する工程と、
前記第2の半導体チップの前記封止部材から露出した上層及び前記第1の熱伝導部材の周囲に第2の熱伝導部材を配置する工程と、
前記第2の熱伝導部材の上層で、前記第1の半導体チップ及び前記第2の半導体チップが並ぶ方向である平面方向に沿って放熱部材を配置する工程と、
を含み、
前記第1の熱伝導部材の熱伝導率は、前記平面方向における熱伝導率よりも低い
半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020214119A JP7484700B2 (ja) | 2020-12-23 | 2020-12-23 | 半導体装置及び半導体装置の製造方法 |
US17/478,991 US11837520B2 (en) | 2020-12-23 | 2021-09-20 | Semiconductor device and semiconductor device fabrication method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020214119A JP7484700B2 (ja) | 2020-12-23 | 2020-12-23 | 半導体装置及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2022100009A JP2022100009A (ja) | 2022-07-05 |
JP7484700B2 true JP7484700B2 (ja) | 2024-05-16 |
Family
ID=82023389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020214119A Active JP7484700B2 (ja) | 2020-12-23 | 2020-12-23 | 半導体装置及び半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US11837520B2 (ja) |
JP (1) | JP7484700B2 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000232284A (ja) | 1998-12-10 | 2000-08-22 | Fujitsu Ltd | 電子機器筐体及びそれに用いる熱伝導パス部材 |
JP2004273570A (ja) | 2003-03-05 | 2004-09-30 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
JP2017103433A (ja) | 2015-12-04 | 2017-06-08 | トヨタ自動車株式会社 | 半導体装置 |
JP7321257B2 (ja) | 2018-10-26 | 2023-08-04 | ザ ケマーズ カンパニー エフシー リミテッド ライアビリティ カンパニー | ジフルオロメタン、テトラフルオロプロペン、及び二酸化炭素を含有する組成物、並びにその使用 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0945827A (ja) | 1995-08-02 | 1997-02-14 | Hitachi Ltd | 半導体装置 |
JP5779042B2 (ja) | 2011-08-18 | 2015-09-16 | 新光電気工業株式会社 | 半導体装置 |
TWI584428B (zh) * | 2016-06-08 | 2017-05-21 | 力成科技股份有限公司 | 降低封裝翹曲之散熱型半導體封裝構造 |
KR20210059470A (ko) * | 2019-11-15 | 2021-05-25 | 삼성전자주식회사 | 반도체 패키지 및 PoP 타입 패키지 |
EP3920467B1 (en) * | 2020-06-04 | 2024-09-18 | Fujitsu Limited | Communication coupling verification method, communication coupling verification program, and network verification apparatus |
US11750383B2 (en) * | 2021-03-31 | 2023-09-05 | Fujitsu Limited | Multi-level access control in sharing of vehicle data with devices |
KR20230037987A (ko) * | 2021-09-10 | 2023-03-17 | 삼성전자주식회사 | 반도체 패키지 |
KR20230086107A (ko) * | 2021-12-08 | 2023-06-15 | 엘지디스플레이 주식회사 | 디스플레이 장치 |
KR20230100028A (ko) * | 2021-12-28 | 2023-07-05 | 삼성전자주식회사 | 반도체 패키지 |
KR20230100158A (ko) * | 2021-12-28 | 2023-07-05 | 삼성전자주식회사 | 반도체 패키지 |
-
2020
- 2020-12-23 JP JP2020214119A patent/JP7484700B2/ja active Active
-
2021
- 2021-09-20 US US17/478,991 patent/US11837520B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000232284A (ja) | 1998-12-10 | 2000-08-22 | Fujitsu Ltd | 電子機器筐体及びそれに用いる熱伝導パス部材 |
JP2004273570A (ja) | 2003-03-05 | 2004-09-30 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
JP2017103433A (ja) | 2015-12-04 | 2017-06-08 | トヨタ自動車株式会社 | 半導体装置 |
JP7321257B2 (ja) | 2018-10-26 | 2023-08-04 | ザ ケマーズ カンパニー エフシー リミテッド ライアビリティ カンパニー | ジフルオロメタン、テトラフルオロプロペン、及び二酸化炭素を含有する組成物、並びにその使用 |
Also Published As
Publication number | Publication date |
---|---|
JP2022100009A (ja) | 2022-07-05 |
US11837520B2 (en) | 2023-12-05 |
US20220199487A1 (en) | 2022-06-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110060992B (zh) | 半导体封装 | |
US10347611B2 (en) | Semiconductor packages having redistribution substrate | |
US10062665B2 (en) | Semiconductor packages with thermal management features for reduced thermal crosstalk | |
US10269668B2 (en) | System and method for bonding package lid | |
TWI613774B (zh) | 功率覆蓋結構及其製造方法 | |
TWI573223B (zh) | 空腔基板保護之積體電路 | |
JP6122863B2 (ja) | 複数の熱経路を備える積み重ねられた半導体ダイアセンブリ、ならびに関連するシステムおよび方法 | |
US8520388B2 (en) | Heat-radiating component and electronic component device | |
US10937771B2 (en) | Semiconductor packages | |
KR101069499B1 (ko) | 반도체 디바이스 및 그 제조 방법 | |
US9859266B2 (en) | Method of forming 3D integrated circuit package with panel type lid | |
US20200152557A1 (en) | Package structure and packaging process | |
US11640930B2 (en) | Semiconductor package having liquid-cooling lid | |
US20220384286A1 (en) | Chip package structure with heat conductive layer | |
JP6457206B2 (ja) | 半導体パッケージ及びその製造方法 | |
CN115312406A (zh) | 芯片封装结构及制备方法 | |
US11488887B1 (en) | Thermal enablement of dies with impurity gettering | |
JP4919689B2 (ja) | モジュール基板 | |
JP7484700B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
KR102492530B1 (ko) | 열 방출 소자, 이를 포함하는 반도체 패키지 및 반도체 소자 | |
US10236227B2 (en) | Electronic package and fabrication method thereof | |
JP6712051B2 (ja) | 半導体装置、半導体装置の製造方法及び電子装置 | |
KR102717855B1 (ko) | 반도체 패키지 | |
US11557526B2 (en) | Substrates for semiconductor device assemblies and systems with improved thermal performance and methods for making the same | |
TW202310244A (zh) | 包括直接接觸熱路徑之設備及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20230608 |
|
TRDD | Decision of grant or rejection written | ||
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20240328 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20240402 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20240415 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7484700 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |